Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main

wally-pipelined/src/mmu/tlb.sv

@@ -89,10 +89,6 @@ module tlb #(parameter TLB_ENTRIES = 8,
   output logic             TLBPageFault
 );
 
-  // Store current virtual memory mode (SV32, SV39, SV48, ect...)
-  //logic [`SVMODE_BITS-1:0] SvMode;
-  logic  [1:0]       EffectivePrivilegeMode; // privilege mode, possibly modified by MPRV
-
   logic [TLB_ENTRIES-1:0] ReadLines, WriteEnables, PTE_G; // used as the one-hot encoding of WriteIndex
 
   // Sections of the virtual and physical addresses
@@ -113,19 +109,14 @@ module tlb #(parameter TLB_ENTRIES = 8,
 
   tlbcontrol tlbcontrol(.SATP_REGW, .Address, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
                         .PrivilegeModeW, .ReadAccess, .WriteAccess, .DisableTranslation, .TLBFlush,
-                        .PTEAccessBits, .CAMHit, .TLBMiss, .TLBHit, .TLBPageFault, .EffectivePrivilegeMode,
+                        .PTEAccessBits, .CAMHit, .TLBMiss, .TLBHit, .TLBPageFault, 
                         .SV39Mode, .Translate);
 
-  // TLB entries are evicted according to the LRU algorithm
   tlblru #(TLB_ENTRIES) lru(.clk, .reset, .TLBWrite, .TLBFlush, .ReadLines, .CAMHit, .WriteEnables);
-
-  //  tlbram #(TLB_ENTRIES) tlbram(.*);
-  tlbram #(TLB_ENTRIES) tlbram(.clk, .reset, .PTE, .ReadLines, .WriteEnables, .PhysicalPageNumber, .PTEAccessBits, .PTE_G);
-
-  // tlbcam #(TLB_ENTRIES, `VPN_BITS + `ASID_BITS, `VPN_SEGMENT_BITS) tlbcam(.*);
   tlbcam #(TLB_ENTRIES, `VPN_BITS + `ASID_BITS, `VPN_SEGMENT_BITS) 
     tlbcam(.clk, .reset, .VirtualPageNumber, .PageTypeWriteVal, .SV39Mode, .TLBFlush, .WriteEnables, .PTE_G, 
            .ASID(SATP_REGW[`ASID_BASE+`ASID_BITS-1:`ASID_BASE]), .ReadLines, .HitPageType, .CAMHit);
+  tlbram #(TLB_ENTRIES) tlbram(.clk, .reset, .PTE, .ReadLines, .WriteEnables, .PhysicalPageNumber, .PTEAccessBits, .PTE_G);
 
   // Replace segments of the virtual page number with segments of the physical
   // page number. For 4 KB pages, the entire virtual page number is replaced.

wally-pipelined/src/mmu/tlbcam.sv

@@ -54,11 +54,10 @@ module tlbcam #(parameter TLB_ENTRIES = 8,
   // page number segments.
 
   tlbcamline #(KEY_BITS, SEGMENT_BITS) camlines[TLB_ENTRIES-1:0](
-    .WriteEnable(WriteEnables),
-    .PageTypeRead, // *** change name to agree
-    .Match(ReadLines), // *** change name to agree
-    .*);
+    .clk, .reset, .VirtualPageNumber, .ASID, .SV39Mode, .PTE_G, .PageTypeWriteVal, .TLBFlush,
+    .WriteEnable(WriteEnables), .PageTypeRead, .Match(ReadLines));
   assign CAMHit = |ReadLines & ~TLBFlush;
   assign HitPageType = PageTypeRead.or; // applies OR to elements of the (TLB_ENTRIES x 2) array to get 2-bit result
 
 endmodule
+

wally-pipelined/src/mmu/tlbcontrol.sv

@@ -48,14 +48,14 @@ module tlbcontrol #(parameter TLB_ENTRIES = 8,
   output logic             TLBMiss,
   output logic             TLBHit,
   output logic             TLBPageFault,
-  output logic [1:0]       EffectivePrivilegeMode,
   output logic             SV39Mode,
   output logic             Translate
 );
 
   // Sections of the page table entry
-  logic [11:0]          PageOffset;
+  logic [11:0]             PageOffset;
   logic [`SVMODE_BITS-1:0] SVMode;
+  logic [1:0]              EffectivePrivilegeMode;
 
   logic PTE_D, PTE_A, PTE_U, PTE_X, PTE_W, PTE_R; // Useful PTE Control Bits
   logic                  UpperBitsUnequalPageFault;