forked from Github_Repos/cvw
Added d cache StallW checks for any time the cache wants to go to STATE_READY.
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9
wally-pipelined/src/cache/dcache.sv
vendored
9
wally-pipelined/src/cache/dcache.sv
vendored
@ -485,8 +485,9 @@ module dcache
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SRAMWordWriteEnableM = 1'b1; // pipelined 1 cycle
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end
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STATE_AMO_WRITE: begin
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NextState = STATE_READY;
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SelAMOWrite = 1'b1;
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if(StallW) NextState = STATE_CPU_BUSY;
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else NextState = STATE_READY;
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end
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STATE_MISS_FETCH_WDV: begin
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@ -540,17 +541,19 @@ module dcache
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STATE_MISS_READ_WORD_DELAY: begin
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SelAdrM = 1'b1;
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NextState = STATE_READY;
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CommittedM = 1'b1;
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if(StallW) NextState = STATE_CPU_BUSY;
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else NextState = STATE_READY;
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end
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STATE_MISS_WRITE_WORD: begin
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SRAMWordWriteEnableM = 1'b1;
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SetDirtyM = 1'b1;
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SelAdrM = 1'b1;
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NextState = STATE_READY;
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DCacheStall = 1'b0;
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CommittedM = 1'b1;
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if(StallW) NextState = STATE_CPU_BUSY;
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else NextState = STATE_READY;
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end
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STATE_MISS_EVICT_DIRTY: begin
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