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Added d cache StallW checks for any time the cache wants to go to STATE_READY.

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This commit is contained in:
Ross Thompson 2021-07-14 17:25:50 -05:00
parent 2c946a282f
commit c79650b508
1 changed files with 6 additions and 3 deletions
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9
wally-pipelined/src/cache/dcache.sv vendored
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@ -485,8 +485,9 @@ module dcache
SRAMWordWriteEnableM = 1'b1; // pipelined 1 cycle
end
STATE_AMO_WRITE: begin
NextState = STATE_READY;
SelAMOWrite = 1'b1;
if(StallW) NextState = STATE_CPU_BUSY;
else NextState = STATE_READY;
end
STATE_MISS_FETCH_WDV: begin
@ -540,17 +541,19 @@ module dcache
STATE_MISS_READ_WORD_DELAY: begin
SelAdrM = 1'b1;
NextState = STATE_READY;
CommittedM = 1'b1;
if(StallW) NextState = STATE_CPU_BUSY;
else NextState = STATE_READY;
end
STATE_MISS_WRITE_WORD: begin
SRAMWordWriteEnableM = 1'b1;
SetDirtyM = 1'b1;
SelAdrM = 1'b1;
NextState = STATE_READY;
DCacheStall = 1'b0;
CommittedM = 1'b1;
if(StallW) NextState = STATE_CPU_BUSY;
else NextState = STATE_READY;
end
STATE_MISS_EVICT_DIRTY: begin