Fixed back to back store issue.

Note there is a bug in the lsuarb which needs to arbitrate a few execution stage signals.

wally-pipelined/src/cache/dcache.sv

@@ -34,9 +34,11 @@ module dcache
    input logic 		       FlushW,
 
    // cpu side
+   input logic [1:0] 	       MemRWE,
    input logic [1:0] 	       MemRWM,
    input logic [2:0] 	       Funct3M,
    input logic [6:0] 	       Funct7M,
+   input logic [1:0] 	       AtomicE, 
    input logic [1:0] 	       AtomicM,
    input logic [`XLEN-1:0]     MemAdrE, // virtual address, but we only use the lower 12 bits.
    input logic [`PA_BITS-1:0]  MemPAdrM, // physical address
@@ -299,6 +301,7 @@ module dcache
   // control path *** eventually move to own module.
 
   logic AnyCPUReqM;
+  logic AnyCPUReqE;
   logic FetchCountFlag;
   logic PreCntEn;
   logic CntEn;
@@ -349,6 +352,7 @@ module dcache
   
 
   assign AnyCPUReqM = |MemRWM | (|AtomicM);
+  assign AnyCPUReqE = |MemRWE | (|AtomicE);  
   assign FetchCountFlag = (FetchCount == FetchCountThreshold[LOGWPL:0]);
 
   flopenr #(LOGWPL+1) 
@@ -406,7 +410,7 @@ module dcache
     case (CurrState)
       STATE_READY: begin
 	// sram busy
-	if (AnyCPUReqM & SRAMWordWriteEnableW) begin
+	if (AnyCPUReqE & SRAMWordWriteEnableM) begin
 	  NextState = STATE_SRAM_BUSY;
 	  DCacheStall = 1'b1;
 	end
@@ -505,11 +509,16 @@ module dcache
       end
 
       STATE_MISS_WRITE_WORD: begin
-	DCacheStall = 1'b0;
 	SRAMWordWriteEnableM = 1'b1;
 	SetDirtyM = 1'b1;
-	NextState = STATE_READY;
 	SelAdrM = 1'b1;
+	if (AnyCPUReqE & SRAMWordWriteEnableM) begin
+	  NextState = STATE_SRAM_BUSY;
+	  DCacheStall = 1'b1;
+	end else begin
+	  NextState = STATE_READY;
+	  DCacheStall = 1'b0;
+	end
       end
 
       STATE_MISS_EVICT_DIRTY: begin

wally-pipelined/src/ieu/controller.sv

@@ -52,6 +52,7 @@ module controller(
   output logic [1:0] MemRWM,
   output logic       CSRReadM, CSRWriteM, PrivilegedM,
   output logic       SCE,
+  output logic [1:0] AtomicE,
   output logic [1:0] AtomicM,
   output logic [2:0] Funct3M,
   output logic       RegWriteM,     // for Hazard Unit
@@ -84,7 +85,7 @@ module controller(
   logic       TargetSrcD, W64D, MulDivD;
   logic       CSRZeroSrcD;
   logic       CSRReadD;
-  logic [1:0] AtomicD, AtomicE;
+  logic [1:0] AtomicD;
   logic       CSRWriteD, CSRWriteE;
   logic       InstrValidD, InstrValidE;
   logic       PrivilegedD, PrivilegedE;

wally-pipelined/src/ieu/ieu.sv

@@ -47,7 +47,9 @@ module ieu (
   // Memory stage interface
   input logic 		   DataMisalignedM, // from LSU
   input logic 		   SquashSCW, // from LSU
+  output logic [1:0] 	   MemRWE, // read/write control goes to LSU	    
   output logic [1:0] 	   MemRWM, // read/write control goes to LSU
+  output logic [1:0] 	   AtomicE, // atomic control goes to LSU	    
   output logic [1:0] 	   AtomicM, // atomic control goes to LSU
   output logic [`XLEN-1:0] MemAdrM, MemAdrE, WriteDataM, // Address and write data to LSU
 
@@ -86,7 +88,6 @@ module ieu (
   logic             RegWriteM, RegWriteW;
   logic             MemReadE, CSRReadE;
   logic             JumpE;
-  logic [1:0]       MemRWE;
            
   controller c(.*);
   datapath   dp(.*);             

wally-pipelined/src/lsu/lsu.sv

@@ -37,9 +37,11 @@ module lsu
 
    // connected to cpu (controls)
    input logic [1:0] 	       MemRWM,
+   input logic [1:0] 	       MemRWE, 
    input logic [2:0] 	       Funct3M,
    input logic [6:0] 	       Funct7M, 
    input logic [1:0] 	       AtomicM,
+   input logic [1:0] 	       AtomicE,   
    output logic 	       CommittedM, 
    output logic 	       SquashSCW,
    output logic 	       DataMisalignedM,
@@ -299,10 +301,12 @@ module lsu
 		.StallW(StallW),
 		.FlushM(FlushM),
 		.FlushW(FlushW),
+		.MemRWE(MemRWE),		 // *** add to arb
 		.MemRWM(MemRWMtoDCache),
 		.Funct3M(Funct3MtoDCache),
 		.Funct7M(Funct7M),		
 		.AtomicM(AtomicMtoDCache),
+		.AtomicE(AtomicE),	    // *** add to arb
 		.MemAdrE(MemAdrEtoDCache),  // *** add to arb
 		.MemPAdrM(MemPAdrM),
 		.WriteDataM(WriteDataM),

wally-pipelined/src/wally/wallypipelinedhart.sv

@@ -63,6 +63,7 @@ module wallypipelinedhart
   // new signals that must connect through DP
   logic 		    MulDivE, W64E;
   logic 		    CSRReadM, CSRWriteM, PrivilegedM;
+  logic [1:0] 		    AtomicE;
   logic [1:0] 		    AtomicM;
   logic [`XLEN-1:0] 	    SrcAE, SrcBE;
   logic [`XLEN-1:0] 	    SrcAM;
@@ -73,6 +74,7 @@ module wallypipelinedhart
   logic [`XLEN-1:0] 	    PCTargetE;
   logic [`XLEN-1:0] 	    CSRReadValW, MulDivResultW;
   logic [`XLEN-1:0] 	    PrivilegedNextPCM;
+  logic [1:0] 		    MemRWE;  
   logic [1:0] 		    MemRWM;
   logic 		    InstrValidM, InstrValidW;
   logic 		    InstrMisalignedFaultM;
@@ -174,9 +176,11 @@ module wallypipelinedhart
 	  .StallW(StallW),
 	  .FlushW(FlushW),
 	  // CPU interface
+	  .MemRWE(MemRWE),                  	  
 	  .MemRWM(MemRWM),                  
 	  .Funct3M(Funct3M),
 	  .Funct7M(InstrM[31:25]),
+	  .AtomicE(AtomicE),
 	  .AtomicM(AtomicM),               
 	  .CommittedM(CommittedM),          
 	  .SquashSCW(SquashSCW),