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Fixed interaction between icache stall and dcache. On hit dcache needs to enter a cpu busy state when the cpu is stalled.

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This commit is contained in:
Ross Thompson 2021-07-13 14:51:42 -05:00
parent 3c1a717399
commit baa2b5d15f
2 changed files with 9 additions and 3 deletions
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6
wally-pipelined/regression/wave.do
View File

@ -394,8 +394,8 @@ add wave -noupdate /testbench/dut/uncore/dtim/risingHREADYTim
add wave -noupdate /testbench/dut/uncore/dtim/memwrite
add wave -noupdate /testbench/dut/uncore/dtim/HWDATA
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 12} {1303743 ns} 0} {{Cursor 4} {1304324 ns} 0} {{Cursor 5} {1303977 ns} 0}
quietly wave cursor active 1
WaveRestoreCursors {{Cursor 12} {1978950 ns} 0} {{Cursor 4} {1979605 ns} 0} {{Cursor 5} {2053811 ns} 0}
quietly wave cursor active 2
configure wave -namecolwidth 250
configure wave -valuecolwidth 297
configure wave -justifyvalue left
@ -410,4 +410,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {1303670 ns} {1304014 ns}
WaveRestoreZoom {1979564 ns} {1979828 ns}

6
wally-pipelined/src/cache/dcache.sv vendored
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@ -401,11 +401,17 @@ module dcache
else if(|AtomicM & ~UncachedM & ~FaultM & CacheHit & ~DTLBMissM) begin
NextState = STATE_AMO_UPDATE;
DCacheStall = 1'b1;
if(StallW) NextState = STATE_CPU_BUSY;
else NextState = STATE_READY;
end
// read hit valid cached
else if(MemRWM[1] & ~UncachedM & ~FaultM & CacheHit & ~DTLBMissM) begin
NextState = STATE_READY;
DCacheStall = 1'b0;
if(StallW) NextState = STATE_CPU_BUSY;
else NextState = STATE_READY;
end
// write hit valid cached
else if (MemRWM[0] & ~UncachedM & ~FaultM & CacheHit & ~DTLBMissM) begin