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hptw: minor cleanup

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This commit is contained in:
David Harris 2021-07-17 13:40:12 -04:00
parent ea2aa469a1
commit 87aa527de7
6 changed files with 9 additions and 15 deletions
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1
wally-pipelined/regression/wally-busybear-batch.do
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@ -32,7 +32,6 @@ vlog -work work_busybear +incdir+../config/busybear +incdir+../config/shared ..
# start and run simulation
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
vopt work_busybear.testbench -o workopt_busybear
vsim workopt_busybear -suppress 8852,12070
run -all

7
wally-pipelined/regression/wally-pipelined-batch.do
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@ -38,6 +38,13 @@ switch $argc {
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
vopt work_$2.testbench -work work_$2 -o workopt_$2
vsim -lib work_$2 workopt_$2
# Adding coverage increases runtime from 2:00 to 4:29. Can't run it all the time
#vopt work_$2.testbench -work work_$2 -o workopt_$2 +cover=sbectf
#vsim -coverage -lib work_$2 workopt_$2
run -all
#coverage report -file wally-pipelined-coverage.txt
# These aren't doing anything helpful
#coverage report -memory
#profile report -calltree -file wally-pipelined-calltree.rpt -cutoff 2
quit

2
wally-pipelined/src/lsu/lsu.sv
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@ -121,7 +121,6 @@ module lsu
logic [`XLEN-1:0] PageTableEntryM;
logic DTLBWriteM;
logic [`XLEN-1:0] HPTWReadPTE;
logic MMUReady;
logic HPTWStall;
logic [`XLEN-1:0] HPTWPAdrE;
logic [`XLEN-1:0] HPTWPAdrM;
@ -164,7 +163,6 @@ module lsu
.ITLBWriteF(ITLBWriteF),
.DTLBWriteM(DTLBWriteM),
.HPTWReadPTE(HPTWReadPTE),
.MMUReady(HPTWReady),
.HPTWStall(HPTWStall),
.HPTWPAdrE(HPTWPAdrE),
.HPTWPAdrM(HPTWPAdrM),

3
wally-pipelined/src/lsu/lsuArb.sv
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@ -34,8 +34,6 @@ module lsuArb
input logic HPTWRead,
input logic [`XLEN-1:0] HPTWPAdrE,
input logic [`XLEN-1:0] HPTWPAdrM,
// to page table walker.
//output logic [`XLEN-1:0] HPTWReadPTE,
output logic HPTWStall,
// from CPU
@ -94,7 +92,6 @@ module lsuArb
// demux the inputs from LSU to walker or cpu's data port.
assign ReadDataW = SelPTW ? `XLEN'b0 : ReadDataWfromDCache; // probably can avoid this demux
//assign HPTWReadPTE = SelPTW ? ReadDataWfromDCache : `XLEN'b0 ; // probably can avoid this demux
assign SquashSCW = SelPTW ? 1'b0 : SquashSCWfromDCache;
assign DataMisalignedM = SelPTW ? 1'b0 : DataMisalignedMfromDCache;
// *** need to rename DcacheStall and Datastall.

4
wally-pipelined/src/mmu/pagetablewalker.sv
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@ -49,7 +49,6 @@ module pagetablewalker
// *** modify to send to LSU // *** KMG: These are inputs/results from the ahblite whose addresses should have already been checked, so I don't think they need to be sent through the LSU
input logic [`XLEN-1:0] HPTWReadPTE,
input logic MMUReady,
input logic HPTWStall,
// *** modify to send to LSU
@ -140,8 +139,7 @@ module pagetablewalker
default: PageType = 2'b00; // kilopage
endcase
assign PRegEn = (NextWalkerState == LEVEL3) | (NextWalkerState == LEVEL2) | (NextWalkerState == LEVEL1) | (NextWalkerState == LEVEL0);
assign HPTWRead = (WalkerState == LEVEL3_WDV) | (WalkerState == LEVEL2_WDV) | (WalkerState == LEVEL1_WDV) | (WalkerState == LEVEL0_WDV); // is this really necessary?
assign HPTWRead = (WalkerState == LEVEL3_WDV) | (WalkerState == LEVEL2_WDV) | (WalkerState == LEVEL1_WDV) | (WalkerState == LEVEL0_WDV);
// *** is there a way to speed up HPTW?
// TranslationPAdr mux

7
wally-pipelined/testbench/testbench-imperas.sv
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@ -283,7 +283,6 @@ string tests32f[] = '{
"rv64i/WALLY-SLLI", "3000",
"rv64i/WALLY-SRLI", "3000",
"rv64i/WALLY-SRAI", "3000",
"rv64i/WALLY-JAL", "4000",
"rv64i/WALLY-JALR", "3000",
"rv64i/WALLY-STORE", "3000",
@ -511,11 +510,7 @@ string tests32f[] = '{
logic [`XLEN-1:0] PCW;
logic DCacheFlushDone, DCacheFlushStart;
logic [`XLEN-1:0] debug;
assign debug = dut.uncore.dtim.RAM[536872960];
flopenr #(`XLEN) PCWReg(clk, reset, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.PCM, PCW);
flopenr #(32) InstrWReg(clk, reset, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.InstrM, InstrW);