forked from Github_Repos/cvw
Pulled out shared PTEReg
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86ca9abe42
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@ -78,7 +78,7 @@ module pagetablewalker
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logic [`PPN_BITS-1:0] BasePageTablePPN;
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logic [`XLEN-1:0] TranslationVAdr;
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logic [`XLEN-1:0] SavedPTE, CurrentPTE;
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logic [`XLEN-1:0] CurrentPTE;
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logic [`PA_BITS-1:0] TranslationPAdr;
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logic [`PPN_BITS-1:0] CurrentPPN;
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logic [`SVMODE_BITS-1:0] SvMode;
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@ -130,31 +130,18 @@ module pagetablewalker
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assign TranslationVAdr = (SelDataTranslation) ? MemAdrM : PCF;
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assign SelDataTranslation = DTLBMissMQ | DTLBMissM;
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/* flopenrc #(1)
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DTLBMissMReg(.clk(clk),
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.reset(reset),
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.en(StartWalk | EndWalk),
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.clear(EndWalk),
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.d(DTLBMissM),
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.q(DTLBMissMQ));
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flopenrc #(1)
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ITLBMissMReg(.clk(clk),
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.reset(reset),
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.en(StartWalk | EndWalk),
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.clear(EndWalk),
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.d(ITLBMissF),
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.q(ITLBMissFQ));*/
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flop #(`XLEN) HPTWPAdrMReg(clk, HPTWPAdrE, HPTWPAdrM);
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flopenrc #(2) TLBMissMReg(clk, reset, EndWalk, StartWalk | EndWalk, {DTLBMissM, ITLBMissF}, {DTLBMissMQ, ITLBMissFQ});
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flopenl #(.TYPE(statetype)) WalkerStateReg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState);
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flopenl #(.TYPE(statetype)) PreviousWalkerStateReg(clk, reset, 1'b1, WalkerState, IDLE, PreviousWalkerState);
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flopenl #(.TYPE(statetype)) WalkerStateReg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState);
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flopenl #(.TYPE(statetype)) PreviousWalkerStateReg(clk, reset, 1'b1, WalkerState, IDLE, PreviousWalkerState);
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flopenr #(`XLEN) ptereg(clk, reset, PRegEn, HPTWReadPTE, CurrentPTE); // Capture page table entry from data cache
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assign CurrentPPN = CurrentPTE[`PPN_BITS+9:10];
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assign AnyTLBMissM = DTLBMissM | ITLBMissF;
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assign StartWalk = WalkerState == IDLE & AnyTLBMissM;
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assign EndWalk = WalkerState == LEAF || WalkerState == FAULT;
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assign StartWalk = (WalkerState == IDLE) & AnyTLBMissM;
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assign EndWalk = (WalkerState == LEAF) || (WalkerState == FAULT);
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// unswizzle PTE bits
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assign {Dirty, Accessed, Global, User,
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@ -291,18 +278,6 @@ module pagetablewalker
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// Capture page table entry from data cache
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// *** may need to delay reading this value until the next clock cycle.
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// The clk to q latency of the SRAM in the data cache will be long.
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// I cannot see directly using this value. This is no different than
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// a load delay hazard. This will require rewriting the walker fsm.
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// also need a new signal to save. Should be a mealy output of the fsm
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// request followed by ~stall.
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flopenr #(32) ptereg(clk, reset, PRegEn, HPTWReadPTE, SavedPTE);
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//mux2 #(32) ptemux(SavedPTE, HPTWReadPTE, PRegEn, CurrentPTE);
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assign CurrentPTE = SavedPTE;
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assign CurrentPPN = CurrentPTE[`PPN_BITS+9:10];
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// Assign outputs to ahblite
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// *** Currently truncate address to 32 bits. This must be changed if
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// we support larger physical address spaces
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@ -514,13 +489,6 @@ module pagetablewalker
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assign VPN1 = TranslationVAdr[29:21];
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assign VPN0 = TranslationVAdr[20:12];
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// Capture page table entry from ahblite
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flopenr #(`XLEN) ptereg(clk, reset, PRegEn, HPTWReadPTE, SavedPTE);
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//mux2 #(`XLEN) ptemux(SavedPTE, HPTWReadPTE, PRegEn, CurrentPTE);
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assign CurrentPTE = SavedPTE;
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assign CurrentPPN = CurrentPTE[`PPN_BITS+9:10];
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// *** Major issue. We need the full virtual address here.
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// When the TLB's are update it use use the orignal address
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// *** Currently truncate address to 32 bits. This must be changed if
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