forked from Github_Repos/cvw
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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commit
412691df2d
@ -137,7 +137,7 @@ module csrm #(parameter
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else
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flopenl #(32) MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, CSRWriteValM[31:0], 32'hFFFFFFFF, MCOUNTEREN_REGW);
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endgenerate
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flopenl #(32) MCOUNTINHIBITreg(clk, reset, WriteMCOUNTINHIBITM, CSRWriteValM[31:0], 32'hFFFFFFFF, MCOUNTINHIBIT_REGW);
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flopenl #(32) MCOUNTINHIBITreg(clk, reset, WriteMCOUNTINHIBITM, CSRWriteValM[31:0], 32'h0, MCOUNTINHIBIT_REGW);
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// There are PMP_ENTRIES = 0, 16, or 64 PMPADDR registers, each of which has its own flop
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@ -44,14 +44,14 @@ module testbench();
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logic [31:0] InstrW;
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logic [`XLEN-1:0] meminit;
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string tests32mmu[] = '{
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//string tests32mmu[] = '{
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//"rv32mmu/WALLY-MMU-SV32", "3000"
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};
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// };
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string tests64mmu[] = '{
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//string tests64mmu[] = '{
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//"rv64mmu/WALLY-MMU-SV48", "3000",
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//"rv64mmu/WALLY-MMU-SV39", "3000"
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};
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//};
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string tests32f[] = '{
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@ -540,7 +540,7 @@ string tests32f[] = '{
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else tests = {tests, tests64iNOc};
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if (`M_SUPPORTED) tests = {tests, tests64m};
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if (`A_SUPPORTED) tests = {tests, tests64a};
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if (`MEM_VIRTMEM) tests = {tests, tests64mmu};
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//if (`MEM_VIRTMEM) tests = {tests, tests64mmu};
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if (`F_SUPPORTED) tests = {tests64f, tests};
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if (`D_SUPPORTED) tests = {tests64d, tests};
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end
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@ -558,7 +558,7 @@ string tests32f[] = '{
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if (`M_SUPPORTED % 2 == 1) tests = {tests, tests32m};
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if (`F_SUPPORTED) tests = {tests32f, tests};
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if (`A_SUPPORTED) tests = {tests, tests32a};
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if (`MEM_VIRTMEM) tests = {tests, tests32mmu};
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//if (`MEM_VIRTMEM) tests = {tests, tests32mmu};
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end
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end
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end
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