Ross Thompson b1ceeb40df Loads in modelsim, but the first store double does not function correctly. The write address is wrong so the cache is updated using the wrong address. ... I think this is do to the cycle latency of stores. We probably need extra muxes to select between MemPAdrM and MemPAdrW depending on if the write is a full cache block or a word write from the CPU.		2021-07-09 17:14:54 -05:00
..
bin	Icache integrated!	2021-04-26 11:48:58 -05:00
config	Don't generate HPTW when MEM_VIRTMEM=0	2021-07-05 23:35:44 -04:00
linux-testgen	optionally output GDB-formatted instruction list to main buildroot folder	2021-07-03 17:25:19 -04:00
misc	Clean up MMU code	2021-05-14 07:12:32 -04:00
ppa	Config file for ppa experiments	2021-03-25 10:23:21 -05:00
regression	Fixed bug in the LSU pagetable walker interlock.	2021-07-06 10:41:36 -05:00
src	Loads in modelsim, but the first store double does not function correctly. The write address is wrong so the cache is updated using the wrong address.	2021-07-09 17:14:54 -05:00
testbench	more completely uncomment MMU tests to make sim wally work	2021-07-06 14:33:52 -04:00
testgen	mcause test fixes and s-mode interrupt bugfix	2021-06-16 17:37:08 -04:00
lint-wally	Merge difficulties	2021-06-07 09:50:23 -04:00