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1007 Commits

Author SHA1 Message Date
Jacob Pease
140d246fb5 Prevented writes to SATP enabling SV57. This follows the spec more accurately. Linux can now successfully probe SATP. 2023-08-22 16:25:56 -05:00
Ross Thompson
c2a9fbb1fc Fixed bug with the cbo.inval clearing already cleared lines. 2023-08-21 17:51:51 -05:00
Ross Thompson
05d590b0b9 Fixed issue when with flush miss. 2023-08-18 16:36:13 -05:00
Ross Thompson
fc3fccafe9 Now we have invalidate, clean, and flush working. 2023-08-18 16:32:22 -05:00
Ross Thompson
4eeba9bed9 Added cbom test to custom. Needs to be moved to wally-riscv-arch-tests. 2023-08-18 15:59:39 -05:00
Ross Thompson
5c408454b8 Might have working cbo clean and flush instructions. 2023-08-18 14:48:21 -05:00
Ross Thompson
21129dde71 Fixed cbo instruction decode. 2023-08-18 11:32:30 -05:00
Ross Thompson
9dcc70d6c1 Updated the hazard logic for CMO operations. 2023-08-17 17:58:49 -05:00
Ross Thompson
072126b967 Found first bug in CMO implementation. 2023-08-17 16:57:54 -05:00
Ross Thompson
f9df1fda23 CMOZ now implemented in the D cache. 2023-08-17 12:46:40 -05:00
Ross Thompson
624b3e3ab2 Added clean and flush to cache fsm. 2023-08-16 14:23:56 -05:00
Ross Thompson
5281077531 More progress towards cmo. 2023-08-15 18:17:15 -05:00
Ross Thompson
9f37fef145 The L1 D cache now supports cache line (block) invalidation and partial support for clean and flush. 2023-08-14 16:39:18 -05:00
Ross Thompson
0eac74ac7b Initial CMO implementation. Just adds control signals into the L1 caches. 2023-08-14 15:43:12 -05:00
Ross Thompson
7a196d3fa7 Cache cleanup. 2023-07-31 14:12:53 -05:00
Ross Thompson
faaf43fa10 Merge pull request #372 from davidharrishmc/dev 
PLIC part select warnings fixed
 2023-07-31 11:28:28 -04:00
David Harris
6ff2b0cc2c Merge pull request #373 from harshinisrinath1001/main 
Improved testing of pmd in priv, fixed bugs, and attempted to reset menvcfg and fixed spacing in fpu/fma and fpu/postprocessing
 2023-07-30 22:46:44 -07:00
Harshini Srinath
7ed4cf97ed Fixed formatting 2023-07-30 18:36:25 -07:00
Harshini Srinath
603ed2160e Fixed formatting 2023-07-30 18:30:23 -07:00
Harshini Srinath
acbbe7941a Fixed formatting 2023-07-30 18:27:22 -07:00
Harshini Srinath
e4de9ae87c Fixed formatting 2023-07-30 18:18:24 -07:00
Harshini Srinath
4c1a07eb9c Fixed formatting 2023-07-30 18:06:25 -07:00
Harshini Srinath
1badc8a8c5 Fixed formatting 2023-07-30 18:00:39 -07:00
Harshini Srinath
41555b149e Fixed formatting 2023-07-30 17:54:47 -07:00
Harshini Srinath
8e97224cd7 Fixed formatting 2023-07-30 17:46:23 -07:00
Harshini Srinath
469b03577d Fixed formatting 2023-07-30 17:39:37 -07:00
Harshini Srinath
141384f60f Fixed formatting 2023-07-30 17:38:22 -07:00
Harshini Srinath
bbbd5f6b2d Fixed spacing 2023-07-30 17:32:46 -07:00
Harshini Srinath
d7b2d84124 Fixed spacing 2023-07-30 17:22:40 -07:00
Harshini Srinath
b129068a92 Fixed spacing 2023-07-30 17:21:52 -07:00
Harshini Srinath
49823ccd45 Fixed spacing 2023-07-30 17:21:22 -07:00
Harshini Srinath
36108e4b52 Fixed spacing 2023-07-30 17:18:25 -07:00
Harshini Srinath
d88b2fd9c1 Fixed spacing 2023-07-30 16:59:27 -07:00
Harshini Srinath
d69d0ececc Fixed spacing 2023-07-30 16:57:57 -07:00
David Harris
d58ece3d44 renamed test-shared.vh to config-shared.vh 2023-07-30 05:22:39 -07:00
David Harris
28823aca6e Cleaned up lint for plic_apb part select 2023-07-30 02:00:38 -07:00
David Harris
654cafb7f7 Fixed Questa warnings in plic_apb about part select out of bounds 2023-07-30 01:54:41 -07:00
Ross Thompson
7e06775135 Fixed a very subtle combinational loop bug the SSTC implementation of csrs.sv. STIMCMPH did not assign all XLEN bits of CSRSReadValM so dc_shell produced d-latches and vivado created a combinational loop. 2023-07-28 11:20:29 -05:00
Ross Thompson
15dc76310e Fixed lint errors for issue #368. Does not fix simulation errors. We made a design decision a long time ago to not support DTIM on the rv32gc config because LLEN was greater than XLEN. 2023-07-26 15:08:01 -05:00
Ross Thompson
2dac02c14c Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-07-25 15:13:07 -05:00
David Harris
ca62487e4c Formatting cleanup 2023-07-25 05:11:38 -07:00
Ross Thompson
b1f7a5768f Removed all old references to the old flash card controller. 
Added git submodule for the flash card in addins.
Replicated flash card top level for our changes into the fpga/src directory.
 2023-07-24 15:45:57 -05:00
Ross Thompson
63afd95ad3 Fixed bugs in boot and new flash card merge. Works with arty a7 now. 2023-07-22 15:52:25 -05:00
Ross Thompson
a89a1e675c Merge branch 'boot' into mergeBoot 
Merges Jacob's new sdc controller into wally.
 2023-07-21 17:43:45 -05:00
Ross Thompson
f895898d22 Improved the critical path even more. The Arty A7 works upto 19Mhz easily. Testing out 22Mhz now. 2023-07-21 16:31:26 -05:00
Ross Thompson
d04d2afed2 Modified the LSU/IFU and caches to improve critical path. Arty A7 went from 15 to 17Mhz. I believe we can push all the way to 20+Mhz with relatively little effort. Along the way I'm fixing up the scripts build the linux images for the flash card. 2023-07-21 13:06:27 -05:00
Jacob Pease
380d96b359 Working new boot process. Buildroot package for sdc. 2023-07-20 14:15:59 -05:00
Ross Thompson
c0966c32e5 Improved critical path. 2023-07-19 14:59:37 -05:00
Ross Thompson
538efaf771 Optimized critial path in ifu's spill logic. 2023-07-19 14:13:46 -05:00
Ross Thompson
af0e33209f Removed QEMU from configurations. 2023-07-19 10:23:55 -05:00
Ross Thompson
b756b248b4 Wow. The newest version of Vivado does not like the enums as parameters. 
The solution is simple.  I changed the type to logic [31:0] and defined macros for the branch predictor types as 32 bit integers.
 2023-07-18 15:07:10 -05:00
Ross Thompson
42e6364b3d Merge branch 'main' of github.com:ross144/cvw 2023-07-17 15:52:27 -05:00
Ross Thompson
c82638774f Updated the FPGA zero stage bootloader. 2023-07-17 15:52:13 -05:00
Ross Thompson
50bc679fef Fixed bug with performance counters not tracking the correct number of requested icache and dcache memory operations. 2023-07-14 16:31:44 -05:00
Jacob Pease
b3aaa87cba Modified bootloader to access GUID partitions. SDC interrupt to PLIC. 
Since writing an SD card image generation script, the bootloader
needed to be altered to access individual binaries from specific
partitions. A new file, gpt.c with it's header gpt.h, have been added
to the bootloader to facilitate this.

The SDC has been added to the device tree for the VCU108
board. Additionally the SDC interrupt signal was added to the PLIC
node in the device tree. The PLIC itself  was modified to accept the
SDC interrupt signal.
 2023-07-14 13:36:44 -05:00
David Harris
644afa16cd Clean up privilege rs1 decoding and implement svinval as sfence.vma 2023-07-13 02:41:17 -07:00
Ross Thompson
625192d9a4 Merge branch 'main' of github.com:ross144/cvw into main 2023-07-11 15:08:26 -05:00
Ross Thompson
38f32805ae Created separate temporary testbench for xcelium. 2023-07-11 15:07:33 -05:00
Ross Thompson
4c4eb080ee RTL changes for Xcelium. 2023-07-11 10:51:02 -05:00
Ross Thompson
12beada55b Fixed the privilege decoder bug which prevented the fpga linux boot. 2023-07-10 17:00:06 -05:00
Ross Thompson
beaec570c7 Merge pull request #359 from davidharrishmc/dev 
CSR updates
 2023-07-10 13:16:57 -04:00
David Harris
e713ba8d3e MENVCFG only exists if U_SUPPORTED 2023-07-09 18:25:07 -07:00
Ross Thompson
27f6f00402 Changes for xcelium. 2023-07-07 18:22:28 -05:00
Ross Thompson
cdf73d3b51 Updated comments. 2023-07-06 15:24:26 -05:00
Ross Thompson
e4555dc4af Removed unused parameter. 2023-07-06 14:57:07 -05:00
Ross Thompson
2ce8b66574 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-07-06 14:55:43 -05:00
David Harris
369e8fb5ec Removed outdated commment about endianness 2023-07-06 12:41:46 -07:00
David Harris
869a7cb827 Removed MTINST, which is not used in a system without a hypervisor 2023-07-06 12:40:53 -07:00
Ross Thompson
a963e50e88 It's a bit hacky, but the plic now passes the regression test and should be compatible with the fpga. 2023-07-06 14:07:37 -05:00
Ross Thompson
df56ff73c0 This is at least functionally correct, but has verilator lint issues. 2023-07-06 11:53:34 -05:00
Ross Thompson
c000366d3e closer, but the wally32/64priv tests are failing. 2023-07-05 17:47:38 -05:00
Ross Thompson
98147e116a Partially solved fpga boot. 2023-07-05 17:30:55 -05:00
David Harris
269bb688ea Fixed comment typo 2023-07-04 11:34:58 -07:00
David Harris
410ef01627 fixed spacing in fdivsqrt 2023-07-04 11:27:36 -07:00
David Harris
afe66d0ee4 Added prefetch instructions; sent cbo instructions to LSU 2023-07-02 10:55:35 -07:00
David Harris
723b8266cb Added prefetch signals 2023-07-02 10:06:58 -07:00
David Harris
482e4e6e92 Enhanced decoder to produce individual CMOpE output for the 4 CMO instructions 2023-07-02 09:35:05 -07:00
David Harris
c48283801a Fixed csr typos 2023-07-02 02:01:40 -07:00
David Harris
61208e486c Fixed ENVCFG to reply on both MENVCFG and SENVCFG when in user mode 2023-07-02 02:00:27 -07:00
David Harris
b6ae5661b4 Added environment configuration control (menvcfg/senvcfg) of cbo instructions 2023-07-02 01:52:25 -07:00
David Harris
15314a9c9a Gated floating-point load/stores with STATUS_FS and added initial decoding for Cache Management Operations 2023-07-02 00:34:30 -07:00
David Harris
41e9f20943 improved decoder checking atomic and RW and MW and privileged instructions 2023-07-02 00:02:03 -07:00
David Harris
e34ef4d636 improved decoder checking atomic instructions 2023-07-01 23:10:57 -07:00
David Harris
d930be332e Improved instruction decoding for illegal floating-point loads/stores and fences 2023-07-01 22:48:04 -07:00
Ross Thompson
f5cee3fb66 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-06-18 16:37:19 -05:00
David Harris
c383407d5c Removed redundant and not-covered atomic check from StoreStallD 2023-06-16 16:05:53 -07:00
Ross Thompson
c44d4321fb FPGA synthesis is broken. This commit moves closer to fixing the issues causes by parameterization. 2023-06-16 15:40:13 -05:00
Ross Thompson
bdc5656ef3 Added comment to uart LCR to check reset value after updating FPGA. 2023-06-15 15:39:51 -05:00
Ross Thompson
4428babda9 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-06-15 15:38:38 -05:00
Ross Thompson
85567841eb Merge branch 'testbench-params2' 2023-06-15 15:31:13 -05:00
Ross Thompson
d2219023c3 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-06-15 14:57:23 -05:00
David Harris
3ca271b6a7 Added input gating on FPU 2023-06-15 12:38:33 -07:00
David Harris
9e839988dc Gated MDU to save power; doesn't seem to have affected simulation time 2023-06-15 12:17:23 -07:00
David Harris
9f88848832 Bit manipulation comment cleanup 2023-06-15 12:16:46 -07:00
Ross Thompson
75b5c23edd Actually removed old `define configuration file for rv64gc. There were a lot of dangling problems. 2023-06-15 14:05:44 -05:00
David Harris
a62211bad1 Gated inputs to BMU when inactive to save power and simulation time 2023-06-15 11:56:59 -07:00
Ross Thompson
009d8966e9 Got the srams parameterized correctly now. 2023-06-15 13:42:24 -05:00
David Harris
d3aebc00d4 Fixed UART merge conflict 2023-06-15 11:36:37 -07:00
Ross Thompson
b8a243827b Found a whole bunch of files still using the old `define configurations. 2023-06-15 13:09:07 -05:00
Harshini Srinath
dd7c13cc2d Update wallypipelinedsoc.sv 
Program clean up
 2023-06-15 10:39:37 -07:00
Harshini Srinath
b4469fd3bf Update wallypipelinedcore.sv 
Program clean up
 2023-06-15 10:38:38 -07:00
Harshini Srinath
85a513e542 Update cvw.sv 
Program clean up
 2023-06-15 10:29:33 -07:00
Harshini Srinath
b5354a811e Update uncore.sv 
Program clean up
 2023-06-15 10:23:47 -07:00
Harshini Srinath
85b982f569 Update uart_apb.sv 
Program clean up
 2023-06-15 10:21:46 -07:00
Harshini Srinath
59178a2e56 Update uartPC16550D.sv 
Program clean up
 2023-06-15 10:20:29 -07:00
Harshini Srinath
d02891d244 Update rom_ahb.sv 
Program clean up
 2023-06-15 10:13:15 -07:00
Harshini Srinath
e227f71d46 Update ram_ahb.sv 
Program clean up
 2023-06-15 10:10:38 -07:00
Harshini Srinath
57f4c8a3e4 Update plic_apb.sv 
Program clean up
 2023-06-15 10:08:16 -07:00
Harshini Srinath
cf25e9ce49 Update gpio_apb.sv 
Program clean up
 2023-06-15 10:04:28 -07:00
Harshini Srinath
a8fa38ff14 Update clint_apb.sv 
Program clean up
 2023-06-15 09:59:11 -07:00
David Harris
325a670435 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-06-15 07:01:44 -07:00
Ross Thompson
60e87b08c4 Improved simulation speed by gating bitmanip zbc's clmul's X and Y inputs with BSelect != 11. Reduced simulation time from 3m45s to 2m35s. 2023-06-14 15:28:58 -05:00
Harshini Srinath
3593762cfa Merge branch 'main' into main 2023-06-14 11:52:45 -07:00
David Harris
430537a052 Moved cvw.sv to src root directory to avoid double-compiling and producing a warning. Adjusted to files to reflect this. 2023-06-14 09:44:52 -07:00
David Harris
9da4005a1e Removed *** from UART code 2023-06-14 08:47:01 -07:00
David Harris
5a2bcb917f Removed QEMU from UART 2023-06-14 08:39:01 -07:00
Harshini Srinath
3f8cd8932c Update csrs.sv 
Program clean up
 2023-06-13 22:16:43 -07:00
Harshini Srinath
12af05da02 Update csrm.sv 
Program clean up
 2023-06-13 22:08:06 -07:00
Harshini Srinath
a213f7d5a4 Update csrc.sv 
Program clean up
 2023-06-13 21:54:47 -07:00
Harshini Srinath
6aba0187d7 Update csr.sv 
Program clean up
 2023-06-13 21:12:49 -07:00
harshini
8570b2f332 deleting CodeAligner file 2023-06-13 17:41:37 -07:00
Harshini Srinath
9e1f03f93b Update ahbapbbridge.sv 
Program clean up
 2023-06-12 20:49:46 -07:00
Harshini Srinath
2c6322647f Update trap.sv 
Program clean up
 2023-06-12 20:31:44 -07:00
Harshini Srinath
dba1a77e5f Update privmode.sv 
Program clean up
 2023-06-12 20:27:48 -07:00
Harshini Srinath
63a7649179 Update privileged.sv 
Program clean up
 2023-06-12 20:26:07 -07:00
Harshini Srinath
d2a41a6422 Update csru.sv 
Program clean up
 2023-06-12 20:21:55 -07:00
Harshini Srinath
6866a9c541 Update csrsr.sv 
Program clean up
 2023-06-12 20:19:47 -07:00
Harshini Srinath
fbdf76629f Update csrsr.sv 
Program clean up
 2023-06-12 20:15:29 -07:00
Harshini Srinath
120cde2aea Update csrs.sv 
Program clean up
 2023-06-12 19:53:41 -07:00
Harshini Srinath
6305412d57 Update csrm.sv 
Program clean up
 2023-06-12 19:42:45 -07:00
Harshini Srinath
61d50a18da Update csri.sv 
Program clean up
 2023-06-12 19:32:04 -07:00
Harshini Srinath
02a11278fc Update csrc.sv 
Program clean up
 2023-06-12 19:03:34 -07:00
Harshini Srinath
a2645dd576 Update csr.sv 
Program clean up
 2023-06-12 18:51:37 -07:00
Harshini Srinath
a1a9d668c5 Update pmpchecker.sv 
Program clean up
 2023-06-12 18:44:36 -07:00
Harshini Srinath
09ac5b1817 Update pmpadrdec.sv 
Program clean up
 2023-06-12 18:41:47 -07:00
Harshini Srinath
ccb81c84f4 Update pmachecker.sv 
Program clean up
 2023-06-12 18:39:36 -07:00
Harshini Srinath
5a6a932b7e Update mmu.sv 
Program clean up
 2023-06-12 18:36:04 -07:00
Harshini Srinath
a57a619349 Update hptw.sv 
Program clean up
 2023-06-12 18:31:38 -07:00
Harshini Srinath
ec0454111f Update adrdecs.sv 
Program clean up
 2023-06-12 18:22:32 -07:00
Harshini Srinath
b1ee6bfde5 Update adrdec.sv 
Program clean up
 2023-06-12 17:28:21 -07:00
Harshini Srinath
7c51dd18dd Update mul.sv 2023-06-12 14:00:37 -07:00
Harshini Srinath
08459c4cc4 Update mdu.sv 
Program clean up
 2023-06-12 13:54:54 -07:00
Harshini Srinath
bdd2206817 Update div.sv 
Program clean up
 2023-06-12 13:47:09 -07:00
Harshini Srinath
15928c5d7b Update swbytemask.sv 
Program clean up
 2023-06-12 13:37:35 -07:00
Harshini Srinath
f3a7d9030c Update subwordwrite.sv 
Program clean up
 2023-06-12 13:35:27 -07:00
Harshini Srinath
f1f21f0896 Update subwordread.sv 
Program clean up
 2023-06-12 13:31:54 -07:00
Harshini Srinath
4d0be994aa Update lsu.sv 
Program clean up
 2023-06-12 13:29:18 -07:00
Harshini Srinath
a45f2fd044 Update lrsc.sv 
Program clean up
 2023-06-12 13:14:36 -07:00
Harshini Srinath
d21fd3da44 Update dtim.sv 
Program clean up
 2023-06-12 13:11:24 -07:00
Harshini Srinath
048e100805 Update atomic.sv 
Program clean up
 2023-06-12 13:08:54 -07:00
Harshini Srinath
ec1aa29edc Update amoalu.sv 
Program clean up
 2023-06-12 12:54:50 -07:00
Harshini Srinath
9d0fc0a138 Update spill.sv 
Program clean up
 2023-06-12 12:50:11 -07:00
Harshini Srinath
19e8acff70 Update irom.sv 
Program clean up
 2023-06-12 12:44:09 -07:00
Harshini Srinath
a5561c2cf6 Update ifu.sv 
Program clean up
 2023-06-12 12:38:52 -07:00
Harshini Srinath
b5c655b1c3 Update decompress.sv 
Program clean up
 2023-06-12 12:27:55 -07:00
Harshini Srinath
d0ede93dc1 Update CodeAligner.py 
Program clean up
 2023-06-12 12:25:47 -07:00
Harshini Srinath
5f73c9727f Update shifter.sv 
Program clean up
 2023-06-12 12:23:45 -07:00
Harshini Srinath
0f36cbd830 Update regfile.sv 
Program clean up
 2023-06-12 12:21:25 -07:00
Harshini Srinath
f1cef043c6 Update ieu.sv 
Program clean up
 2023-06-12 12:19:04 -07:00
Harshini Srinath
304adcb9b0 Update extend.sv 
Program clean up
 2023-06-12 12:15:33 -07:00
Harshini Srinath
1d24a9c912 Update datapath.sv 
Program clean up
 2023-06-12 12:13:58 -07:00
Ross Thompson
ee4352975c This parameterizes the testbench but does not use the verilator updates or the new testbench. 2023-06-12 11:00:30 -05:00
Ross Thompson
7031a7b1ea Merge pull request #327 from harshinisrinath1001/main 
Fixed the spacing in the fpu module
 2023-06-12 11:53:52 -04:00
Harshini Srinath
0c324bce7b Update prioritythermometer.sv 
Program clean up
 2023-06-11 19:18:21 -07:00
Harshini Srinath
66856f31ca Update or_rows.sv 
Program clean up
 2023-06-11 19:16:37 -07:00
Harshini Srinath
250ea7668e Update neg.sv 
Program clean up
 2023-06-11 19:15:28 -07:00
Harshini Srinath
5a40272fd7 Update counter.sv 
Program clean up
 2023-06-11 19:12:57 -07:00
Harshini Srinath
16028a5766 Update adder.sv 
Program clean up
 2023-06-11 19:09:18 -07:00
Harshini Srinath
61b85d1c7f Update unpackinput.sv 
Program clean up
 2023-06-11 17:09:11 -07:00
Harshini Srinath
37ad074c4d Update fctrl.sv 
Program clean up
 2023-06-11 17:03:29 -07:00
Harshini Srinath
ac17b93a84 Update fcmp.sv 
Program clean up
 2023-06-11 16:54:52 -07:00
Harshini Srinath
c19ba6c3f4 Update fsgninj.sv 
Program clean up
 2023-06-11 16:52:00 -07:00
Harshini Srinath
cf39819bac Update fregfile.sv 
Program clean up
 2023-06-11 16:49:20 -07:00
Harshini Srinath
a98096aa7d Update fpu.sv 
Program clean up
 2023-06-11 16:43:31 -07:00
Harshini Srinath
4c4e6ca520 Update fhazard.sv 
Program clean up
 2023-06-11 16:06:44 -07:00
Harshini Srinath
610ac81a71 Update fcvt.sv 
Program clean up
 2023-06-11 16:05:14 -07:00
Harshini Srinath
e469e4fd20 Update fcvt.sv 
Program clean up
 2023-06-11 15:59:20 -07:00
Ross Thompson
e27dfb8ce0 Merge branch 'verilator' 2023-06-11 15:28:04 -05:00
David Harris
29b48334d8 Fixed lint errors, presumably detected by latest version of verilator 2023-06-11 06:48:42 -07:00
David Harris
99fe09fb40 Merge pull request #322 from harshinisrinath1001/main 
Fixing spacing for ebu
 2023-06-11 06:00:35 -07:00
Harshini Srinath
aead7cbe49 Update fctrl.sv 
Program clean up
 2023-06-10 19:38:50 -07:00
Harshini Srinath
04a744c249 Update fcmp.sv 
Program clean up
 2023-06-10 19:35:58 -07:00
Harshini Srinath
ffada57ea2 Update fcmp.sv 
Program clean up
 2023-06-10 19:34:58 -07:00
Harshini Srinath
ec188987b8 Update fclassify.sv 
Program clean up
 2023-06-10 19:30:18 -07:00
Harshini Srinath
9dc72c9e54 Update controllerinput.sv 
Program clean up
 2023-06-10 18:26:06 -07:00
Harshini Srinath
dbdb3c69d3 Update ahbinterface.sv 
Program clean up
 2023-06-10 18:18:16 -07:00
Harshini Srinath
dc0b95c4ac Program clean up 2023-06-10 18:13:40 -07:00
Ross Thompson
c7536663c0 Merge pull request #319 from davidharrishmc/dev 
Renamed Performance Counter extension
 2023-06-09 21:21:45 -04:00
David Harris
b70b0c7c5e Added support for menvcfg and senvcfg, including menvcfg.STCE for supervisor timer compare 2023-06-09 14:40:01 -07:00
David Harris
df96900aa1 Added named support for Zicntr and Zihpm 2023-06-09 09:35:51 -07:00
Harshini Srinath
aafa5d6ec3 Update ebu.sv 
Code clean up
 2023-06-09 08:53:27 -07:00
Harshini Srinath
570a628198 Update subcachelineread.sv 
Code clean up
 2023-06-09 08:50:51 -07:00
Harshini Srinath
c49232f0d2 Update cacheway.sv 
Code clean up
 2023-06-09 08:48:11 -07:00
Harshini Srinath
e7fb7403ef Update cacheLRU.sv 
Code clean up
 2023-06-09 08:43:38 -07:00
Harshini Srinath
19c1a0f99b Update cache.sv 
Formatting clean up
 2023-06-09 08:39:57 -07:00
Ross Thompson
a8a8422557 Updated parameterization types. Modelsim version 2022.1 did requires defaults to a 32 bit integer. The base and ranges for the address decoder need to be larger. 2023-06-09 09:28:24 -05:00
David Harris
75dc86ddc0 Merge pull request #313 from ross144/main 
Fix extraneous force in testbench which keep btb in reset.
 2023-06-06 08:41:34 -07:00
David Harris
c9ca5108b1 Merge pull request #312 from ross144/main 
Fixed typo in coremark makefile.
 2023-06-06 05:44:22 -07:00
Ross Thompson
918464c236 Found the coremark performance issue. The testbench was continuously forcing the BTB to all zeros. Once fixed it resolved the performance problem. 2023-06-05 15:42:05 -05:00
James Stine
3bd5bbce48 Update some spacing to make it look better 2023-06-05 11:03:06 -05:00
Ross Thompson
1ceea51d8b Changes required to make verilator compile wally's testbench to c++. Not actually tested in simulation yet. 2023-05-31 16:51:00 -05:00
Ross Thompson
a963f0af3a Updated source code to be compatible with verilator 5.011 for lint only. 2023-05-31 10:44:23 -05:00
Ross Thompson
169539f773 Cleanup parameterization for verilator 5.010. 2023-05-31 10:02:34 -05:00
Ross Thompson
8e1476cb8c Possible fix for Linux bug and bug 203. ImperasDV mismatches in linux boot around 571M instructions after the login prompt. 
This bug occurs when there are back to back HPTW requests and the first generates an access fault during the walk. The old implementation uses a delayed version of the fault to prevent the HTPW fsm from transitioning out of the IDLE state.  Because the first request generates the fault and the second request is pipelined the second request appears as if it also faults so the FSM does not perform the walk.
The new implementation adds a FAULT state.  When the HPTW generates an access fault it transitions to this state removes the HPTWStall and then transitions to IDLE.  There may still be a remaining bug here if the pipeline is stalled for another reason.  However I don't think it is possible by construction.  The only possible sources of stalls at this point would be IFU and LSU stalls and both are required to make this condition happen.
 2023-05-30 15:20:24 -05:00
Ross Thompson
04d0fd94f0 Merge branch 'param-lim-merge' 2023-05-26 16:25:35 -05:00
Ross Thompson
3cc85349b5 Uncore is now parameterized. 2023-05-26 16:24:12 -05:00
Ross Thompson
1315a0bf4a Got the branch predictor parameterized using Lim's method. Also had to add a global enum included in both cvw.sv and the configs which defines the branch predictor types. This should be synthesizable, but I'll need to double check. 2023-05-26 16:00:14 -05:00
Jacob Pease
40f81d5da6 The Vivado-RISC-V SDC works. Wally is now booting through it. 2023-05-26 15:42:33 -05:00
Ross Thompson
f1b8689955 Finished fpu parameterization using Lim's method. 2023-05-26 14:40:06 -05:00
Ross Thompson
29e0357f21 fdiv is now parameterized using Lim's method. 2023-05-26 14:25:14 -05:00
Ross Thompson
81491e85e5 Parameterized fpu's unpack and fma using Lim's method. 2023-05-26 14:12:25 -05:00
Ross Thompson
c7e515634d I think I've solved the slow down issue. Parameters can't be mixed with cvw_t and other types. 2023-05-26 13:56:51 -05:00
Ross Thompson
b517a96261 Update top level parameterized. Simulation slowed down to 4.5 minutes. 2023-05-26 12:13:11 -05:00
Ross Thompson
8cf38b28aa The privileged unit is parameterized using Lim's method. 2023-05-26 12:03:46 -05:00
Ross Thompson
4d961bd080 Completed LSU parameterization based on Lim's changes. 2023-05-26 11:26:09 -05:00
Ross Thompson
d37e010aa4 Subwordread now parameterized. 2023-05-26 11:22:44 -05:00
Ross Thompson
02a788a083 PMA checker's address decoder is now parameterized. I did not see bit slicing in Lim's code. I'm not sure how they got around this issue. 2023-05-26 11:06:48 -05:00
Ross Thompson
0e1131d190 Progress on LSU. 2023-05-26 10:47:09 -05:00
Ross Thompson
0020d94b39 Updated mmu's tlb and hptw to use Lim's parameterization. 2023-05-24 18:02:22 -05:00
Ross Thompson
70c8828ac2 PM(P/A) checkers parameterized based on Lim's work. 2023-05-24 17:20:55 -05:00
Ross Thompson
fcb1c63f5f Partial parameterization into mmu. 2023-05-24 16:12:41 -05:00
Ross Thompson
5f5f33787d MDU and hazard unit now also parameterized. Based on Lim's work. Again I want to clarify this their work. Not mine. I'm just doing this because the merge had an issue. 2023-05-24 15:01:35 -05:00
Ross Thompson
1299319d0b More parameterization. Based on Lim's work. EBU, IFU (except bpred), and IEU done. 2023-05-24 14:56:02 -05:00
Ross Thompson
052bc95966 More parameterization. Copied Lim. Still no slow down. 2023-05-24 14:49:22 -05:00
Ross Thompson
b91b54589e Updated a large number of the source files to use parameters rather than `defines. Based on Lim's work. So far there is no simulation slow down. 2023-05-24 14:05:44 -05:00
Ross Thompson
6d2e3070a5 Merged changes. 2023-05-24 13:15:52 -05:00
Ross Thompson
80aa0888f3 Updated headers to local branch history predictors. 2023-05-24 12:52:42 -05:00
Ross Thompson
930fb67308 Trying to figure out why the parameterization slowed down modelsim so much. 2023-05-24 12:44:42 -05:00
Ross Thompson
69a9bf7055 Adds local history predictor. 
Fixes performance counters, but not coremark.
 2023-05-23 18:53:46 -05:00
Ross Thompson
664231c0da Merge branch 'localhistory' 
Repair to wave file.
Created implementations of local history. Part of my Ph.D. research.
 2023-05-22 10:13:31 -05:00
Ross Thompson
625d365f3e Fixes load and store stall counters. 2023-05-22 10:08:49 -05:00
Ross Thompson
8f305bf3cf Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-05-11 14:56:53 -05:00
Ross Thompson
d545a2ec74 Partially working local history repair. 2023-05-11 14:56:26 -05:00
Ross Thompson
3a98fb8680 Baseline localhistory with speculative repair built. 2023-05-05 15:23:45 -05:00
Ross Thompson
42517bae6f Fixed bug in local history predictor. 2023-05-04 16:54:41 -05:00
Ross Thompson
ee1e380fad Almost working ahead pipelined local history predictor. 2023-05-04 16:17:31 -05:00
Ross Thompson
8235042ba2 Maybe I finally have the ahead pipelined local history predictor working. 2023-05-04 14:11:34 -05:00
Ross Thompson
060d40853a Ahead pipelining is not yet working. :( 2023-05-03 17:41:38 -05:00
Ross Thompson
8b0791b6b5 I think ahead pipelining is working for local history. 2023-05-03 12:52:32 -05:00
Ross Thompson
414c79b923 Updated configs for local branch history `defines. 2023-05-02 11:11:04 -05:00
Ross Thompson
08b237b878 Added comment explaining the difference between global history and local history basic implementations. 2023-05-02 11:01:46 -05:00
Ross Thompson
0904a9b97f Swapped the m and k parameters for local history predictor. 2023-05-02 10:52:41 -05:00
Ross Thompson
4eff75449a Maybe have the baseline local history predictor working. 2023-05-01 15:45:27 -05:00
Ross Thompson
7437cb67e5 Merge branch 'main' into localhistory 2023-05-01 10:35:50 -05:00
David Harris
d5b718be38 IMMU exclude non word-sized accesses 2023-05-01 08:14:19 -07:00
Ross Thompson
67539a4af1 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-04-30 23:30:13 -05:00
David Harris
90b2a4882f Fixed redundant check of SupportedFmt on fmv that caused coverage problem on fctrl 2023-04-29 05:58:40 -07:00
David Harris
6253c042b2 Merged coverage exclusions for PMP 2023-04-28 08:04:25 -07:00
David Harris
194b848fbf PMA Checker coverage 2023-04-28 07:53:59 -07:00
David Harris
af7959a3e2 Commenting 2023-04-28 07:52:08 -07:00