1007 Commits

Author	SHA1	Message	Date
Rose Thompson	1ca9a8be6d	I think I solved the AMO/store hazard issue introduced by removing the store delay hazard.	2023-12-14 16:31:02 -06:00
Rose Thompson	a7f0aaa722	Added comments to finish store delay stall removal.	2023-12-13 20:35:13 -06:00
Rose Thompson	9cf6b1fdeb	Merge branch 'main' of https://github.com/openhwgroup/cvw	2023-12-13 20:34:35 -06:00
Rose Thompson	9f4c32d49c	Merge branch 'main' of github.com:ross144/cvw	2023-12-13 20:32:59 -06:00
Rose Thompson	b69a5b59cd	DTIM works without the store delay stall. Still a bit of work remaining. The DTIM needs cleanup. ... The cache needs a bit of clean up and the chapter needs updates. The controller needs to be updated to remove the store delay hazard for cmo instructions.	2023-12-13 20:32:14 -06:00
Rose Thompson	e089b421bb	Got it working for the cache.	2023-12-13 20:24:46 -06:00
Rose Thompson	f592baa741	Closer.	2023-12-13 18:15:32 -06:00
Rose Thompson	eeced05f33	More progress towards store delay reduction.	2023-12-13 15:56:29 -06:00
Rose Thompson	f3d43a7713	Progress on reducing store stall in d cache.	2023-12-13 15:34:21 -06:00
David Harris	ff26baf7e8	Rolled back attempt to support Verilator	2023-12-13 12:53:44 -08:00
David Harris	333e390f8d	Test commit from dev	2023-12-13 11:52:21 -08:00
David Harris	6c017141c5	Renamed HADE to ADUE for Svadu	2023-12-13 11:49:04 -08:00
David Harris	aff61ea97a	Fixed Linux makefile; load branch predictor RAMs at startup for sim; fixed comment in trap; starting to make testbench more compatible with Verilator	2023-12-13 11:33:59 -08:00
Rose Thompson	3d0f9ce4f3	Cleaned up comments about pc reset.	2023-12-13 13:06:33 -06:00
Rose Thompson	c98c0dd3e0	Removed unnecessary pc reset logic from ifu and btb.	2023-12-13 13:05:10 -06:00
Rose Thompson	13bb5d845b	On the way to solving the store delay hazard.	2023-12-13 10:39:01 -06:00
Jacob Pease	bc2c4d5295	Merge branch 'main' of github.com:openhwgroup/cvw	2023-12-04 15:23:22 -06:00
Rose Thompson	9348025727	Cachefsm simplifications.	2023-12-03 18:19:00 -06:00
Rose Thompson	1ebc7aa95a	Optimized align.	2023-12-03 16:43:55 -06:00
Rose Thompson	3bef2a2361	Better name for cache signals.	2023-12-03 15:49:06 -06:00
Jacob Pease	7e494f2d3b	Removed vivado property from rom1p1r.sv. It's now dynamically added using the FPGA makefile.	2023-12-01 18:59:18 -06:00
Rose Thompson	025b04ae8b	Minior cleanup.	2023-11-29 19:44:59 -06:00
Rose Thompson	ab68a76e77	LineDirty is either the Victim Way or the Flush way dirty, but never the hitway dirty. CBO instructions require hitway dirty. However we cannot mux hitway dirty into LineDirty wihtout creating a combinational loop so we need a separate port.	2023-11-29 17:58:39 -06:00
Rose Thompson	f11f88ac2b	Updates to tlb to check access permissions for cbo*	2023-11-29 16:20:43 -06:00
Rose Thompson	f4e4aac8b5	Added CMOp to pmp checker	2023-11-29 16:09:31 -06:00
Rose Thompson	fc04b6f7d8	Removed redundant ZICBOM/Z_SUPPORTED from pmachecker.	2023-11-29 15:39:39 -06:00
Rose Thompson	80336493f5	Cleaned up redundant ZICBOM/Z_SUPPORTED.	2023-11-29 15:20:49 -06:00
Rose Thompson	053b094620	Simpilified pmachecker for cmo.	2023-11-29 12:26:18 -06:00
Rose Thompson	d29b2b95f7	Additional cleanup.	2023-11-28 23:28:50 -06:00
Rose Thompson	4149ae6c11	More cleanup.	2023-11-28 23:05:47 -06:00
Rose Thompson	143c6ca4d1	Simplification to alignment.	2023-11-28 22:28:11 -06:00
Rose Thompson	a69a70ba7f	Removed unused hardware from alignment.	2023-11-28 19:54:25 -06:00
Rose Thompson	865ebf8b9b	cclsm cleanup.	2023-11-28 19:41:46 -06:00
Rose Thompson	f4e77e9669	Clean up.	2023-11-28 14:21:37 -06:00
Rose Thompson	df85428041	More optimizations for cclsm.	2023-11-28 14:19:30 -06:00
Rose Thompson	4d4790ecf9	Optimizations to cclsm.	2023-11-28 14:18:06 -06:00
Rose Thompson	0229df4a0f	Oups. Introduced undetected bug into the cache's cbo insructions.	2023-11-28 01:03:48 -06:00
Rose Thompson	9a24a5d957	Renamed signal in pmachecker.	2023-11-28 00:05:12 -06:00
Rose Thompson	69653e5faa	Fixed minor bug in the cbo hazard logic.	2023-11-27 23:38:53 -06:00
Rose Thompson	195def5808	Extended the abhcacheinterface to zero a cacheline's worth of uncached memory on cbo.zero.	2023-11-27 21:24:30 -06:00
Rose Thompson	9290c3f957	Added correct cbo fault behavior.	2023-11-27 20:57:33 -06:00
Rose Thompson	beb95dd592	Modified the pmachecker to correctly check the permissions for cmo instructions. ... However this isn't fully tested.	2023-11-27 17:44:11 -06:00
Rose Thompson	337903d8dd	More cache simplifications.	2023-11-27 14:59:42 -06:00
Rose Thompson	08549446ef	Reduced cache fsm complexity.	2023-11-27 13:13:36 -06:00
Rose Thompson	c3da4c3c31	Clarified names in cacheway.	2023-11-27 12:56:11 -06:00
Rose Thompson	d7ef490c12	Sutble bug in the cacheway logic for cacheline invalidation.	2023-11-27 01:27:09 -06:00
David Harris	1f57df7f8b	Fixed reference to deleted atomic signal in cache	2023-11-23 20:29:10 -08:00
David Harris	3f3c20a38f	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2023-11-21 14:04:02 -08:00
David Harris	b5f79c44f9	Reset STIMECMP to 0 to agree with ImperasDV	2023-11-21 13:43:51 -08:00
Rose Thompson	58d89cc347	Merge branch 'main' of https://github.com/openhwgroup/cvw	2023-11-21 10:48:05 -06:00