David Harris
9b1f85d353
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-03-30 16:26:27 +00:00
Ross Thompson
e4f4e1bd43
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-03-30 11:09:44 -05:00
Ross Thompson
f52ab01362
Partial cleanup of memories.
2022-03-30 11:09:21 -05:00
Ross Thompson
839bede656
Converted over to the blockram/sram memories. Now I just need to cleanup. But before the cleanup I wan to make sure the FPGA synthesizes with these changes and actually keeps the preload.
2022-03-30 11:04:15 -05:00
Ross Thompson
997c1b87fe
rv32gc and rv64gc now use the updated ram3.sv (will rename to ram.sv) which uses a vivado block ram compatible memory. Still need to update simpleram.sv to use this block ram compatible memory.
2022-03-29 23:48:19 -05:00
Ross Thompson
66e9380cfb
Partial fix to allow byte write enables with fpga and still get a preload to work.
2022-03-29 19:12:29 -05:00
David Harris
03fa9084bc
Updated synthesis to look at fma16.v, other scripts to use fma16.v instead of fma16.sv
2022-03-29 19:16:41 +00:00
David Harris
c4f2c6b110
fpu compare simplification, minor cleanup
2022-03-29 17:11:28 +00:00
Kip Macsai-Goren
56a0542405
made machine timer bit of IP registers unwriteable so it can only change when the interrupt actually changes
2022-03-29 02:26:42 +00:00
bbracker
8ea25e591b
fix typo that Madeleine found
2022-03-28 15:39:29 -07:00
Kip Macsai-Goren
709f8e6e0d
fixed double multiplication on vectored interrupts
2022-03-28 19:12:31 +00:00
Ross Thompson
61c714ebe6
I think this version of csri matches what is required in the spec. ExtIntS should not be written into the SEIP register bit.
2022-03-25 13:10:31 -05:00
Ross Thompson
fe896bff8e
Found a way to remove a bus input into MMU. PAdr can be made into VAdr by selecting the faulting virtual address when writing the DTLB.
2022-03-24 23:47:28 -05:00
bbracker
d33de3ef6b
tabs vs spaces disagreement
2022-03-24 17:11:41 -07:00
bbracker
4b376e2834
1st attempt at multiple channel PLIC
2022-03-24 17:08:10 -07:00
Ross Thompson
71aad2d213
Moved WriteDataM register into LSU.
2022-03-23 14:17:59 -05:00
Ross Thompson
8f74fd2a50
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-03-23 14:10:38 -05:00
Katherine Parry
7cf994526a
fixed typo in unpack.sv
2022-03-23 18:26:59 +00:00
Katherine Parry
fcd23a006e
fixed lint error in fpudivsqrtrecur.sv
2022-03-23 03:24:41 +00:00
Ross Thompson
849707f161
Switched csri IP_REGW to use assignements rather than always_comb as this is incompatible with forcing.
2022-03-22 22:04:06 -05:00
Ross Thompson
b2487f4b72
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-03-22 21:28:50 -05:00
Katherine Parry
23adb2dd03
unpack.sv cleanup
2022-03-23 01:53:37 +00:00
Ross Thompson
ca8fb45367
Added comment about needed fix to misaligned fault.
2022-03-22 16:52:07 -05:00
Katherine Parry
e3d01c875b
FMA parameterized and FMA testbench reworked
2022-03-19 19:39:03 +00:00
Ross Thompson
ee4b38dce3
dtim writes are supressed on non cacheable operation.
2022-03-12 00:46:11 -06:00
Ross Thompson
86cc758354
cleanup of ram.sv
2022-03-11 18:09:22 -06:00
Ross Thompson
67ff8f27f4
Can now support the following memory and bus configurations.
...
1. dtim/irom only
2. bus only
3. dtim/irom + bus
4. caches + bus
2022-03-11 15:18:56 -06:00
Ross Thompson
9dce2a0679
Towards allowing dtim + bus.
2022-03-11 14:58:21 -06:00
Ross Thompson
6e24a807f6
mild cleanup.
2022-03-11 13:05:47 -06:00
Ross Thompson
b7a680ec2a
Moved subcachelineread inside the cache. There is some ugliness to still resolve.
2022-03-11 12:44:04 -06:00
Ross Thompson
a18f06c20b
Moved subcacheline read inside the cache.
2022-03-11 11:03:36 -06:00
Ross Thompson
52cc852600
removed unused parameter.
2022-03-11 10:43:54 -06:00
Ross Thompson
7f0c5cc847
atomic cleanup.
2022-03-10 18:56:37 -06:00
Ross Thompson
257015a2df
Name changes.
2022-03-10 18:50:03 -06:00
Ross Thompson
6d914def08
Name cleanup.
2022-03-10 18:44:50 -06:00
Ross Thompson
63b1ea88c9
Signal name cleanup.
2022-03-10 18:26:58 -06:00
Ross Thompson
654c4d1148
simplified uncore's name for HWDATA.
2022-03-10 18:17:44 -06:00
Ross Thompson
1aa87c9f3a
Moved subwordwrite to lsu directory.
2022-03-10 18:15:25 -06:00
Ross Thompson
d0cf41dbe4
Simplified byte write enable logic.
2022-03-10 18:13:35 -06:00
Ross Thompson
396c97fc36
Byte write enables are passing all configs now.
2022-03-10 17:26:32 -06:00
Ross Thompson
d8e71e8e35
Progress on the path to getting all configs working with byte write enables.
2022-03-10 17:02:52 -06:00
Ross Thompson
67ef46ea92
Partially working byte write enables. Works for cache, but not dtim or bus only.
2022-03-10 16:11:39 -06:00
Ross Thompson
7a129c75cd
Added byte write enables to cache SRAMs.
2022-03-10 15:48:31 -06:00
David Harris
bc2b757952
bit write update
2022-03-09 19:09:20 +00:00
David Harris
27f09ffb33
Refactored SRAM bit write enable
2022-03-09 17:49:28 +00:00
David Harris
89e0830883
Updated testbench to read expected flags
2022-03-09 13:58:17 +00:00
Ross Thompson
95bb4cc8a8
Minor cleanup to interlockfsm.
2022-03-08 23:38:58 -06:00
Ross Thompson
9b113149b6
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-03-08 18:05:35 -06:00
Ross Thompson
0310fe858f
Comments.
2022-03-08 18:05:25 -06:00
Ross Thompson
75e93baaee
Marked signals for name changes.
2022-03-08 17:41:02 -06:00
David Harris
00908132e6
Added more test cases and rounding modes to fma test generator
2022-03-08 23:29:29 +00:00
David Harris
c8f2dce026
fma16_testgen.c test cases
2022-03-08 23:18:18 +00:00
Ross Thompson
3ec32d7ce8
Removed unused signal.
2022-03-08 16:58:26 -06:00
Ross Thompson
d78ba777a4
Added parameter to spillsupport.
2022-03-08 16:38:48 -06:00
Ross Thompson
7b96b3f73c
Moved cacheable signal into cache.
2022-03-08 16:34:02 -06:00
David Harris
7391c6d338
Checked in fma16_template.v
2022-03-06 13:29:35 +00:00
David Harris
2cea3349ad
LSU/Cache code review notes
2022-03-04 00:07:31 +00:00
David Harris
6431ad4a8b
Fixed fma files to stop breaking synthesis. Changed Makefiles to skip Imperas
2022-03-03 15:38:08 +00:00
David Harris
8e83aaeced
fma file fixes
2022-03-02 23:47:01 +00:00
bbracker
11423d1d17
but apparently QEMU doesn't show UXL in SSTATUS
2022-03-02 22:44:19 +00:00
bbracker
6d7bc928af
update SXL UXL bits in MSTATUS to match new QEMU trace
2022-03-02 22:15:57 +00:00
David Harris
c543fedc60
removed imperas-riscv-tests
2022-03-02 17:28:20 +00:00
David Harris
0ecfff7e3a
FMA project ready to start
2022-03-01 20:58:08 +00:00
David Harris
329fea9329
Renamed unpacking unit to unpack and renamed WriteDataW to ResultW in IEU datapath
2022-02-28 20:50:51 +00:00
David Harris
2ea93c4ac3
adrdecs comments
2022-02-28 20:33:41 +00:00
David Harris
2de31a15da
Modified address decoder for native access to CLINT
2022-02-28 19:13:14 +00:00
David Harris
3a43450ac9
hptw cleanup for synthesis
2022-02-28 05:54:34 +00:00
David Harris
f4be78ecc3
Created softfloat_demo showcasing how to do math with SoftFloat
2022-02-27 18:17:21 +00:00
David Harris
3675a813c6
Linking against riscv-isa-sim SoftFloat library for RISC-V NaN behavior
2022-02-27 17:23:33 +00:00
David Harris
62d62f9a9e
Moved FMA back into source tree to facilitate synthesis
2022-02-27 15:41:41 +00:00
David Harris
c35a071203
Moved fma directory
2022-02-27 14:20:15 +00:00
David Harris
283a25e1a7
fma simulation infrastructure
2022-02-27 04:36:43 +00:00
David Harris
40bc380073
fma passing multiply vectors
2022-02-27 04:36:01 +00:00
David Harris
f29cc4b33f
simplified fma Makefile
2022-02-26 19:55:42 +00:00
David Harris
b2db58e982
Made softfloat.a a symlink
2022-02-26 19:53:04 +00:00
David Harris
a9f9cfa5b6
Added start of fma
2022-02-26 19:51:19 +00:00
Ross Thompson
730fdb029a
Fixed bug with DAPageFault being wrong when HPTW writes not supported.
2022-02-23 10:54:34 -06:00
Ross Thompson
6f53f7943f
More spillsupport more structual.
2022-02-23 10:27:14 -06:00
Ross Thompson
19ec874641
Fixed bug with spill support and Instruction DA Page Faults.
2022-02-23 10:16:12 -06:00
Ross Thompson
15f6871a8d
Added generates to pcnextf muxes for privileged and caches.
2022-02-22 22:45:00 -06:00
Ross Thompson
59f04f2518
Minor busdp cleanup.
2022-02-22 17:28:26 -06:00
Ross Thompson
ea29291024
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-22 14:45:53 -06:00
Ross Thompson
971dd494f6
Clarified interlockfsm.
2022-02-22 11:31:28 -06:00
bbracker
2322e66f9f
fix lint bugs in PLIC and UART
2022-02-22 05:04:18 +00:00
bbracker
ac114e1c6d
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-02-22 04:27:50 +00:00
bbracker
c26526c9f3
change RX side of UART to aslo be LSB-first
2022-02-22 03:34:08 +00:00
Ross Thompson
1ab2e7590b
Added some clearity to lsuvirtmem.sv.
2022-02-21 17:20:58 -06:00
Ross Thompson
8a280f211f
Annotated IFU for mux changes.
2022-02-21 17:20:34 -06:00
Ross Thompson
ace743ae91
Changed HPTWRead/HPTWWrite to be HPTWRW to be similar to MemRW.
2022-02-21 16:54:38 -06:00
Ross Thompson
414e73edd9
Cleaned up names in lsuvirtmem.
2022-02-21 16:44:30 -06:00
Ross Thompson
456a54166a
Minor cleanup of lsu.
2022-02-21 12:46:06 -06:00
Ross Thompson
5d9ad011d2
Moved mux into lsuvirtmem.
2022-02-21 09:31:29 -06:00
Ross Thompson
8af055c78e
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-21 09:06:09 -06:00
Ross Thompson
a60332b455
Minor changes to LSU.
2022-02-19 14:38:17 -06:00
David Harris
4e194b2576
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-02-18 23:08:47 +00:00
David Harris
a88302f0d7
Removed problematic warning about reaching default state in HPTW
2022-02-18 23:08:40 +00:00
Ross Thompson
0bd533473c
New config option to enable hptw writes to PTE in memory to update Access and Dirty bits.
2022-02-17 17:19:41 -06:00
Ross Thompson
a7b774e453
Accidentally cleared dirty bit when setting access bit in hptw.
2022-02-17 16:20:20 -06:00
Ross Thompson
7dffcba182
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-17 14:49:37 -06:00
Ross Thompson
d152733a17
Rough implementation passing regression test with hptw atomic writes to memory.
2022-02-17 14:46:11 -06:00
David Harris
3036de316a
Started make allsynth to try many experiments
2022-02-17 17:57:02 +00:00
Ross Thompson
4cfb601dc8
Fixed a bunch of the virtual memory changes. Now supports atomic update of PTE in memory concurrent with TLB.
2022-02-17 10:04:18 -06:00
Ross Thompson
565ca4e4a3
Broken state. address translation not working after changes to hptw to support atomic updates to PT.
2022-02-16 23:37:36 -06:00
Ross Thompson
beac362364
Moved a few muxes around after sww changes.
2022-02-16 15:43:03 -06:00
Ross Thompson
6a2bcfcd01
cleanup of signal names.
2022-02-16 15:29:08 -06:00
Ross Thompson
84edb8b5d5
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-16 15:22:35 -06:00
Ross Thompson
bd7343b791
Modified lsu and uncore so only 1 sww is present. The sww is in the LSU if there is a cache or dtim. uncore.sv contains the sww if there is no local memory in the LSU. This is necessary as the subword write needs the read data to be valid and that read data is not aviable in the correct cycle in the LSU if there is no dtim or cache. Muxing could be done to provide the correct read data, but it adds muxes to the critical path.
2022-02-16 15:22:19 -06:00
David Harris
131a1a4ded
Cleaned warning on HPTW default state
2022-02-16 17:40:13 +00:00
David Harris
799736632b
Register file comments about reset
2022-02-16 17:21:05 +00:00
Ross Thompson
a64839d999
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-16 09:48:16 -06:00
David Harris
72e83db9fe
removed csrn and all of its outputs because depricated
2022-02-15 19:59:29 +00:00
David Harris
d3034c4f01
Mostly removed N_SUPPORTED
2022-02-15 19:50:44 +00:00
David Harris
f734afb866
Just needed to recompile - all good. Now removed uretM because N-mode is depricated
2022-02-15 19:48:49 +00:00
David Harris
1326ade1a0
Removed depricated N-mode support and SI/EDELEG registers. rv64gc_wally64priv tests are failing, but seem to be failing before this change.
2022-02-15 19:20:41 +00:00
Ross Thompson
6076f90bbc
Cache mods to be consistant with diagrams.
2022-02-14 12:40:51 -06:00
David Harris
1d5c8a7b98
t push
...
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-02-14 01:22:22 +00:00
Ross Thompson
1bb4d46ac1
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-13 18:21:15 -06:00
Ross Thompson
e852cb8a31
Eliminated more ports in cacheway.
2022-02-13 15:53:46 -06:00
Ross Thompson
1d7949513d
More cache cleanup.
2022-02-13 15:47:27 -06:00
Ross Thompson
7ffbc6b2ab
Changed names of signals in cache.
2022-02-13 15:06:18 -06:00
Ross Thompson
a5ad4331ec
More cache cleanup.
2022-02-13 12:38:39 -06:00
David Harris
b360e7b941
Synthesis cleanup
2022-02-12 06:25:12 +00:00
David Harris
a34cbdb7d0
Synthesis script cleanup, eliminated privileged instructiosn from controller when ZICSR_SUPPORTED = 0
2022-02-12 05:50:34 +00:00
Ross Thompson
dd944265aa
Formating improvements to cache.
2022-02-11 23:10:58 -06:00
Ross Thompson
bf173b035c
More cache simplifications.
2022-02-11 22:54:05 -06:00
Ross Thompson
16abe90a0d
Reduced seladr to 1 bit as second bit is same as selflush.
2022-02-11 22:41:36 -06:00
Ross Thompson
b11e9eca7b
Reduced complexity of the address selection during flush.
2022-02-11 22:27:27 -06:00
Ross Thompson
1255e82154
Removed redundant signals from cache.
2022-02-11 22:23:47 -06:00
Ross Thompson
52894a7a4f
Cache fsm simplifications.
2022-02-11 15:16:45 -06:00
Ross Thompson
e2e0a4f595
Removed STATE_CPU_BUSY_FINISH_AMO from cache. This is redundant with STATE_CPU_BUSY.
2022-02-11 15:09:00 -06:00
Ross Thompson
0f2ac0cb24
Simplified cache fsm.
2022-02-11 14:54:57 -06:00
Ross Thompson
1c83914662
Fixed bug.
...
It was possible for DTLBMissM to prevent a dcache flush.
2022-02-11 14:00:01 -06:00
Ross Thompson
febd019854
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-11 10:47:21 -06:00
Ross Thompson
6d12010d02
Fixed subtle and infrequenct bug.
...
Loading buildroot at 483M instructions started with a spill + ITLBMiss. The spillsupport logic allowed transition to the second access only after the bus/cache completed the first operation. However the BusStall was suppressed if ITLBMissF occurs resulting in the spillfsm advancing to the second operation. Now the spill logic also takes in ITLBMissF and prevents the early transition to the second access.
2022-02-11 10:46:06 -06:00
David Harris
de5e80696d
Cleaned up synthesis warnings
2022-02-11 01:15:16 +00:00
Ross Thompson
689c32215f
Fixed bugs in ifu spills and missing reset on bus data register.
2022-02-10 18:11:57 -06:00
Ross Thompson
5fd22caed4
Replacement policy cleanup.
2022-02-10 11:42:40 -06:00
Ross Thompson
f716cce832
Replacement policy cleanup.
2022-02-10 11:40:10 -06:00
Ross Thompson
104a9acf81
Cleanup.
2022-02-10 11:27:15 -06:00
Ross Thompson
fdb4f909fc
Cleanup + critical path optimizations.
2022-02-10 11:11:16 -06:00
Ross Thompson
88c7a94aa9
Cache name clarifications.
2022-02-10 10:50:17 -06:00
Ross Thompson
32eee5a06a
More cache cleanup.
2022-02-10 10:43:37 -06:00
Ross Thompson
91f2b5adf5
structural muxes.
2022-02-09 19:36:21 -06:00
Ross Thompson
7ff715f44f
More cache cleanup.
2022-02-09 19:29:15 -06:00
Ross Thompson
754bd41fde
Cleaned up comments.
2022-02-09 19:21:35 -06:00
Ross Thompson
36ab78ef3b
Removed all possilbe paths to PreSelAdr from TrapM.
2022-02-09 19:20:10 -06:00
Ross Thompson
7810a09782
Annotated the final changes required to move sram address off the critial path.
2022-02-08 18:17:31 -06:00
Ross Thompson
30d6514661
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-08 17:52:15 -06:00
Ross Thompson
4a7ebb3757
Cache cleanup write enables.
2022-02-08 17:52:09 -06:00
Ross Thompson
bdb3794d5e
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-08 15:43:18 -06:00
Ross Thompson
c2907ec0f4
Cleanup IFU.
2022-02-08 14:54:53 -06:00
Ross Thompson
038897f448
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-08 14:47:15 -06:00
Ross Thompson
4273775a2b
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-08 14:22:19 -06:00
Ross Thompson
e02bc8db67
rv32e works for now. Still need to optimize.
2022-02-08 14:21:55 -06:00
Ross Thompson
f211fe635a
Moved some muxes back into the bp.
2022-02-08 14:17:44 -06:00
David Harris
1479762ae9
RAM simplification
2022-02-08 20:15:23 +00:00
Ross Thompson
aa12d90272
Temporary commit which gets the no branch predictor implementation working.
2022-02-08 14:13:55 -06:00
Ross Thompson
8a2ee22395
Finished merge.
2022-02-08 11:36:24 -06:00
Ross Thompson
e2191e3637
Preparing to make a major change to the cache's write enables.
2022-02-08 09:47:01 -06:00
David Harris
c61cd55c5c
Merged TIM and regular testbenches. RV32e now working and back in regression.
2022-02-08 12:18:13 +00:00
Ross Thompson
5c9e23527d
cachefsm cleanup.
2022-02-07 22:09:56 -06:00
Ross Thompson
da2dca9816
Removed VDWriteEnable.
2022-02-07 21:59:18 -06:00
Ross Thompson
161f907cae
more partial cleanup of fsm and write enables.
2022-02-07 17:41:56 -06:00
Ross Thompson
359a23237d
Progress towards simplifying the cache's write enables.
2022-02-07 17:23:09 -06:00
Ross Thompson
188fe28691
more cleanup.
2022-02-07 13:29:19 -06:00
Ross Thompson
9510a33c15
More cachefsm cleanup.
2022-02-07 13:19:37 -06:00
Ross Thompson
708e0cf183
More cachefsm cleanup.
2022-02-07 12:30:27 -06:00
Ross Thompson
5539a5fa6f
More cachefsm cleanup.
2022-02-07 11:16:20 -06:00
Ross Thompson
6668956351
More cachefsm cleanup.
2022-02-07 11:12:28 -06:00
Ross Thompson
5536e3ca90
More cachefsm cleanup.
2022-02-07 10:54:22 -06:00
Ross Thompson
529d8b629a
Cache cleanup.
2022-02-07 10:43:58 -06:00
Ross Thompson
41a79556e0
More cachfsm cleanup.
2022-02-07 10:33:50 -06:00
David Harris
99f3d7a7f6
Reverted cache change
2022-02-07 14:47:20 +00:00
David Harris
45dc9c1ae6
Cache syntax cleanup
2022-02-07 14:43:24 +00:00
Ross Thompson
0b66106925
More cachefsm cleanup.
2022-02-06 21:50:44 -06:00
Ross Thompson
dd6baa9ed4
started cachefsm cleanup.
2022-02-06 21:39:38 -06:00
David Harris
9b55848ffc
Added E tests to wally-riscv-arch-test rv32i_m/I and fixed cyclic path in rv32e configuration
2022-02-06 01:22:40 +00:00
Ross Thompson
d21be9d998
Added config to allow using the save/restore or replay implementation to handle sram clocked read delay.
2022-02-04 23:49:07 -06:00
Ross Thompson
ea84211ff9
Removed unused ports from caches and buses.
2022-02-04 22:52:51 -06:00
Ross Thompson
011ad09341
Cleanup.
2022-02-04 22:40:51 -06:00
Ross Thompson
4074f695e0
Moved the hwdata mux back into the busdp.
2022-02-04 22:39:13 -06:00
Ross Thompson
40eb055861
Merged together the two sub cache line read muxes.
...
One mux was used for loads and the other for eviction.
2022-02-04 22:30:04 -06:00
David Harris
72bc64ef28
Temporarily changed rv32e config to use TIM, but it still fails. Added rv32e tests.
2022-02-05 04:16:18 +00:00
Ross Thompson
290430cda8
Moved the sub cache line read logic to lsu/ifu.
2022-02-04 20:42:53 -06:00
Ross Thompson
725852362e
Got separate module for the sub cache line read.
2022-02-04 20:23:09 -06:00
Ross Thompson
cdd599e340
Second optimization of save/restore.
2022-02-04 14:35:12 -06:00
Ross Thompson
459054900f
Optimization of cache save/restore.
2022-02-04 14:21:04 -06:00
Ross Thompson
7c1f7e335c
Working first cut of the cache changes moving the replay to a save/restore.
...
The current implementation is too expensive costing (tag+linelen)*numway flip flops and muxes.
2022-02-04 13:31:32 -06:00
David Harris
ee3300bcd2
sram1rw cleanup
2022-02-03 18:03:22 +00:00
David Harris
97d31cec21
sram1rw cleanup
2022-02-03 17:50:23 +00:00
David Harris
f9dd79d3e3
cachereplacementpolicy cleanup
2022-02-03 17:19:14 +00:00
David Harris
034ff5462c
cachereplacementpolicy cleanup
2022-02-03 17:18:48 +00:00
David Harris
65f3bf4e0a
cacheway cleanup
2022-02-03 16:52:22 +00:00
David Harris
eef04eed84
cacheway cleanup
2022-02-03 16:33:01 +00:00
David Harris
4d09510af9
cacheway cleanup
2022-02-03 16:07:55 +00:00
David Harris
7f237220dd
cacheway cleanup
2022-02-03 16:00:57 +00:00
David Harris
a6708ed887
cache cleanup
2022-02-03 15:36:11 +00:00
David Harris
38bbe23d14
More config file cleanup; 32ic tests broken
2022-02-03 01:08:34 +00:00
David Harris
da8819d64b
changed DMEM and IMEM configurations to support BUS/TIM/CACHE
2022-02-03 00:41:09 +00:00
David Harris
02071700d6
Removed Busybear dependencies
2022-02-02 20:28:21 +00:00
Ross Thompson
6c5b0bec40
More cleanup of IFU.
2022-02-01 14:32:27 -06:00
Ross Thompson
85d510e315
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-01 10:50:38 -06:00
Ross Thompson
73edd50120
Updated fpga's bootloader to reflect the changes to the gpio address change.
2022-02-01 10:43:24 -06:00
Ross Thompson
1f0821da0d
IFU and LSU now share the same busdp module.
2022-01-31 16:25:41 -06:00
Ross Thompson
86bac2a083
partial ifu cleanup.
2022-01-31 16:08:53 -06:00
Ross Thompson
e4ee630a3e
cleanup.
2022-01-31 13:29:04 -06:00
Ross Thompson
c9a163b8fd
Repaired linux-wave.do
2022-01-31 12:54:18 -06:00
Ross Thompson
4422e2f91c
Repaired wavefile and fixed modelsim warning.
2022-01-31 12:34:17 -06:00
Ross Thompson
c2b2fae98d
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-31 12:17:37 -06:00
Ross Thompson
f4e62bcb54
Cleanup busdp.
2022-01-31 12:17:07 -06:00
Ross Thompson
31da37dd0f
Moved lsu virtual memory logic into separate module.
2022-01-31 11:56:03 -06:00
Ross Thompson
9cd502d0af
Encapsulated dtim.
2022-01-31 11:23:55 -06:00
Ross Thompson
c939eb20eb
Removed unused signals in the LSU.
2022-01-31 10:35:35 -06:00
Ross Thompson
5fe30ff8a9
Moved atomic logic to own module.
2022-01-31 10:28:12 -06:00
Ross Thompson
a4f6653cd8
Encapsulated the bus data path into a separate module.
2022-01-31 10:15:48 -06:00
David Harris
090533cfe9
Replaced || and && with | and &
2022-01-31 01:07:35 +00:00
Ross Thompson
ac50a36aac
LSU and IFU cleanup.
2022-01-28 15:26:06 -06:00
Ross Thompson
2e00186eea
Updated wave.do to match the ifu/lsu changes.
2022-01-28 14:37:15 -06:00
Ross Thompson
42d60235f0
Clean up of mmu instances in IFU and LSU.
2022-01-28 14:02:05 -06:00
Ross Thompson
c5e0024e9f
Moved spills to own module.
2022-01-28 13:40:35 -06:00
Ross Thompson
06209c417f
Cleaned up the InstrMisalignedFault.
2022-01-28 13:19:24 -06:00
Ross Thompson
862bf2faae
Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault.
2022-01-27 17:11:27 -06:00
Ross Thompson
d15cb64bdf
Relocated the misalignment faults.
2022-01-27 16:03:00 -06:00
David Harris
30cc27e719
IFU cleanup
2022-01-27 17:18:55 +00:00
David Harris
5ab06fef20
IFU cleanup
2022-01-27 16:41:57 +00:00
David Harris
bdd5796f3a
Optimized out second adder from IFU for PC+2
2022-01-27 16:06:24 +00:00
David Harris
7f91170bab
Comments in LSU code about restructuring
2022-01-27 15:53:59 +00:00
Ross Thompson
db0a0bd29e
BPPredWrongM needs to be 0 when there is no branch predictor. BPPredWRongM is only used when there is an icacheflush.
2022-01-27 07:59:59 -06:00
Ross Thompson
cc5a9a015b
Removed mux in PCNextF logic. Minor IFU improvements.
2022-01-26 22:33:26 -06:00
Ross Thompson
42ef1e22e5
1. Modified the cache so it can handle the reset delay internally. This removes the mux from the IFU.
...
2. Removed the write address delay from simpleram.sv
3. Fixed rv32tim and rv32ic mode to handle missalignment correctly.
4. Added imperas32i and imperas32c to rv32tim mode.
2022-01-26 18:23:39 -06:00
Ross Thompson
fc86651937
IFU simplifications.
2022-01-26 13:54:59 -06:00
Ross Thompson
840e814e95
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-25 19:21:04 -06:00
David Harris
8d04e83c9f
simpleram simplification
2022-01-25 19:46:13 +00:00
David Harris
9da1ed4ed9
simpleram simplification
2022-01-25 19:40:07 +00:00
David Harris
a86a9f5c2a
simpleram simplification
2022-01-25 18:26:31 +00:00
David Harris
e3136c9a1e
simpleram address simplification
2022-01-25 18:17:33 +00:00
David Harris
7ad2eb009a
simpleram address simplification
2022-01-25 18:00:50 +00:00
David Harris
6a555032eb
simpleram clk and reset simplification
2022-01-25 17:34:15 +00:00
David Harris
cf50beb958
Start of IFU cleanup
2022-01-25 17:31:53 +00:00
Ross Thompson
8ef70389d3
Added spill support back into the IROM IFU.
2022-01-21 15:50:54 -06:00
Ross Thompson
9982549057
Changed the IROM and DTIM memories to behave like edge-triggered srams.
2022-01-21 15:42:54 -06:00
Ross Thompson
e2343699d1
Factored out InstrValidNotFlushedM from each csr*.sv to csr.sv
2022-01-20 16:39:54 -06:00
David Harris
07425369fc
Renamed wallypipelinedhart to wallypipelinedcore
2022-01-20 16:02:08 +00:00
Ross Thompson
acec56c27e
Added PCNextF and PostSpillInstrRawF to ila.
2022-01-19 14:05:14 -06:00
Ross Thompson
4a75e69457
Merged in the debug ila updates.
2022-01-18 17:29:21 -06:00
Ross Thompson
28859f959b
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-18 17:19:59 -06:00
Ross Thompson
a5f773220e
Updated CSR modules to prevent writting the registers when flushing. This only effects architecture writes not side effect writes.
2022-01-18 17:19:33 -06:00
David Harris
55b4423329
Added E extension, and downloaded riscv-dv and embench-iot to addins
2022-01-17 14:42:59 +00:00
David Harris
bd320c2f76
lsu cleanup down to 346 lines
2022-01-15 01:19:44 +00:00
David Harris
325724f556
LSU Cleanup
2022-01-15 01:11:17 +00:00
