Ross Thompson 7c1f7e335c Working first cut of the cache changes moving the replay to a save/restore. ... The current implementation is too expensive costing (tag+linelen)*numway flip flops and muxes.		2022-02-04 13:31:32 -06:00
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cache	Working first cut of the cache changes moving the replay to a save/restore.	2022-02-04 13:31:32 -06:00
ebu	Renamed wallypipelinedhart to wallypipelinedcore	2022-01-20 16:02:08 +00:00
fpu	Replaced || and && with | and &	2022-01-31 01:07:35 +00:00
generic	1. Modified the cache so it can handle the reset delay internally. This removes the mux from the IFU.	2022-01-26 18:23:39 -06:00
hazard	Renamed LSUStall to LSUStallM	2022-01-15 00:24:16 +00:00
ieu	cacheway cleanup	2022-02-03 16:07:55 +00:00
ifu	changed DMEM and IMEM configurations to support BUS/TIM/CACHE	2022-02-03 00:41:09 +00:00
lsu	cache cleanup	2022-02-03 15:36:11 +00:00
mmu	More config file cleanup; 32ic tests broken	2022-02-03 01:08:34 +00:00
muldiv	Better solution to the integer divider interrupt interaction.	2022-01-12 14:22:18 -06:00
privileged	More config file cleanup; 32ic tests broken	2022-02-03 01:08:34 +00:00
uncore	Comments in LSU code about restructuring	2022-01-27 15:53:59 +00:00
wally	Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault.	2022-01-27 17:11:27 -06:00
sdc