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simpleram simplification

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This commit is contained in:
David Harris 2022-01-25 19:46:13 +00:00
parent 9da1ed4ed9
commit 8d04e83c9f
2 changed files with 3 additions and 0 deletions
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2
pipelined/src/ifu/ifu.sv
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@ -233,6 +233,8 @@ module ifu (
if (`MEM_IROM) begin : irom
logic [`XLEN-1:0] FinalInstrRawF_FIXME;
// *** adjust interface so write address doesn't need delaying
// *** modify to be a ROM rather than RAM
simpleram #(
.BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram (
.clk,

1
pipelined/src/lsu/lsu.sv
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@ -245,6 +245,7 @@ module lsu (
logic SelUncachedAdr;
if (`MEM_DTIM) begin : dtim
// *** adjust interface so write address doesn't need delaying; switch to standard RAM?
simpleram #(.BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram (
.clk,
.a(CPUBusy ? IEUAdrM[31:0] : IEUAdrE[31:0]),