Ross Thompson beac362364 Moved a few muxes around after sww changes.		2022-02-16 15:43:03 -06:00
..
cache	Cache mods to be consistant with diagrams.	2022-02-14 12:40:51 -06:00
ebu	Cleaned up synthesis warnings	2022-02-11 01:15:16 +00:00
fpu	Replaced || and && with | and &	2022-01-31 01:07:35 +00:00
generic	RAM simplification	2022-02-08 20:15:23 +00:00
hazard	Renamed LSUStall to LSUStallM	2022-01-15 00:24:16 +00:00
ieu	Register file comments about reset	2022-02-16 17:21:05 +00:00
ifu	Moved a few muxes around after sww changes.	2022-02-16 15:43:03 -06:00
lsu	Moved a few muxes around after sww changes.	2022-02-16 15:43:03 -06:00
mmu	Cleaned warning on HPTW default state	2022-02-16 17:40:13 +00:00
muldiv	Better solution to the integer divider interrupt interaction.	2022-01-12 14:22:18 -06:00
privileged	Cleaned warning on HPTW default state	2022-02-16 17:40:13 +00:00
uncore	Modified lsu and uncore so only 1 sww is present. The sww is in the LSU if there is a cache or dtim. uncore.sv contains the sww if there is no local memory in the LSU. This is necessary as the subword write needs the read data to be valid and that read data is not aviable in the correct cycle in the LSU if there is no dtim or cache. Muxing could be done to provide the correct read data, but it adds muxes to the critical path.	2022-02-16 15:22:19 -06:00
wally	Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault.	2022-01-27 17:11:27 -06:00
sdc	piplined directory cleanup	2022-01-07 12:43:50 +00:00