Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main

Makefile

@@ -9,9 +9,14 @@ install:
 	cp ${RISCV}/riscv-isa-sim/arch_test_target/spike/Makefile.include addins/riscv-arch-test/
 	sed -i '/export TARGETDIR ?=/c\export TARGETDIR ?= ${RISCV}/riscv-isa-sim/arch_test_target' addins/riscv-arch-test/Makefile.include
 	echo export RISCV_PREFIX = riscv64-unknown-elf- >> addins/riscv-arch-test/Makefile.include
+	cd tests/linux-testgen/linux-testvectors; source ./tvLinker.sh # needs to be run in local directory
+	rm tests/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe
+	ln -s ${RISCV}/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe tests/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe
 
 regression:
 	make -C pipelined/regression
 
-
+clean:
+	make clean -C pipelined/regression
+	
 

README.md

@@ -3,4 +3,31 @@ Configurable RISC-V Processor
 
 Wally is a 5-stage pipelined processor configurable to support all the standard RISC-V options, incluidng RV32/64, A, C, F, D, and M extensions, FENCE.I, and the various privileged modes and CSRs.  It is written in SystemVerilog.  It passes the RISC-V Arch Tests and Imperas tests.  As of October 2021, it boots the first 10 million instructions of Buildroot Linux.
 
+If you are new to using Linux and Github, follow the steps in the RISCV SoC Design textbook to:
+
+
 See Chapter 2 of draft book of how to install and compile tests.
+
+	Download and install x2go - A.1
+	Download and install VSCode - A.4.2
+	Make sure you can log into Tera acceptly via x2go and via a terminal
+		Terminal on Mac, cmd on Windows, xterm on Linux
+		See A.1 about ssh -Y login from a terminal
+	Git started with Git configuration and authentication: B.1
+
+Then follow Section 2.2.2 to clone the repo, source setup,  make the tests and run regression
+
+	$ cd
+	$ export RISCV=/opt/riscv
+	$ git clone --recurse-submodules https://github.com/davidharrishmc/riscv-wally
+	$ cd riscv-wally
+	$ source ./setup.sh
+	$ make
+	$ cd pipelined/regression
+	$ ./regression-wally       (depends on having Questa installed)
+
+Add the following lines to your .bashrc or .bash_profile
+
+	if [ -f ~/riscv-wally/setup.sh ]; then
+		source ~/riscv-wally/setup.sh
+	fi

addins/riscv-dv

@@ -1 +1 @@
-Subproject commit 96c1ee6f371f2754c45b4831fcab95f6671689d9
+Subproject commit a7e27bc046405f0dbcde091be99f5a5d564e2172

benchmarks/embench/Makefile

@@ -0,0 +1,15 @@
+# Makefile added 1/20/22 David_Harris@hmc.edu
+# Compile Embench for Wally
+
+all: Makefile
+	../../addins/embench-iot/build_all.py --arch riscv32 --chip generic --board ri5cyverilator --cflags "-O2 -march=rv32i -mabi=ilp32 -mcmodel=medany" --cc riscv64-unknown-elf-gcc 
+	./benchmark_size.py 
+	./benchmark_speed.py
+
+# view with
+# more `ls -t | head -1`
+
+# --cflags "-O2 -g -nostartfiles"
+
+
+#riscv64-unknown-elf-gcc -O2 -g -nostartfiles -I/home/harris/riscv-wally/addins/embench-iot/support -I/home/harris/riscv-wally/addins/embench-iot/config/riscv32/boards/ri5cyverilator -I/home/harris/riscv-wally/addins/embench-iot/config/riscv32/chips/generic -I/home/harris/riscv-wally/addins/embench-iot/config/riscv32 -DCPU_MHZ=1 -DWARMUP_HEAT=1 -o main.o /home/harris/riscv-wally/addins/embench-iot/support/main.c

benchmarks/embench/Makefile~

@@ -0,0 +1,7 @@
+# Makefile added 1/20/22 David_Harris@hmc.edu
+# Compile Embench for Wally
+
+all: Makefile
+	./build_all.py --arch riscv32 --chip generic --board ri5cyverilator --cc riscv64-unknown-elf-gcc 
+	./benchmark_size.py 
+	./benchmark_speed.py

examples/C/fir/Makefile

@@ -0,0 +1,33 @@
+TARGET = fir
+
+$(TARGET).objdump: $(TARGET)
+	riscv64-unknown-elf-objdump -S -D $(TARGET) > $(TARGET).objdump
+	spike $(TARGET)
+    
+$(TARGET): $(TARGET).c Makefile
+	riscv64-unknown-elf-gcc -o $(TARGET) -g -O\
+	  -march=rv64gc -mabi=lp64d -mcmodel=medany \
+	  -nostdlib -static -lm -fno-tree-loop-distribute-patterns \
+	  -T../common/test.ld -I../common \
+	  $(TARGET).c ../common/crt.S ../common/syscalls.c
+# Compiler flags:
+#  -o $(TARGET) defines the name of the output file
+#  -g generates debugging symbols for gdb
+#  -O turns on basic optimization; -O3 turns on heavy optimization; omit for no optimization
+#  -march=rv64gc -mabi=lp64d =mcmodel=medany generates code for RV64GC with doubles and long/ptrs = 64 bits
+#  -static forces static linking (no dynamic shared libraries on bare metal)
+#  -lm links the math library if necessary (when #include math.h)
+#  -nostdlib avoids inserting standard startup files and default libraries 
+#     because we are using crt.s on bare metal
+#  -fno-tree-loop-distribute-patterns turns replacing loops with memcpy/memset in the std library 
+#  -T specifies the linker file
+#  -I specifies the include path (e.g. for util.h)
+#  The last line defines the C files to compile.  
+#    crt.S is needed as our startup file to initialize the processor
+#    syscalls.c implements printf through the HTIF for Spike
+# other flags from riscv-tests makefiles that don't seem to be important
+#	  -ffast-math -DPREALLOCATE=1 -std=gnu99  \
+#     -fno-common -fno-builtin-printf -nostartfiles -lgcc \
+
+clean:
+	rm -f $(TARGET) $(TARGET).objdump

examples/C/fir/fir.c

@@ -0,0 +1,42 @@
+// fir.c
+// David_Harris@hmc.edu 20 January 2022
+// Finite Impulse Response Filter
+
+#include <stdio.h>  // supports printf
+#include "util.h"   // supports verify
+
+void fir(int N, int M, double X[], double c[], double Y[]) {
+  int i, n;
+  double sum; 
+
+  for (n=0; n<N; n++) {
+      sum = 0;
+      for (i=0; i<M; i++) {
+          sum += c[i]*X[n-i+(M-1)];
+      }
+      Y[n] = sum;
+  }
+}
+
+int main(void) {
+    double X[20] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20};
+    double c[5] = {0.2, 0.2, 0.2, 0.2, 0.2};
+    double Y[15];
+    double Yexpected[15] = {3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17}; 
+ 
+    setStats(1);
+    fir(15, 5, X, c, Y);
+    setStats(0);
+    // library linked doesn't support printing doubles, so convert to integers to print
+    for (int i=0; i<15; i++)  {
+        int tmp = Y[i];
+        printf("Y[%d] = %d\n", i, tmp);
+    }
+    // verifyDouble doesn't work exaclty because of rounding, so check for almost equal
+    for (int i=0; i<15; i++) {
+        if (fabs(Y[i] - Yexpected[i]) > 1e-10) {
+            return 1;
+        }
+    }
+    return 0;
+}

examples/asm/example/Makefile

@@ -1,9 +1,9 @@
 example.objdump: example
 	riscv64-unknown-elf-objdump -D example > example.objdump
     
-example: example.S
+example: example.S Makefile
 	riscv64-unknown-elf-gcc -o example -march=rv32i -mabi=ilp32 -mcmodel=medany \
-	    -nostartfiles -nostdlib -T../../link/link.ld  example.S
+	    -nostartfiles -T../../link/link.ld  example.S
 
 clean:
 	rm -f example example.objdump

examples/asm/sumtest/fir.c

@@ -1,38 +0,0 @@
-// fir.C
-// David_Harris@hmc.edu 25 December 2021
-// Finite Impulse Response Filter
-
-#include <math.h>
-
-#define N 2000
-#define M 100
-#define PI 3.14159
-
-double fir(double a[], double c[], double y[], int N, int M) {
-    int i, j
-    for (i=0; i<N-M; i++) {
-        y[i] = 0;
-        for (j=0; j<M; j++) {
-            y[i] += c[j] * a[M+i-j];
-        }
-    }
-}
-
-int main(void) {
-    double a[N], c[M], y[N-M];
-
-    int i;
-
-    // // step input with overlying high frequency sinusoid
-    for (i=0; i<N; i++) a[i] = (i < N/2) + 0.5 * cos(2*PI*i/50); 
-
-    // filter coeffieints: replace with a sinc function with sharper response
-    //for (i=0; i<M; i++) c[i] = 1.0/M; // low pass filter with equal coefficients
-    for (i=0; i<M; i++) c[i] = 2.0*B*(sin(2.0*B*i/10)/(2.0*B*i/10)); // low pass filter with equal coefficients
-
-    // inline assembly to measure time, with macro
-    fir(a, c, y, N, M);
-    // measure time again
-    // *** generate signature
-    // *** write_tohost
-}

examples/asm/sumtest/sumtest.reference_output

@@ -1,2 +1,2 @@
 000000000000000A
-000000000000001C
+000000000000001D

examples/link/link.ld

@@ -4,7 +4,7 @@ ENTRY(rvtest_entry_point)
 SECTIONS
 {
   . = 0x80000000;
-  .text : { *(.text) }
+  .text : { *(.text.init) }
   . = ALIGN(0x1000);
   .tohost : { *(.tohost) }
   . = ALIGN(0x1000);

examples/verilog/riscvsingle/riscvsingle.do

@@ -12,12 +12,12 @@ add wave /testbench/reset
 add wave -divider "Main Datapath"
 add wave /testbench/dut/PC
 add wave /testbench/dut/Instr
-add wave /testbench/dut/rvsingle/dp/SrcA
-add wave /testbench/dut/rvsingle/dp/SrcB
-add wave /testbench/dut/rvsingle/dp/Result
+add wave /testbench/dut/ieu/dp/SrcA
+add wave /testbench/dut/ieu/dp/SrcB
+add wave /testbench/dut/ieu/dp/Result
 add wave -divider "Memory Bus"
 add wave /testbench/MemWrite
-add wave /testbench/DataAdr
+add wave /testbench/IEUAdr
 add wave /testbench/WriteData
-run -all
+run 210
 view wave

examples/verilog/riscvsingle/riscvsingle.sv

@@ -1,20 +1,45 @@
+///////////////////////////////////////////
 // riscvsingle.sv
+//
+// Written: David_Harris@hmc.edu 9 January 2021
+// Modified: 
+//
+// Purpose: Simplified Single Cycle RISC-V Processor
+//          Adapted from DDCA RISC-V Edition
+//          Modified to match partitioning in RISC-V SoC Design
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// MIT LICENSE
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
+// software and associated documentation files (the "Software"), to deal in the Software 
+// without restriction, including without limitation the rights to use, copy, modify, merge, 
+// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
+// to whom the Software is furnished to do so, subject to the following conditions:
+//
+//   The above copyright notice and this permission notice shall be included in all copies or 
+//   substantial portions of the Software.
+//
+//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+//   OR OTHER DEALINGS IN THE SOFTWARE.
+////////////////////////////////////////////////////////////////////////////////////////////////
 
-// RISC-V single-cycle processor
-// From Section 7.6 of Digital Design & Computer Architecture
-// 27 April 2020
-// David_Harris@hmc.edu 
-// Sarah.Harris@unlv.edu
 
 // run 210
 // Expect simulator to print "Simulation succeeded"
 // when the value 25 (0x19) is written to address 100 (0x64)
 
 // Single-cycle implementation of RISC-V (RV32I)
-// User-level Instruction Set Architecture V2.2 (May 7, 2017)
+// User-level Instruction Set Architecture V2.2 
 // Implements a subset of the base integer instructions:
 //    lw, sw
-//    add, sub, and, or, slt, 
+//    add, sub, and, or, slt
 //    addi, andi, ori, slti
 //    beq
 //    jal
@@ -78,193 +103,188 @@
 //   sw           0100011   010       immediate
 //   jal          1101111   immediate immediate
 
-module testbench();
 
+/* verilator lint_on UNUSED */
+
+/* verilator lint_off COMBDLY */ 
+/* verilator lint_off INITIALDLY */ 
+/* verilator lint_off STMTDLY */ 
+
+module testbench();
   logic        clk;
   logic        reset;
-
-  logic [31:0] WriteData, DataAdr;
+  logic [31:0] WriteData, IEUAdr;
   logic        MemWrite;
 
   // instantiate device to be tested
-  top dut(clk, reset, WriteData, DataAdr, MemWrite);
+  riscvsinglecore dut(clk, reset, WriteData, IEUAdr, MemWrite);
   
   // initialize test
-  initial
-    begin
+  initial begin
       reset <= 1; # 22; reset <= 0;
-    end
+  end
 
   // generate clock to sequence tests
-  always
-    begin
+  always begin
       clk <= 1; # 5; clk <= 0; # 5;
-    end
+  end
 
   // check results
-  always @(negedge clk)
-    begin
+  always @(negedge clk) begin
       if(MemWrite) begin
-        if(DataAdr === 100 & WriteData === 25) begin
+        if(IEUAdr === 100 & WriteData === 25) begin
           $display("Simulation succeeded");
           $stop;
-        end else if (DataAdr !== 96) begin
+        end else if (IEUAdr !== 96) begin
           $display("Simulation failed");
           $stop;
         end
       end
-    end
+  end
 endmodule
 
-module top(input  logic        clk, reset, 
-           output logic [31:0] WriteData, DataAdr, 
-           output logic        MemWrite);
+module riscvsinglecore(
+  input  logic        clk, reset, 
+  output logic [31:0] WriteData, IEUAdr, 
+  output logic        MemWrite);
 
-  logic [31:0] PC, Instr, ReadData;
-  
-  // instantiate processor and memories
-  riscvsingle rvsingle(clk, reset, PC, Instr, MemWrite, DataAdr, 
-                       WriteData, ReadData);
-  imem imem(PC, Instr);
-  dmem dmem(clk, MemWrite, DataAdr, WriteData, ReadData);
+  logic [31:0] PC, PCPlus4, Instr, ReadData;
+  logic        PCSrc;
+
+  ifu ifu(.clk, .reset, .PCSrc, .IEUAdr, .Instr, .PC, .PCPlus4);
+  ieu ieu(.clk, .reset, .Instr, .PC, .PCPlus4, .PCSrc, .MemWrite, .IEUAdr, .WriteData, .ReadData);
+  lsu lsu(.clk, .MemWrite, .IEUAdr, .WriteData, .ReadData);
 endmodule
 
-module riscvsingle(input  logic        clk, reset,
-                   output logic [31:0] PC,
-                   input  logic [31:0] Instr,
-                   output logic        MemWrite,
-                   output logic [31:0] ALUResult, WriteData,
-                   input  logic [31:0] ReadData);
+module ifu(
+  input  logic        clk, reset,
+  input  logic        PCSrc,
+  input  logic [31:0] IEUAdr, 
+  output logic [31:0] Instr, PC, PCPlus4);
 
-  logic       ALUSrc, RegWrite, Jump, Zero;
-  logic [1:0] ResultSrc, ImmSrc;
-  logic [2:0] ALUControl;
-
-  controller c(Instr[6:0], Instr[14:12], Instr[30], Zero,
-               ResultSrc, MemWrite, PCSrc,
-               ALUSrc, RegWrite, Jump,
-               ImmSrc, ALUControl);
-  datapath dp(clk, reset, ResultSrc, PCSrc,
-              ALUSrc, RegWrite,
-              ImmSrc, ALUControl,
-              Zero, PC, Instr,
-              ALUResult, WriteData, ReadData);
-endmodule
-
-module controller(input  logic [6:0] op,
-                  input  logic [2:0] funct3,
-                  input  logic       funct7b5,
-                  input  logic       Zero,
-                  output logic [1:0] ResultSrc,
-                  output logic       MemWrite,
-                  output logic       PCSrc, ALUSrc,
-                  output logic       RegWrite, Jump,
-                  output logic [1:0] ImmSrc,
-                  output logic [2:0] ALUControl);
-
-  logic [1:0] ALUOp;
-  logic       Branch;
-
-  maindec md(op, ResultSrc, MemWrite, Branch,
-             ALUSrc, RegWrite, Jump, ImmSrc, ALUOp);
-  aludec  ad(op[5], funct3, funct7b5, ALUOp, ALUControl);
-
-  assign PCSrc = Branch & Zero | Jump;
-endmodule
-
-module maindec(input  logic [6:0] op,
-               output logic [1:0] ResultSrc,
-               output logic       MemWrite,
-               output logic       Branch, ALUSrc,
-               output logic       RegWrite, Jump,
-               output logic [1:0] ImmSrc,
-               output logic [1:0] ALUOp);
-
-  logic [10:0] controls;
-
-  assign {RegWrite, ImmSrc, ALUSrc, MemWrite,
-          ResultSrc, Branch, ALUOp, Jump} = controls;
-
-  always_comb
-    case(op)
-    // RegWrite_ImmSrc_ALUSrc_MemWrite_ResultSrc_Branch_ALUOp_Jump
-      7'b0000011: controls = 11'b1_00_1_0_01_0_00_0; // lw
-      7'b0100011: controls = 11'b0_01_1_1_00_0_00_0; // sw
-      7'b0110011: controls = 11'b1_xx_0_0_00_0_10_0; // R-type 
-      7'b1100011: controls = 11'b0_10_0_0_00_1_01_0; // beq
-      7'b0010011: controls = 11'b1_00_1_0_00_0_10_0; // I-type ALU
-      7'b1101111: controls = 11'b1_11_0_0_10_0_00_1; // jal
-      default:    controls = 11'bx_xx_x_x_xx_x_xx_x; // non-implemented instruction
-    endcase
-endmodule
-
-module aludec(input  logic       opb5,
-              input  logic [2:0] funct3,
-              input  logic       funct7b5, 
-              input  logic [1:0] ALUOp,
-              output logic [2:0] ALUControl);
-
-  logic  RtypeSub;
-  assign RtypeSub = funct7b5 & opb5;  // TRUE for R-type subtract instruction
-
-  always_comb
-    case(ALUOp)
-      2'b00:                ALUControl = 3'b000; // addition
-      2'b01:                ALUControl = 3'b001; // subtraction
-      default: case(funct3) // R-type or I-type ALU
-                 3'b000:  if (RtypeSub) 
-                            ALUControl = 3'b001; // sub
-                          else          
-                            ALUControl = 3'b000; // add, addi
-                 3'b010:    ALUControl = 3'b101; // slt, slti
-                 3'b110:    ALUControl = 3'b011; // or, ori
-                 3'b111:    ALUControl = 3'b010; // and, andi
-                 default:   ALUControl = 3'bxxx; // ???
-               endcase
-    endcase
-endmodule
-
-module datapath(input  logic        clk, reset,
-                input  logic [1:0]  ResultSrc, 
-                input  logic        PCSrc, ALUSrc,
-                input  logic        RegWrite,
-                input  logic [1:0]  ImmSrc,
-                input  logic [2:0]  ALUControl,
-                output logic        Zero,
-                output logic [31:0] PC,
-                input  logic [31:0] Instr,
-                output logic [31:0] ALUResult, WriteData,
-                input  logic [31:0] ReadData);
-
-  logic [31:0] PCNext, PCPlus4, PCTarget;
-  logic [31:0] ImmExt;
-  logic [31:0] SrcA, SrcB;
-  logic [31:0] Result;
+  logic [31:0] PCNext;
 
   // next PC logic
   flopr #(32) pcreg(clk, reset, PCNext, PC); 
   adder       pcadd4(PC, 32'd4, PCPlus4);
-  adder       pcaddbranch(PC, ImmExt, PCTarget);
-  mux2 #(32)  pcmux(PCPlus4, PCTarget, PCSrc, PCNext);
- 
-  // register file logic
-  regfile     rf(clk, RegWrite, Instr[19:15], Instr[24:20], 
-                 Instr[11:7], Result, SrcA, WriteData);
-  extend      ext(Instr[31:7], ImmSrc, ImmExt);
-
-  // ALU logic
-  mux2 #(32)  srcbmux(WriteData, ImmExt, ALUSrc, SrcB);
-  alu         alu(SrcA, SrcB, ALUControl, ALUResult, Zero);
-  mux3 #(32)  resultmux(ALUResult, ReadData, PCPlus4, ResultSrc, Result);
+  mux2 #(32)  pcmux(PCPlus4, IEUAdr, PCSrc, PCNext);
+  irom        irom(PC, Instr);
 endmodule
 
-module regfile(input  logic        clk, 
-               input  logic        we3, 
-               input  logic [ 4:0] a1, a2, a3, 
-               input  logic [31:0] wd3, 
-               output logic [31:0] rd1, rd2);
+module irom(input  logic [31:0] a,
+            output logic [31:0] rd);
 
-  logic [31:0] rf[31:0];
+  logic [31:0] RAM[63:0];
+
+  initial
+      $readmemh("riscvtest.memfile",RAM);
+
+  assign rd = RAM[a[7:2]]; // word aligned
+endmodule
+
+module ieu(
+  input  logic        clk, reset,
+  input  logic [31:0] Instr,
+  input  logic [31:0] PC, PCPlus4,
+  output logic        PCSrc, MemWrite,
+  output logic [31:0] IEUAdr, WriteData,
+  input  logic [31:0] ReadData);
+
+  logic       RegWrite, Jump, Eq, ALUResultSrc, ResultSrc;
+  logic [1:0] ALUSrc, ImmSrc;
+  logic [1:0] ALUControl;
+
+  controller c(.Op(Instr[6:0]), .Funct3(Instr[14:12]), .Funct7b5(Instr[30]), .Eq,
+               .ALUResultSrc, .ResultSrc, .MemWrite, .PCSrc,
+               .ALUSrc, .RegWrite, .ImmSrc, .ALUControl);
+  datapath dp(.clk, .reset, .Funct3(Instr[14:12]),  
+              .ALUResultSrc, .ResultSrc, .ALUSrc, .RegWrite, .ImmSrc, .ALUControl, .Eq,
+              .PC, .PCPlus4, .Instr, .IEUAdr, .WriteData, .ReadData);
+endmodule
+
+module controller(
+  input  logic [6:0] Op,
+  input  logic       Eq,
+  input  logic [2:0] Funct3,
+  input  logic       Funct7b5,
+  output logic       ALUResultSrc,
+  output logic       ResultSrc,
+  output logic       MemWrite,
+  output logic       PCSrc, 
+  output logic       RegWrite, 
+  output logic [1:0] ALUSrc, ImmSrc,
+  output logic [1:0] ALUControl); 
+
+  logic       Branch, Jump;
+  logic       Sub, ALUOp;
+
+  logic [10:0] controls;
+
+  // Main decoder
+  always_comb
+    case(Op)
+    // RegWrite_ImmSrc_ALUSrc_ALUOp_ALUResultSrc_MemWrite_ResultSrc_Branch_Jump
+      7'b0000011: controls = 11'b1_00_01_0_0_0_1_0_0; // lw
+      7'b0100011: controls = 11'b0_01_01_0_0_1_0_0_0; // sw
+      7'b0110011: controls = 11'b1_xx_00_1_0_0_0_0_0; // R-type 
+      7'b0010011: controls = 11'b1_00_01_1_0_0_0_0_0; // I-type ALU
+      7'b1100011: controls = 11'b0_10_11_0_0_0_0_1_0; // beq
+      7'b1101111: controls = 11'b1_11_11_0_1_0_0_0_1; // jal
+      default:    controls = 11'bx_xx_xx_x_x_x_x_x_x; // non-implemented instruction
+    endcase
+  
+  assign {RegWrite, ImmSrc, ALUSrc, ALUOp, ALUResultSrc, MemWrite,
+          ResultSrc, Branch, Jump} = controls;
+
+  // ALU Control Logic
+  assign Sub = ALUOp & ((Funct3 == 3'b000) & Funct7b5 & Op[5] | (Funct3 == 3'b010));  // subtract or SLT
+  assign ALUControl = {Sub, ALUOp};
+
+  // PCSrc logic
+  assign PCSrc = Branch & Eq | Jump;
+endmodule
+
+module datapath(
+  input  logic        clk, reset,
+  input  logic [2:0]  Funct3,
+  input  logic        ALUResultSrc, ResultSrc, 
+  input  logic [1:0]  ALUSrc,
+  input  logic        RegWrite,
+  input  logic [1:0]  ImmSrc,
+  input  logic [1:0]  ALUControl,
+  output logic        Eq,
+  input  logic [31:0] PC, PCPlus4,
+  input  logic [31:0] Instr,
+  output logic [31:0] IEUAdr, WriteData,
+  input  logic [31:0] ReadData);
+
+  logic [31:0] ImmExt;
+  logic [31:0] R1, R2, SrcA, SrcB;
+  logic [31:0] ALUResult, IEUResult, Result;
+
+  // register file logic
+  regfile     rf(.clk, .WE3(RegWrite), .A1(Instr[19:15]), .A2(Instr[24:20]), 
+                 .A3(Instr[11:7]), .WD3(Result), .RD1(R1), .RD2(R2));
+  extend      ext(.Instr(Instr[31:7]), .ImmSrc, .ImmExt);
+
+  // ALU logic
+  cmp         cmp(.R1, .R2, .Eq);
+  mux2 #(32)  srcamux(R1, PC, ALUSrc[1], SrcA);
+  mux2 #(32)  srcbmux(R2, ImmExt, ALUSrc[0], SrcB);
+  alu         alu(.SrcA, .SrcB, .ALUControl, .Funct3, .ALUResult, .IEUAdr);
+  mux2 #(32)  ieuresultmux(ALUResult, PCPlus4, ALUResultSrc, IEUResult);
+  mux2 #(32)  resultmux(IEUResult, ReadData, ResultSrc, Result);
+  assign WriteData = R2;
+endmodule
+
+module regfile(
+  input  logic        clk, 
+  input  logic        WE3, 
+  input  logic [ 4:0] A1, A2, A3, 
+  input  logic [31:0] WD3, 
+  output logic [31:0] RD1, RD2);
+
+  logic [31:0] rf[31:1];
 
   // three ported register file
   // read two ports combinationally (A1/RD1, A2/RD2)
@@ -272,10 +292,103 @@ module regfile(input  logic        clk,
   // register 0 hardwired to 0
 
   always_ff @(posedge clk)
-    if (we3) rf[a3] <= wd3;	
+    if (WE3) rf[A3] <= WD3;	
 
-  assign rd1 = (a1 != 0) ? rf[a1] : 0;
-  assign rd2 = (a2 != 0) ? rf[a2] : 0;
+  assign RD1 = (A1 != 0) ? rf[A1] : 0;
+  assign RD2 = (A2 != 0) ? rf[A2] : 0;
+endmodule
+
+module extend(
+  input  logic [31:7] Instr,
+  input  logic [1:0]  ImmSrc,
+  output logic [31:0] ImmExt);
+ 
+  always_comb
+    case(ImmSrc) 
+               // I-type 
+      2'b00:   ImmExt = {{20{Instr[31]}}, Instr[31:20]};  
+               // S-type (stores)
+      2'b01:   ImmExt = {{20{Instr[31]}}, Instr[31:25], Instr[11:7]}; 
+               // B-type (branches)
+      2'b10:   ImmExt = {{20{Instr[31]}}, Instr[7], Instr[30:25], Instr[11:8], 1'b0}; 
+               // J-type (jal)
+      2'b11:   ImmExt = {{12{Instr[31]}}, Instr[19:12], Instr[20], Instr[30:21], 1'b0}; 
+      default: ImmExt = 32'bx; // undefined
+    endcase             
+endmodule
+
+module cmp(
+  input  logic [31:0] R1, R2,
+  output logic        Eq
+);
+ 
+   assign Eq = (R1 == R2);
+endmodule
+  
+
+module alu(
+  input  logic [31:0] SrcA, SrcB,
+  input  logic [1:0]  ALUControl,
+  input  logic [2:0]  Funct3,
+  output logic [31:0] ALUResult, IEUAdr);
+
+  logic [31:0] CondInvb, Sum, SLT;
+  logic        ALUOp, Sub, Overflow, Neg, LT;       
+  logic [2:0]  ALUFunct;
+
+  assign {Sub, ALUOp} = ALUControl;
+
+  // Add or subtract
+  assign CondInvb = Sub ? ~SrcB : SrcB;
+  assign Sum = SrcA + CondInvb + Sub;
+  assign IEUAdr = Sum; // Send this out to IFU and LSU
+
+  // Set less than based on subtraction result
+  assign Overflow = (SrcA[31] ^ SrcB[31]) & (SrcA[31] ^ Sum[31]);
+  assign Neg  = Sum[31];
+  assign LT = Neg ^ Overflow;
+  assign SLT = {31'b0, LT};
+ 
+  assign ALUFunct = Funct3 & {3{ALUOp}}; // Force ALUFunct to 0 to Add when ALUOp = 0
+  always_comb
+    case (ALUFunct)
+      3'b000:  ALUResult = Sum;          // add or sub
+      3'b010:  ALUResult = SLT;          // slt
+      3'b110:  ALUResult = SrcA | SrcB;  // or 
+      3'b111:  ALUResult = SrcA & SrcB;  // and
+      default: ALUResult = 'x;
+    endcase
+endmodule
+
+module lsu(
+  input  logic        clk, MemWrite,
+  input  logic [31:0] IEUAdr, WriteData,
+  output logic [31:0] ReadData);
+
+  logic [31:0] RAM[63:0];
+
+  assign ReadData = RAM[IEUAdr[7:2]]; // word aligned
+
+  always_ff @(posedge clk)
+    if (MemWrite) RAM[IEUAdr[7:2]] <= WriteData;
+endmodule
+
+module flopr #(parameter WIDTH = 8) (
+  input  logic             clk, reset,
+  input  logic [WIDTH-1:0] d, 
+  output logic [WIDTH-1:0] q);
+
+  always_ff @(posedge clk, posedge reset)
+    if (reset) q <= 0;
+    else       q <= d;
+endmodule
+
+module mux2 #(parameter WIDTH = 8) (
+  input  logic [WIDTH-1:0] d0, d1, 
+  input  logic             s, 
+  output logic [WIDTH-1:0] y);
+
+  assign y = s ? d1 : d0; 
 endmodule
 
 module adder(input  [31:0] a, b,
@@ -284,101 +397,3 @@ module adder(input  [31:0] a, b,
   assign y = a + b;
 endmodule
 
-module extend(input  logic [31:7] instr,
-              input  logic [1:0]  immsrc,
-              output logic [31:0] immext);
- 
-  always_comb
-    case(immsrc) 
-               // I-type 
-      2'b00:   immext = {{20{instr[31]}}, instr[31:20]};  
-               // S-type (stores)
-      2'b01:   immext = {{20{instr[31]}}, instr[31:25], instr[11:7]}; 
-               // B-type (branches)
-      2'b10:   immext = {{20{instr[31]}}, instr[7], instr[30:25], instr[11:8], 1'b0}; 
-               // J-type (jal)
-      2'b11:   immext = {{12{instr[31]}}, instr[19:12], instr[20], instr[30:21], 1'b0}; 
-      default: immext = 32'bx; // undefined
-    endcase             
-endmodule
-
-module flopr #(parameter WIDTH = 8)
-              (input  logic             clk, reset,
-               input  logic [WIDTH-1:0] d, 
-               output logic [WIDTH-1:0] q);
-
-  always_ff @(posedge clk, posedge reset)
-    if (reset) q <= 0;
-    else       q <= d;
-endmodule
-
-module mux2 #(parameter WIDTH = 8)
-             (input  logic [WIDTH-1:0] d0, d1, 
-              input  logic             s, 
-              output logic [WIDTH-1:0] y);
-
-  assign y = s ? d1 : d0; 
-endmodule
-
-module mux3 #(parameter WIDTH = 8)
-             (input  logic [WIDTH-1:0] d0, d1, d2,
-              input  logic [1:0]       s, 
-              output logic [WIDTH-1:0] y);
-
-  assign y = s[1] ? d2 : (s[0] ? d1 : d0); 
-endmodule
-
-module imem(input  logic [31:0] a,
-            output logic [31:0] rd);
-
-  logic [31:0] RAM[63:0];
-
-  initial
-      $readmemh("riscvtest.memfile",RAM);
-
-  assign rd = RAM[a[31:2]]; // word aligned
-endmodule
-
-module dmem(input  logic        clk, we,
-            input  logic [31:0] a, wd,
-            output logic [31:0] rd);
-
-  logic [31:0] RAM[63:0];
-
-  assign rd = RAM[a[31:2]]; // word aligned
-
-  always_ff @(posedge clk)
-    if (we) RAM[a[31:2]] <= wd;
-endmodule
-
-module alu(input  logic [31:0] a, b,
-           input  logic [2:0]  alucontrol,
-           output logic [31:0] result,
-           output logic        zero);
-
-  logic [31:0] condinvb, sum;
-  logic        v;              // overflow
-  logic        isAddSub;       // true when is add or subtract operation
-
-  assign condinvb = alucontrol[0] ? ~b : b;
-  assign sum = a + condinvb + alucontrol[0];
-  assign isAddSub = ~alucontrol[2] & ~alucontrol[1] |
-                    ~alucontrol[1] & alucontrol[0];
-
-  always_comb
-    case (alucontrol)
-      3'b000:  result = sum;         // add
-      3'b001:  result = sum;         // subtract
-      3'b010:  result = a & b;       // and
-      3'b011:  result = a | b;       // or
-      3'b100:  result = a ^ b;       // xor
-      3'b101:  result = sum[31] ^ v; // slt
-      3'b110:  result = a << b[4:0]; // sll
-      3'b111:  result = a >> b[4:0]; // srl
-      default: result = 32'bx;
-    endcase
-
-  assign zero = (result == 32'b0);
-  assign v = ~(alucontrol[0] ^ a[31] ^ b[31]) & (a[31] ^ sum[31]) & isAddSub;
-  
-endmodule

fpga/constraints/debug2.xdc

@@ -17,60 +17,60 @@ endgroup
 connect_debug_port u_ila_0/clk [get_nets [list xlnx_ddr4_c0/inst/u_ddr4_infrastructure/addn_ui_clkout1 ]]
 set_property port_width 64 [get_debug_ports u_ila_0/probe0]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
-connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[0]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[1]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[2]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[3]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[4]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[5]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[6]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[7]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[8]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[9]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[10]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[11]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[12]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[13]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[14]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[15]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[16]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[17]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[18]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[19]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[20]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[21]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[22]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[23]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[24]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[25]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[26]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[27]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[28]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[29]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[30]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[31]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[32]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[33]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[34]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[35]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[36]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[37]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[38]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[39]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[40]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[41]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[42]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[43]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[44]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[45]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[46]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[47]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[48]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[49]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[50]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[51]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[52]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[53]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[54]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[55]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[56]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[57]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[58]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[59]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[60]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[61]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[62]} {wallypipelinedsoc/hart/lsu/LSUBusHWDATA[63]} ]]
+connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsoc/core/lsu/LSUBusHWDATA[0]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[1]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[2]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[3]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[4]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[5]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[6]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[7]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[8]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[9]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[10]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[11]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[12]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[13]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[14]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[15]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[16]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[17]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[18]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[19]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[20]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[21]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[22]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[23]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[24]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[25]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[26]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[27]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[28]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[29]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[30]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[31]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[32]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[33]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[34]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[35]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[36]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[37]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[38]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[39]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[40]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[41]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[42]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[43]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[44]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[45]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[46]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[47]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[48]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[49]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[50]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[51]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[52]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[53]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[54]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[55]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[56]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[57]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[58]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[59]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[60]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[61]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[62]} {wallypipelinedsoc/core/lsu/LSUBusHWDATA[63]} ]]
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe1]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
-connect_debug_port u_ila_0/probe1 [get_nets [list {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[0]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[1]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[2]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[3]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[4]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[5]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[6]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[7]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[8]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[9]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[10]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[11]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[12]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[13]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[14]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[15]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[16]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[17]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[18]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[19]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[20]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[21]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[22]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[23]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[24]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[25]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[26]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[27]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[28]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[29]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[30]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[31]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[32]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[33]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[34]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[35]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[36]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[37]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[38]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[39]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[40]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[41]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[42]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[43]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[44]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[45]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[46]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[47]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[48]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[49]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[50]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[51]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[52]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[53]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[54]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[55]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[56]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[57]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[58]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[59]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[60]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[61]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[62]} {wallypipelinedsoc/hart/lsu/LSUBusHRDATA[63]} ]]
+connect_debug_port u_ila_0/probe1 [get_nets [list {wallypipelinedsoc/core/lsu/LSUBusHRDATA[0]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[1]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[2]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[3]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[4]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[5]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[6]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[7]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[8]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[9]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[10]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[11]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[12]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[13]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[14]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[15]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[16]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[17]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[18]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[19]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[20]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[21]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[22]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[23]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[24]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[25]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[26]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[27]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[28]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[29]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[30]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[31]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[32]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[33]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[34]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[35]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[36]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[37]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[38]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[39]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[40]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[41]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[42]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[43]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[44]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[45]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[46]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[47]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[48]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[49]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[50]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[51]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[52]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[53]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[54]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[55]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[56]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[57]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[58]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[59]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[60]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[61]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[62]} {wallypipelinedsoc/core/lsu/LSUBusHRDATA[63]} ]]
 create_debug_port u_ila_0 probe
 set_property port_width 32 [get_debug_ports u_ila_0/probe2]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
-connect_debug_port u_ila_0/probe2 [get_nets [list {wallypipelinedsoc/hart/lsu/LSUBusAdr[0]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[1]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[2]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[3]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[4]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[5]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[6]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[7]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[8]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[9]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[10]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[11]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[12]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[13]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[14]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[15]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[16]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[17]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[18]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[19]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[20]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[21]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[22]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[23]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[24]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[25]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[26]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[27]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[28]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[29]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[30]} {wallypipelinedsoc/hart/lsu/LSUBusAdr[31]} ]]
+connect_debug_port u_ila_0/probe2 [get_nets [list {wallypipelinedsoc/core/lsu/LSUBusAdr[0]} {wallypipelinedsoc/core/lsu/LSUBusAdr[1]} {wallypipelinedsoc/core/lsu/LSUBusAdr[2]} {wallypipelinedsoc/core/lsu/LSUBusAdr[3]} {wallypipelinedsoc/core/lsu/LSUBusAdr[4]} {wallypipelinedsoc/core/lsu/LSUBusAdr[5]} {wallypipelinedsoc/core/lsu/LSUBusAdr[6]} {wallypipelinedsoc/core/lsu/LSUBusAdr[7]} {wallypipelinedsoc/core/lsu/LSUBusAdr[8]} {wallypipelinedsoc/core/lsu/LSUBusAdr[9]} {wallypipelinedsoc/core/lsu/LSUBusAdr[10]} {wallypipelinedsoc/core/lsu/LSUBusAdr[11]} {wallypipelinedsoc/core/lsu/LSUBusAdr[12]} {wallypipelinedsoc/core/lsu/LSUBusAdr[13]} {wallypipelinedsoc/core/lsu/LSUBusAdr[14]} {wallypipelinedsoc/core/lsu/LSUBusAdr[15]} {wallypipelinedsoc/core/lsu/LSUBusAdr[16]} {wallypipelinedsoc/core/lsu/LSUBusAdr[17]} {wallypipelinedsoc/core/lsu/LSUBusAdr[18]} {wallypipelinedsoc/core/lsu/LSUBusAdr[19]} {wallypipelinedsoc/core/lsu/LSUBusAdr[20]} {wallypipelinedsoc/core/lsu/LSUBusAdr[21]} {wallypipelinedsoc/core/lsu/LSUBusAdr[22]} {wallypipelinedsoc/core/lsu/LSUBusAdr[23]} {wallypipelinedsoc/core/lsu/LSUBusAdr[24]} {wallypipelinedsoc/core/lsu/LSUBusAdr[25]} {wallypipelinedsoc/core/lsu/LSUBusAdr[26]} {wallypipelinedsoc/core/lsu/LSUBusAdr[27]} {wallypipelinedsoc/core/lsu/LSUBusAdr[28]} {wallypipelinedsoc/core/lsu/LSUBusAdr[29]} {wallypipelinedsoc/core/lsu/LSUBusAdr[30]} {wallypipelinedsoc/core/lsu/LSUBusAdr[31]} ]]
 create_debug_port u_ila_0 probe
 set_property port_width 6 [get_debug_ports u_ila_0/probe3]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
-connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsoc/hart/priv.priv/trap/MIP_REGW[1]} {wallypipelinedsoc/hart/priv.priv/trap/MIP_REGW[3]} {wallypipelinedsoc/hart/priv.priv/trap/MIP_REGW[5]} {wallypipelinedsoc/hart/priv.priv/trap/MIP_REGW[7]} {wallypipelinedsoc/hart/priv.priv/trap/MIP_REGW[9]} {wallypipelinedsoc/hart/priv.priv/trap/MIP_REGW[11]} ]]
+connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[1]} {wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[3]} {wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[5]} {wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[7]} {wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[9]} {wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[11]} ]]
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe4]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
-connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[0]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[1]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[2]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[3]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[4]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[5]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[6]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[7]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[8]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[9]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[10]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[11]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[12]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[13]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[14]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[15]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[16]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[17]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[18]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[19]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[20]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[21]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[22]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[23]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[24]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[25]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[26]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[27]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[28]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[29]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[30]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[31]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[32]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[33]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[34]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[35]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[36]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[37]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[38]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[39]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[40]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[41]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[42]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[43]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[44]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[45]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[46]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[47]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[48]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[49]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[50]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[51]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[52]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[53]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[54]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[55]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[56]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[57]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[58]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[59]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[60]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[61]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[62]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MCAUSE_REGW[63]} ]]
+connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[63]} ]]
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe5]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
-connect_debug_port u_ila_0/probe5 [get_nets [list {wallypipelinedsoc/hart/ReadDataM[0]} {wallypipelinedsoc/hart/ReadDataM[1]} {wallypipelinedsoc/hart/ReadDataM[2]} {wallypipelinedsoc/hart/ReadDataM[3]} {wallypipelinedsoc/hart/ReadDataM[4]} {wallypipelinedsoc/hart/ReadDataM[5]} {wallypipelinedsoc/hart/ReadDataM[6]} {wallypipelinedsoc/hart/ReadDataM[7]} {wallypipelinedsoc/hart/ReadDataM[8]} {wallypipelinedsoc/hart/ReadDataM[9]} {wallypipelinedsoc/hart/ReadDataM[10]} {wallypipelinedsoc/hart/ReadDataM[11]} {wallypipelinedsoc/hart/ReadDataM[12]} {wallypipelinedsoc/hart/ReadDataM[13]} {wallypipelinedsoc/hart/ReadDataM[14]} {wallypipelinedsoc/hart/ReadDataM[15]} {wallypipelinedsoc/hart/ReadDataM[16]} {wallypipelinedsoc/hart/ReadDataM[17]} {wallypipelinedsoc/hart/ReadDataM[18]} {wallypipelinedsoc/hart/ReadDataM[19]} {wallypipelinedsoc/hart/ReadDataM[20]} {wallypipelinedsoc/hart/ReadDataM[21]} {wallypipelinedsoc/hart/ReadDataM[22]} {wallypipelinedsoc/hart/ReadDataM[23]} {wallypipelinedsoc/hart/ReadDataM[24]} {wallypipelinedsoc/hart/ReadDataM[25]} {wallypipelinedsoc/hart/ReadDataM[26]} {wallypipelinedsoc/hart/ReadDataM[27]} {wallypipelinedsoc/hart/ReadDataM[28]} {wallypipelinedsoc/hart/ReadDataM[29]} {wallypipelinedsoc/hart/ReadDataM[30]} {wallypipelinedsoc/hart/ReadDataM[31]} {wallypipelinedsoc/hart/ReadDataM[32]} {wallypipelinedsoc/hart/ReadDataM[33]} {wallypipelinedsoc/hart/ReadDataM[34]} {wallypipelinedsoc/hart/ReadDataM[35]} {wallypipelinedsoc/hart/ReadDataM[36]} {wallypipelinedsoc/hart/ReadDataM[37]} {wallypipelinedsoc/hart/ReadDataM[38]} {wallypipelinedsoc/hart/ReadDataM[39]} {wallypipelinedsoc/hart/ReadDataM[40]} {wallypipelinedsoc/hart/ReadDataM[41]} {wallypipelinedsoc/hart/ReadDataM[42]} {wallypipelinedsoc/hart/ReadDataM[43]} {wallypipelinedsoc/hart/ReadDataM[44]} {wallypipelinedsoc/hart/ReadDataM[45]} {wallypipelinedsoc/hart/ReadDataM[46]} {wallypipelinedsoc/hart/ReadDataM[47]} {wallypipelinedsoc/hart/ReadDataM[48]} {wallypipelinedsoc/hart/ReadDataM[49]} {wallypipelinedsoc/hart/ReadDataM[50]} {wallypipelinedsoc/hart/ReadDataM[51]} {wallypipelinedsoc/hart/ReadDataM[52]} {wallypipelinedsoc/hart/ReadDataM[53]} {wallypipelinedsoc/hart/ReadDataM[54]} {wallypipelinedsoc/hart/ReadDataM[55]} {wallypipelinedsoc/hart/ReadDataM[56]} {wallypipelinedsoc/hart/ReadDataM[57]} {wallypipelinedsoc/hart/ReadDataM[58]} {wallypipelinedsoc/hart/ReadDataM[59]} {wallypipelinedsoc/hart/ReadDataM[60]} {wallypipelinedsoc/hart/ReadDataM[61]} {wallypipelinedsoc/hart/ReadDataM[62]} {wallypipelinedsoc/hart/ReadDataM[63]} ]]
+connect_debug_port u_ila_0/probe5 [get_nets [list {wallypipelinedsoc/core/ReadDataM[0]} {wallypipelinedsoc/core/ReadDataM[1]} {wallypipelinedsoc/core/ReadDataM[2]} {wallypipelinedsoc/core/ReadDataM[3]} {wallypipelinedsoc/core/ReadDataM[4]} {wallypipelinedsoc/core/ReadDataM[5]} {wallypipelinedsoc/core/ReadDataM[6]} {wallypipelinedsoc/core/ReadDataM[7]} {wallypipelinedsoc/core/ReadDataM[8]} {wallypipelinedsoc/core/ReadDataM[9]} {wallypipelinedsoc/core/ReadDataM[10]} {wallypipelinedsoc/core/ReadDataM[11]} {wallypipelinedsoc/core/ReadDataM[12]} {wallypipelinedsoc/core/ReadDataM[13]} {wallypipelinedsoc/core/ReadDataM[14]} {wallypipelinedsoc/core/ReadDataM[15]} {wallypipelinedsoc/core/ReadDataM[16]} {wallypipelinedsoc/core/ReadDataM[17]} {wallypipelinedsoc/core/ReadDataM[18]} {wallypipelinedsoc/core/ReadDataM[19]} {wallypipelinedsoc/core/ReadDataM[20]} {wallypipelinedsoc/core/ReadDataM[21]} {wallypipelinedsoc/core/ReadDataM[22]} {wallypipelinedsoc/core/ReadDataM[23]} {wallypipelinedsoc/core/ReadDataM[24]} {wallypipelinedsoc/core/ReadDataM[25]} {wallypipelinedsoc/core/ReadDataM[26]} {wallypipelinedsoc/core/ReadDataM[27]} {wallypipelinedsoc/core/ReadDataM[28]} {wallypipelinedsoc/core/ReadDataM[29]} {wallypipelinedsoc/core/ReadDataM[30]} {wallypipelinedsoc/core/ReadDataM[31]} {wallypipelinedsoc/core/ReadDataM[32]} {wallypipelinedsoc/core/ReadDataM[33]} {wallypipelinedsoc/core/ReadDataM[34]} {wallypipelinedsoc/core/ReadDataM[35]} {wallypipelinedsoc/core/ReadDataM[36]} {wallypipelinedsoc/core/ReadDataM[37]} {wallypipelinedsoc/core/ReadDataM[38]} {wallypipelinedsoc/core/ReadDataM[39]} {wallypipelinedsoc/core/ReadDataM[40]} {wallypipelinedsoc/core/ReadDataM[41]} {wallypipelinedsoc/core/ReadDataM[42]} {wallypipelinedsoc/core/ReadDataM[43]} {wallypipelinedsoc/core/ReadDataM[44]} {wallypipelinedsoc/core/ReadDataM[45]} {wallypipelinedsoc/core/ReadDataM[46]} {wallypipelinedsoc/core/ReadDataM[47]} {wallypipelinedsoc/core/ReadDataM[48]} {wallypipelinedsoc/core/ReadDataM[49]} {wallypipelinedsoc/core/ReadDataM[50]} {wallypipelinedsoc/core/ReadDataM[51]} {wallypipelinedsoc/core/ReadDataM[52]} {wallypipelinedsoc/core/ReadDataM[53]} {wallypipelinedsoc/core/ReadDataM[54]} {wallypipelinedsoc/core/ReadDataM[55]} {wallypipelinedsoc/core/ReadDataM[56]} {wallypipelinedsoc/core/ReadDataM[57]} {wallypipelinedsoc/core/ReadDataM[58]} {wallypipelinedsoc/core/ReadDataM[59]} {wallypipelinedsoc/core/ReadDataM[60]} {wallypipelinedsoc/core/ReadDataM[61]} {wallypipelinedsoc/core/ReadDataM[62]} {wallypipelinedsoc/core/ReadDataM[63]} ]]
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe6]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
-connect_debug_port u_ila_0/probe6 [get_nets [list {wallypipelinedsoc/hart/WriteDataM[0]} {wallypipelinedsoc/hart/WriteDataM[1]} {wallypipelinedsoc/hart/WriteDataM[2]} {wallypipelinedsoc/hart/WriteDataM[3]} {wallypipelinedsoc/hart/WriteDataM[4]} {wallypipelinedsoc/hart/WriteDataM[5]} {wallypipelinedsoc/hart/WriteDataM[6]} {wallypipelinedsoc/hart/WriteDataM[7]} {wallypipelinedsoc/hart/WriteDataM[8]} {wallypipelinedsoc/hart/WriteDataM[9]} {wallypipelinedsoc/hart/WriteDataM[10]} {wallypipelinedsoc/hart/WriteDataM[11]} {wallypipelinedsoc/hart/WriteDataM[12]} {wallypipelinedsoc/hart/WriteDataM[13]} {wallypipelinedsoc/hart/WriteDataM[14]} {wallypipelinedsoc/hart/WriteDataM[15]} {wallypipelinedsoc/hart/WriteDataM[16]} {wallypipelinedsoc/hart/WriteDataM[17]} {wallypipelinedsoc/hart/WriteDataM[18]} {wallypipelinedsoc/hart/WriteDataM[19]} {wallypipelinedsoc/hart/WriteDataM[20]} {wallypipelinedsoc/hart/WriteDataM[21]} {wallypipelinedsoc/hart/WriteDataM[22]} {wallypipelinedsoc/hart/WriteDataM[23]} {wallypipelinedsoc/hart/WriteDataM[24]} {wallypipelinedsoc/hart/WriteDataM[25]} {wallypipelinedsoc/hart/WriteDataM[26]} {wallypipelinedsoc/hart/WriteDataM[27]} {wallypipelinedsoc/hart/WriteDataM[28]} {wallypipelinedsoc/hart/WriteDataM[29]} {wallypipelinedsoc/hart/WriteDataM[30]} {wallypipelinedsoc/hart/WriteDataM[31]} {wallypipelinedsoc/hart/WriteDataM[32]} {wallypipelinedsoc/hart/WriteDataM[33]} {wallypipelinedsoc/hart/WriteDataM[34]} {wallypipelinedsoc/hart/WriteDataM[35]} {wallypipelinedsoc/hart/WriteDataM[36]} {wallypipelinedsoc/hart/WriteDataM[37]} {wallypipelinedsoc/hart/WriteDataM[38]} {wallypipelinedsoc/hart/WriteDataM[39]} {wallypipelinedsoc/hart/WriteDataM[40]} {wallypipelinedsoc/hart/WriteDataM[41]} {wallypipelinedsoc/hart/WriteDataM[42]} {wallypipelinedsoc/hart/WriteDataM[43]} {wallypipelinedsoc/hart/WriteDataM[44]} {wallypipelinedsoc/hart/WriteDataM[45]} {wallypipelinedsoc/hart/WriteDataM[46]} {wallypipelinedsoc/hart/WriteDataM[47]} {wallypipelinedsoc/hart/WriteDataM[48]} {wallypipelinedsoc/hart/WriteDataM[49]} {wallypipelinedsoc/hart/WriteDataM[50]} {wallypipelinedsoc/hart/WriteDataM[51]} {wallypipelinedsoc/hart/WriteDataM[52]} {wallypipelinedsoc/hart/WriteDataM[53]} {wallypipelinedsoc/hart/WriteDataM[54]} {wallypipelinedsoc/hart/WriteDataM[55]} {wallypipelinedsoc/hart/WriteDataM[56]} {wallypipelinedsoc/hart/WriteDataM[57]} {wallypipelinedsoc/hart/WriteDataM[58]} {wallypipelinedsoc/hart/WriteDataM[59]} {wallypipelinedsoc/hart/WriteDataM[60]} {wallypipelinedsoc/hart/WriteDataM[61]} {wallypipelinedsoc/hart/WriteDataM[62]} {wallypipelinedsoc/hart/WriteDataM[63]} ]]
+connect_debug_port u_ila_0/probe6 [get_nets [list {wallypipelinedsoc/core/WriteDataM[0]} {wallypipelinedsoc/core/WriteDataM[1]} {wallypipelinedsoc/core/WriteDataM[2]} {wallypipelinedsoc/core/WriteDataM[3]} {wallypipelinedsoc/core/WriteDataM[4]} {wallypipelinedsoc/core/WriteDataM[5]} {wallypipelinedsoc/core/WriteDataM[6]} {wallypipelinedsoc/core/WriteDataM[7]} {wallypipelinedsoc/core/WriteDataM[8]} {wallypipelinedsoc/core/WriteDataM[9]} {wallypipelinedsoc/core/WriteDataM[10]} {wallypipelinedsoc/core/WriteDataM[11]} {wallypipelinedsoc/core/WriteDataM[12]} {wallypipelinedsoc/core/WriteDataM[13]} {wallypipelinedsoc/core/WriteDataM[14]} {wallypipelinedsoc/core/WriteDataM[15]} {wallypipelinedsoc/core/WriteDataM[16]} {wallypipelinedsoc/core/WriteDataM[17]} {wallypipelinedsoc/core/WriteDataM[18]} {wallypipelinedsoc/core/WriteDataM[19]} {wallypipelinedsoc/core/WriteDataM[20]} {wallypipelinedsoc/core/WriteDataM[21]} {wallypipelinedsoc/core/WriteDataM[22]} {wallypipelinedsoc/core/WriteDataM[23]} {wallypipelinedsoc/core/WriteDataM[24]} {wallypipelinedsoc/core/WriteDataM[25]} {wallypipelinedsoc/core/WriteDataM[26]} {wallypipelinedsoc/core/WriteDataM[27]} {wallypipelinedsoc/core/WriteDataM[28]} {wallypipelinedsoc/core/WriteDataM[29]} {wallypipelinedsoc/core/WriteDataM[30]} {wallypipelinedsoc/core/WriteDataM[31]} {wallypipelinedsoc/core/WriteDataM[32]} {wallypipelinedsoc/core/WriteDataM[33]} {wallypipelinedsoc/core/WriteDataM[34]} {wallypipelinedsoc/core/WriteDataM[35]} {wallypipelinedsoc/core/WriteDataM[36]} {wallypipelinedsoc/core/WriteDataM[37]} {wallypipelinedsoc/core/WriteDataM[38]} {wallypipelinedsoc/core/WriteDataM[39]} {wallypipelinedsoc/core/WriteDataM[40]} {wallypipelinedsoc/core/WriteDataM[41]} {wallypipelinedsoc/core/WriteDataM[42]} {wallypipelinedsoc/core/WriteDataM[43]} {wallypipelinedsoc/core/WriteDataM[44]} {wallypipelinedsoc/core/WriteDataM[45]} {wallypipelinedsoc/core/WriteDataM[46]} {wallypipelinedsoc/core/WriteDataM[47]} {wallypipelinedsoc/core/WriteDataM[48]} {wallypipelinedsoc/core/WriteDataM[49]} {wallypipelinedsoc/core/WriteDataM[50]} {wallypipelinedsoc/core/WriteDataM[51]} {wallypipelinedsoc/core/WriteDataM[52]} {wallypipelinedsoc/core/WriteDataM[53]} {wallypipelinedsoc/core/WriteDataM[54]} {wallypipelinedsoc/core/WriteDataM[55]} {wallypipelinedsoc/core/WriteDataM[56]} {wallypipelinedsoc/core/WriteDataM[57]} {wallypipelinedsoc/core/WriteDataM[58]} {wallypipelinedsoc/core/WriteDataM[59]} {wallypipelinedsoc/core/WriteDataM[60]} {wallypipelinedsoc/core/WriteDataM[61]} {wallypipelinedsoc/core/WriteDataM[62]} {wallypipelinedsoc/core/WriteDataM[63]} ]]
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe7]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
-connect_debug_port u_ila_0/probe7 [get_nets [list {wallypipelinedsoc/hart/PCM[0]} {wallypipelinedsoc/hart/PCM[1]} {wallypipelinedsoc/hart/PCM[2]} {wallypipelinedsoc/hart/PCM[3]} {wallypipelinedsoc/hart/PCM[4]} {wallypipelinedsoc/hart/PCM[5]} {wallypipelinedsoc/hart/PCM[6]} {wallypipelinedsoc/hart/PCM[7]} {wallypipelinedsoc/hart/PCM[8]} {wallypipelinedsoc/hart/PCM[9]} {wallypipelinedsoc/hart/PCM[10]} {wallypipelinedsoc/hart/PCM[11]} {wallypipelinedsoc/hart/PCM[12]} {wallypipelinedsoc/hart/PCM[13]} {wallypipelinedsoc/hart/PCM[14]} {wallypipelinedsoc/hart/PCM[15]} {wallypipelinedsoc/hart/PCM[16]} {wallypipelinedsoc/hart/PCM[17]} {wallypipelinedsoc/hart/PCM[18]} {wallypipelinedsoc/hart/PCM[19]} {wallypipelinedsoc/hart/PCM[20]} {wallypipelinedsoc/hart/PCM[21]} {wallypipelinedsoc/hart/PCM[22]} {wallypipelinedsoc/hart/PCM[23]} {wallypipelinedsoc/hart/PCM[24]} {wallypipelinedsoc/hart/PCM[25]} {wallypipelinedsoc/hart/PCM[26]} {wallypipelinedsoc/hart/PCM[27]} {wallypipelinedsoc/hart/PCM[28]} {wallypipelinedsoc/hart/PCM[29]} {wallypipelinedsoc/hart/PCM[30]} {wallypipelinedsoc/hart/PCM[31]} {wallypipelinedsoc/hart/PCM[32]} {wallypipelinedsoc/hart/PCM[33]} {wallypipelinedsoc/hart/PCM[34]} {wallypipelinedsoc/hart/PCM[35]} {wallypipelinedsoc/hart/PCM[36]} {wallypipelinedsoc/hart/PCM[37]} {wallypipelinedsoc/hart/PCM[38]} {wallypipelinedsoc/hart/PCM[39]} {wallypipelinedsoc/hart/PCM[40]} {wallypipelinedsoc/hart/PCM[41]} {wallypipelinedsoc/hart/PCM[42]} {wallypipelinedsoc/hart/PCM[43]} {wallypipelinedsoc/hart/PCM[44]} {wallypipelinedsoc/hart/PCM[45]} {wallypipelinedsoc/hart/PCM[46]} {wallypipelinedsoc/hart/PCM[47]} {wallypipelinedsoc/hart/PCM[48]} {wallypipelinedsoc/hart/PCM[49]} {wallypipelinedsoc/hart/PCM[50]} {wallypipelinedsoc/hart/PCM[51]} {wallypipelinedsoc/hart/PCM[52]} {wallypipelinedsoc/hart/PCM[53]} {wallypipelinedsoc/hart/PCM[54]} {wallypipelinedsoc/hart/PCM[55]} {wallypipelinedsoc/hart/PCM[56]} {wallypipelinedsoc/hart/PCM[57]} {wallypipelinedsoc/hart/PCM[58]} {wallypipelinedsoc/hart/PCM[59]} {wallypipelinedsoc/hart/PCM[60]} {wallypipelinedsoc/hart/PCM[61]} {wallypipelinedsoc/hart/PCM[62]} {wallypipelinedsoc/hart/PCM[63]} ]]
+connect_debug_port u_ila_0/probe7 [get_nets [list {wallypipelinedsoc/core/PCM[0]} {wallypipelinedsoc/core/PCM[1]} {wallypipelinedsoc/core/PCM[2]} {wallypipelinedsoc/core/PCM[3]} {wallypipelinedsoc/core/PCM[4]} {wallypipelinedsoc/core/PCM[5]} {wallypipelinedsoc/core/PCM[6]} {wallypipelinedsoc/core/PCM[7]} {wallypipelinedsoc/core/PCM[8]} {wallypipelinedsoc/core/PCM[9]} {wallypipelinedsoc/core/PCM[10]} {wallypipelinedsoc/core/PCM[11]} {wallypipelinedsoc/core/PCM[12]} {wallypipelinedsoc/core/PCM[13]} {wallypipelinedsoc/core/PCM[14]} {wallypipelinedsoc/core/PCM[15]} {wallypipelinedsoc/core/PCM[16]} {wallypipelinedsoc/core/PCM[17]} {wallypipelinedsoc/core/PCM[18]} {wallypipelinedsoc/core/PCM[19]} {wallypipelinedsoc/core/PCM[20]} {wallypipelinedsoc/core/PCM[21]} {wallypipelinedsoc/core/PCM[22]} {wallypipelinedsoc/core/PCM[23]} {wallypipelinedsoc/core/PCM[24]} {wallypipelinedsoc/core/PCM[25]} {wallypipelinedsoc/core/PCM[26]} {wallypipelinedsoc/core/PCM[27]} {wallypipelinedsoc/core/PCM[28]} {wallypipelinedsoc/core/PCM[29]} {wallypipelinedsoc/core/PCM[30]} {wallypipelinedsoc/core/PCM[31]} {wallypipelinedsoc/core/PCM[32]} {wallypipelinedsoc/core/PCM[33]} {wallypipelinedsoc/core/PCM[34]} {wallypipelinedsoc/core/PCM[35]} {wallypipelinedsoc/core/PCM[36]} {wallypipelinedsoc/core/PCM[37]} {wallypipelinedsoc/core/PCM[38]} {wallypipelinedsoc/core/PCM[39]} {wallypipelinedsoc/core/PCM[40]} {wallypipelinedsoc/core/PCM[41]} {wallypipelinedsoc/core/PCM[42]} {wallypipelinedsoc/core/PCM[43]} {wallypipelinedsoc/core/PCM[44]} {wallypipelinedsoc/core/PCM[45]} {wallypipelinedsoc/core/PCM[46]} {wallypipelinedsoc/core/PCM[47]} {wallypipelinedsoc/core/PCM[48]} {wallypipelinedsoc/core/PCM[49]} {wallypipelinedsoc/core/PCM[50]} {wallypipelinedsoc/core/PCM[51]} {wallypipelinedsoc/core/PCM[52]} {wallypipelinedsoc/core/PCM[53]} {wallypipelinedsoc/core/PCM[54]} {wallypipelinedsoc/core/PCM[55]} {wallypipelinedsoc/core/PCM[56]} {wallypipelinedsoc/core/PCM[57]} {wallypipelinedsoc/core/PCM[58]} {wallypipelinedsoc/core/PCM[59]} {wallypipelinedsoc/core/PCM[60]} {wallypipelinedsoc/core/PCM[61]} {wallypipelinedsoc/core/PCM[62]} {wallypipelinedsoc/core/PCM[63]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe8]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
-connect_debug_port u_ila_0/probe8 [get_nets [list {wallypipelinedsoc/hart/IEUAdrM[0]} {wallypipelinedsoc/hart/IEUAdrM[1]} {wallypipelinedsoc/hart/IEUAdrM[2]} {wallypipelinedsoc/hart/IEUAdrM[3]} {wallypipelinedsoc/hart/IEUAdrM[4]} {wallypipelinedsoc/hart/IEUAdrM[5]} {wallypipelinedsoc/hart/IEUAdrM[6]} {wallypipelinedsoc/hart/IEUAdrM[7]} {wallypipelinedsoc/hart/IEUAdrM[8]} {wallypipelinedsoc/hart/IEUAdrM[9]} {wallypipelinedsoc/hart/IEUAdrM[10]} {wallypipelinedsoc/hart/IEUAdrM[11]} {wallypipelinedsoc/hart/IEUAdrM[12]} {wallypipelinedsoc/hart/IEUAdrM[13]} {wallypipelinedsoc/hart/IEUAdrM[14]} {wallypipelinedsoc/hart/IEUAdrM[15]} {wallypipelinedsoc/hart/IEUAdrM[16]} {wallypipelinedsoc/hart/IEUAdrM[17]} {wallypipelinedsoc/hart/IEUAdrM[18]} {wallypipelinedsoc/hart/IEUAdrM[19]} {wallypipelinedsoc/hart/IEUAdrM[20]} {wallypipelinedsoc/hart/IEUAdrM[21]} {wallypipelinedsoc/hart/IEUAdrM[22]} {wallypipelinedsoc/hart/IEUAdrM[23]} {wallypipelinedsoc/hart/IEUAdrM[24]} {wallypipelinedsoc/hart/IEUAdrM[25]} {wallypipelinedsoc/hart/IEUAdrM[26]} {wallypipelinedsoc/hart/IEUAdrM[27]} {wallypipelinedsoc/hart/IEUAdrM[28]} {wallypipelinedsoc/hart/IEUAdrM[29]} {wallypipelinedsoc/hart/IEUAdrM[30]} {wallypipelinedsoc/hart/IEUAdrM[31]} {wallypipelinedsoc/hart/IEUAdrM[32]} {wallypipelinedsoc/hart/IEUAdrM[33]} {wallypipelinedsoc/hart/IEUAdrM[34]} {wallypipelinedsoc/hart/IEUAdrM[35]} {wallypipelinedsoc/hart/IEUAdrM[36]} {wallypipelinedsoc/hart/IEUAdrM[37]} {wallypipelinedsoc/hart/IEUAdrM[38]} {wallypipelinedsoc/hart/IEUAdrM[39]} {wallypipelinedsoc/hart/IEUAdrM[40]} {wallypipelinedsoc/hart/IEUAdrM[41]} {wallypipelinedsoc/hart/IEUAdrM[42]} {wallypipelinedsoc/hart/IEUAdrM[43]} {wallypipelinedsoc/hart/IEUAdrM[44]} {wallypipelinedsoc/hart/IEUAdrM[45]} {wallypipelinedsoc/hart/IEUAdrM[46]} {wallypipelinedsoc/hart/IEUAdrM[47]} {wallypipelinedsoc/hart/IEUAdrM[48]} {wallypipelinedsoc/hart/IEUAdrM[49]} {wallypipelinedsoc/hart/IEUAdrM[50]} {wallypipelinedsoc/hart/IEUAdrM[51]} {wallypipelinedsoc/hart/IEUAdrM[52]} {wallypipelinedsoc/hart/IEUAdrM[53]} {wallypipelinedsoc/hart/IEUAdrM[54]} {wallypipelinedsoc/hart/IEUAdrM[55]} {wallypipelinedsoc/hart/IEUAdrM[56]} {wallypipelinedsoc/hart/IEUAdrM[57]} {wallypipelinedsoc/hart/IEUAdrM[58]} {wallypipelinedsoc/hart/IEUAdrM[59]} {wallypipelinedsoc/hart/IEUAdrM[60]} {wallypipelinedsoc/hart/IEUAdrM[61]} {wallypipelinedsoc/hart/IEUAdrM[62]} {wallypipelinedsoc/hart/IEUAdrM[63]} ]]
+connect_debug_port u_ila_0/probe8 [get_nets [list {wallypipelinedsoc/core/IEUAdrM[0]} {wallypipelinedsoc/core/IEUAdrM[1]} {wallypipelinedsoc/core/IEUAdrM[2]} {wallypipelinedsoc/core/IEUAdrM[3]} {wallypipelinedsoc/core/IEUAdrM[4]} {wallypipelinedsoc/core/IEUAdrM[5]} {wallypipelinedsoc/core/IEUAdrM[6]} {wallypipelinedsoc/core/IEUAdrM[7]} {wallypipelinedsoc/core/IEUAdrM[8]} {wallypipelinedsoc/core/IEUAdrM[9]} {wallypipelinedsoc/core/IEUAdrM[10]} {wallypipelinedsoc/core/IEUAdrM[11]} {wallypipelinedsoc/core/IEUAdrM[12]} {wallypipelinedsoc/core/IEUAdrM[13]} {wallypipelinedsoc/core/IEUAdrM[14]} {wallypipelinedsoc/core/IEUAdrM[15]} {wallypipelinedsoc/core/IEUAdrM[16]} {wallypipelinedsoc/core/IEUAdrM[17]} {wallypipelinedsoc/core/IEUAdrM[18]} {wallypipelinedsoc/core/IEUAdrM[19]} {wallypipelinedsoc/core/IEUAdrM[20]} {wallypipelinedsoc/core/IEUAdrM[21]} {wallypipelinedsoc/core/IEUAdrM[22]} {wallypipelinedsoc/core/IEUAdrM[23]} {wallypipelinedsoc/core/IEUAdrM[24]} {wallypipelinedsoc/core/IEUAdrM[25]} {wallypipelinedsoc/core/IEUAdrM[26]} {wallypipelinedsoc/core/IEUAdrM[27]} {wallypipelinedsoc/core/IEUAdrM[28]} {wallypipelinedsoc/core/IEUAdrM[29]} {wallypipelinedsoc/core/IEUAdrM[30]} {wallypipelinedsoc/core/IEUAdrM[31]} {wallypipelinedsoc/core/IEUAdrM[32]} {wallypipelinedsoc/core/IEUAdrM[33]} {wallypipelinedsoc/core/IEUAdrM[34]} {wallypipelinedsoc/core/IEUAdrM[35]} {wallypipelinedsoc/core/IEUAdrM[36]} {wallypipelinedsoc/core/IEUAdrM[37]} {wallypipelinedsoc/core/IEUAdrM[38]} {wallypipelinedsoc/core/IEUAdrM[39]} {wallypipelinedsoc/core/IEUAdrM[40]} {wallypipelinedsoc/core/IEUAdrM[41]} {wallypipelinedsoc/core/IEUAdrM[42]} {wallypipelinedsoc/core/IEUAdrM[43]} {wallypipelinedsoc/core/IEUAdrM[44]} {wallypipelinedsoc/core/IEUAdrM[45]} {wallypipelinedsoc/core/IEUAdrM[46]} {wallypipelinedsoc/core/IEUAdrM[47]} {wallypipelinedsoc/core/IEUAdrM[48]} {wallypipelinedsoc/core/IEUAdrM[49]} {wallypipelinedsoc/core/IEUAdrM[50]} {wallypipelinedsoc/core/IEUAdrM[51]} {wallypipelinedsoc/core/IEUAdrM[52]} {wallypipelinedsoc/core/IEUAdrM[53]} {wallypipelinedsoc/core/IEUAdrM[54]} {wallypipelinedsoc/core/IEUAdrM[55]} {wallypipelinedsoc/core/IEUAdrM[56]} {wallypipelinedsoc/core/IEUAdrM[57]} {wallypipelinedsoc/core/IEUAdrM[58]} {wallypipelinedsoc/core/IEUAdrM[59]} {wallypipelinedsoc/core/IEUAdrM[60]} {wallypipelinedsoc/core/IEUAdrM[61]} {wallypipelinedsoc/core/IEUAdrM[62]} {wallypipelinedsoc/core/IEUAdrM[63]} ]]
 create_debug_port u_ila_0 probe
 set_property port_width 32 [get_debug_ports u_ila_0/probe9]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
-connect_debug_port u_ila_0/probe9 [get_nets [list {wallypipelinedsoc/hart/InstrM[0]} {wallypipelinedsoc/hart/InstrM[1]} {wallypipelinedsoc/hart/InstrM[2]} {wallypipelinedsoc/hart/InstrM[3]} {wallypipelinedsoc/hart/InstrM[4]} {wallypipelinedsoc/hart/InstrM[5]} {wallypipelinedsoc/hart/InstrM[6]} {wallypipelinedsoc/hart/InstrM[7]} {wallypipelinedsoc/hart/InstrM[8]} {wallypipelinedsoc/hart/InstrM[9]} {wallypipelinedsoc/hart/InstrM[10]} {wallypipelinedsoc/hart/InstrM[11]} {wallypipelinedsoc/hart/InstrM[12]} {wallypipelinedsoc/hart/InstrM[13]} {wallypipelinedsoc/hart/InstrM[14]} {wallypipelinedsoc/hart/InstrM[15]} {wallypipelinedsoc/hart/InstrM[16]} {wallypipelinedsoc/hart/InstrM[17]} {wallypipelinedsoc/hart/InstrM[18]} {wallypipelinedsoc/hart/InstrM[19]} {wallypipelinedsoc/hart/InstrM[20]} {wallypipelinedsoc/hart/InstrM[21]} {wallypipelinedsoc/hart/InstrM[22]} {wallypipelinedsoc/hart/InstrM[23]} {wallypipelinedsoc/hart/InstrM[24]} {wallypipelinedsoc/hart/InstrM[25]} {wallypipelinedsoc/hart/InstrM[26]} {wallypipelinedsoc/hart/InstrM[27]} {wallypipelinedsoc/hart/InstrM[28]} {wallypipelinedsoc/hart/InstrM[29]} {wallypipelinedsoc/hart/InstrM[30]} {wallypipelinedsoc/hart/InstrM[31]} ]]
+connect_debug_port u_ila_0/probe9 [get_nets [list {wallypipelinedsoc/core/InstrM[0]} {wallypipelinedsoc/core/InstrM[1]} {wallypipelinedsoc/core/InstrM[2]} {wallypipelinedsoc/core/InstrM[3]} {wallypipelinedsoc/core/InstrM[4]} {wallypipelinedsoc/core/InstrM[5]} {wallypipelinedsoc/core/InstrM[6]} {wallypipelinedsoc/core/InstrM[7]} {wallypipelinedsoc/core/InstrM[8]} {wallypipelinedsoc/core/InstrM[9]} {wallypipelinedsoc/core/InstrM[10]} {wallypipelinedsoc/core/InstrM[11]} {wallypipelinedsoc/core/InstrM[12]} {wallypipelinedsoc/core/InstrM[13]} {wallypipelinedsoc/core/InstrM[14]} {wallypipelinedsoc/core/InstrM[15]} {wallypipelinedsoc/core/InstrM[16]} {wallypipelinedsoc/core/InstrM[17]} {wallypipelinedsoc/core/InstrM[18]} {wallypipelinedsoc/core/InstrM[19]} {wallypipelinedsoc/core/InstrM[20]} {wallypipelinedsoc/core/InstrM[21]} {wallypipelinedsoc/core/InstrM[22]} {wallypipelinedsoc/core/InstrM[23]} {wallypipelinedsoc/core/InstrM[24]} {wallypipelinedsoc/core/InstrM[25]} {wallypipelinedsoc/core/InstrM[26]} {wallypipelinedsoc/core/InstrM[27]} {wallypipelinedsoc/core/InstrM[28]} {wallypipelinedsoc/core/InstrM[29]} {wallypipelinedsoc/core/InstrM[30]} {wallypipelinedsoc/core/InstrM[31]} ]]
 create_debug_port u_ila_0 probe
 set_property port_width 2 [get_debug_ports u_ila_0/probe10]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
-connect_debug_port u_ila_0/probe10 [get_nets [list {wallypipelinedsoc/hart/MemRWM[0]} {wallypipelinedsoc/hart/MemRWM[1]} ]]
+connect_debug_port u_ila_0/probe10 [get_nets [list {wallypipelinedsoc/core/MemRWM[0]} {wallypipelinedsoc/core/MemRWM[1]} ]]
 create_debug_port u_ila_0 probe
 set_property port_width 6 [get_debug_ports u_ila_0/probe11]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
-connect_debug_port u_ila_0/probe11 [get_nets [list {wallypipelinedsoc/hart/priv.priv/csr/csrm/MIE_REGW[1]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MIE_REGW[3]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MIE_REGW[5]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MIE_REGW[7]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MIE_REGW[9]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MIE_REGW[11]} ]]
+connect_debug_port u_ila_0/probe11 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[11]} ]]
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe12]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
-connect_debug_port u_ila_0/probe12 [get_nets [list {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[0]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[1]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[2]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[3]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[4]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[5]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[6]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[7]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[8]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[9]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[10]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[11]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[12]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[13]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[14]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[15]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[16]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[17]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[18]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[19]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[20]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[21]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[22]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[23]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[24]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[25]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[26]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[27]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[28]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[29]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[30]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[31]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[32]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[33]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[34]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[35]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[36]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[37]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[38]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[39]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[40]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[41]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[42]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[43]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[44]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[45]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[46]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[47]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[48]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[49]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[50]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[51]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[52]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[53]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[54]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[55]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[56]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[57]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[58]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[59]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[60]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[61]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[62]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MEPC_REGW[63]} ]]
+connect_debug_port u_ila_0/probe12 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[63]} ]]
 create_debug_port u_ila_0 probe
 set_property port_width 6 [get_debug_ports u_ila_0/probe13]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
-connect_debug_port u_ila_0/probe13 [get_nets [list {wallypipelinedsoc/hart/priv.priv/csr/csrm/MIP_REGW[1]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MIP_REGW[3]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MIP_REGW[5]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MIP_REGW[7]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MIP_REGW[9]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MIP_REGW[11]} ]]
+connect_debug_port u_ila_0/probe13 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[11]} ]]
 create_debug_port u_ila_0 probe
 set_property port_width 5 [get_debug_ports u_ila_0/probe14]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
@@ -86,31 +86,31 @@ connect_debug_port u_ila_0/probe16 [get_nets [list {wallypipelinedsoc/uncore/sdc
 create_debug_port u_ila_0 probe
 set_property port_width 4 [get_debug_ports u_ila_0/probe17]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
-connect_debug_port u_ila_0/probe17 [get_nets [list {wallypipelinedsoc/hart/lsu/bus.dcache.dcache/cachefsm/CurrState[0]} {wallypipelinedsoc/hart/lsu/bus.dcache.dcache/cachefsm/CurrState[1]} {wallypipelinedsoc/hart/lsu/bus.dcache.dcache/cachefsm/CurrState[2]} {wallypipelinedsoc/hart/lsu/bus.dcache.dcache/cachefsm/CurrState[3]} ]]
+connect_debug_port u_ila_0/probe17 [get_nets [list {wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[0]} {wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[1]} {wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[2]} {wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[3]} ]]
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe18]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
-connect_debug_port u_ila_0/probe18 [get_nets [list {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[0]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[1]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[2]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[3]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[4]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[5]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[6]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[7]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[8]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[9]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[10]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[11]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[12]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[13]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[14]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[15]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[16]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[17]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[18]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[19]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[20]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[21]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[22]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[23]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[24]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[25]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[26]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[27]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[28]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[29]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[30]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[31]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[32]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[33]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[34]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[35]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[36]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[37]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[38]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[39]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[40]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[41]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[42]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[43]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[44]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[45]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[46]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[47]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[48]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[49]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[50]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[51]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[52]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[53]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[54]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[55]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[56]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[57]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[58]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[59]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[60]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[61]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[62]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/SEPC_REGW[63]} ]]
+connect_debug_port u_ila_0/probe18 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[63]} ]]
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe19]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
-connect_debug_port u_ila_0/probe19 [get_nets [list {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[0]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[1]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[2]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[3]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[4]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[5]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[6]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[7]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[8]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[9]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[10]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[11]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[12]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[13]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[14]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[15]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[16]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[17]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[18]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[19]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[20]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[21]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[22]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[23]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[24]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[25]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[26]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[27]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[28]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[29]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[30]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[31]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[32]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[33]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[34]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[35]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[36]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[37]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[38]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[39]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[40]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[41]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[42]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[43]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[44]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[45]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[46]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[47]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[48]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[49]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[50]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[51]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[52]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[53]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[54]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[55]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[56]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[57]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[58]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[59]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[60]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[61]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[62]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SCAUSE_REGW[63]} ]]
+connect_debug_port u_ila_0/probe19 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[63]} ]]
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe20]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
-connect_debug_port u_ila_0/probe20 [get_nets [list {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[0]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[1]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[2]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[3]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[4]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[5]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[6]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[7]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[8]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[9]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[10]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[11]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[12]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[13]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[14]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[15]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[16]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[17]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[18]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[19]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[20]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[21]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[22]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[23]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[24]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[25]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[26]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[27]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[28]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[29]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[30]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[31]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[32]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[33]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[34]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[35]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[36]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[37]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[38]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[39]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[40]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[41]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[42]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[43]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[44]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[45]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[46]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[47]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[48]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[49]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[50]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[51]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[52]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[53]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[54]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[55]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[56]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[57]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[58]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[59]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[60]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[61]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[62]} {wallypipelinedsoc/hart/priv.priv/trap/SEPC_REGW[63]} ]]
+connect_debug_port u_ila_0/probe20 [get_nets [list {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[0]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[1]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[2]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[3]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[4]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[5]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[6]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[7]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[8]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[9]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[10]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[11]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[12]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[13]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[14]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[15]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[16]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[17]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[18]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[19]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[20]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[21]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[22]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[23]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[24]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[25]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[26]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[27]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[28]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[29]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[30]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[31]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[32]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[33]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[34]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[35]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[36]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[37]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[38]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[39]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[40]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[41]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[42]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[43]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[44]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[45]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[46]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[47]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[48]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[49]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[50]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[51]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[52]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[53]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[54]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[55]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[56]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[57]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[58]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[59]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[60]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[61]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[62]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[63]} ]]
 create_debug_port u_ila_0 probe
 set_property port_width 3 [get_debug_ports u_ila_0/probe21]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
-connect_debug_port u_ila_0/probe21 [get_nets [list {wallypipelinedsoc/hart/priv.priv/trap/SIP_REGW[1]} {wallypipelinedsoc/hart/priv.priv/trap/SIP_REGW[5]} {wallypipelinedsoc/hart/priv.priv/trap/SIP_REGW[9]} ]]
+connect_debug_port u_ila_0/probe21 [get_nets [list {wallypipelinedsoc/core/priv.priv/trap/SIP_REGW[1]} {wallypipelinedsoc/core/priv.priv/trap/SIP_REGW[5]} {wallypipelinedsoc/core/priv.priv/trap/SIP_REGW[9]} ]]
 create_debug_port u_ila_0 probe
 set_property port_width 3 [get_debug_ports u_ila_0/probe22]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
-connect_debug_port u_ila_0/probe22 [get_nets [list {wallypipelinedsoc/hart/priv.priv/trap/SIE_REGW[1]} {wallypipelinedsoc/hart/priv.priv/trap/SIE_REGW[5]} {wallypipelinedsoc/hart/priv.priv/trap/SIE_REGW[9]} ]]
+connect_debug_port u_ila_0/probe22 [get_nets [list {wallypipelinedsoc/core/priv.priv/trap/SIE_REGW[1]} {wallypipelinedsoc/core/priv.priv/trap/SIE_REGW[5]} {wallypipelinedsoc/core/priv.priv/trap/SIE_REGW[9]} ]]
 create_debug_port u_ila_0 probe
 set_property port_width 63 [get_debug_ports u_ila_0/probe23]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
-connect_debug_port u_ila_0/probe23 [get_nets [list {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[0]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[2]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[3]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[4]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[5]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[6]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[7]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[8]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[9]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[10]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[11]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[12]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[13]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[14]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[15]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[16]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[17]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[18]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[19]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[20]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[21]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[22]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[23]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[24]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[25]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[26]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[27]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[28]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[29]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[30]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[31]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[32]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[33]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[34]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[35]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[36]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[37]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[38]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[39]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[40]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[41]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[42]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[43]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[44]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[45]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[46]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[47]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[48]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[49]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[50]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[51]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[52]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[53]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[54]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[55]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[56]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[57]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[58]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[59]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[60]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[61]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[62]} {wallypipelinedsoc/hart/priv.priv/trap/STVEC_REGW[63]} ]]
+connect_debug_port u_ila_0/probe23 [get_nets [list {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[0]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[2]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[3]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[4]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[5]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[6]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[7]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[8]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[9]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[10]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[11]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[12]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[13]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[14]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[15]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[16]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[17]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[18]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[19]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[20]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[21]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[22]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[23]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[24]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[25]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[26]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[27]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[28]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[29]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[30]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[31]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[32]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[33]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[34]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[35]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[36]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[37]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[38]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[39]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[40]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[41]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[42]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[43]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[44]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[45]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[46]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[47]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[48]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[49]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[50]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[51]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[52]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[53]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[54]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[55]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[56]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[57]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[58]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[59]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[60]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[61]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[62]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[63]} ]]
 create_debug_port u_ila_0 probe
 set_property port_width 4 [get_debug_ports u_ila_0/probe24]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
@@ -122,15 +122,15 @@ connect_debug_port u_ila_0/probe25 [get_nets [list {wallypipelinedsoc/uncore/sdc
 create_debug_port u_ila_0 probe
 set_property port_width 12 [get_debug_ports u_ila_0/probe26]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26]
-connect_debug_port u_ila_0/probe26 [get_nets [list {wallypipelinedsoc/hart/priv.priv/trap/PendingIntsM[0]} {wallypipelinedsoc/hart/priv.priv/trap/PendingIntsM[1]} {wallypipelinedsoc/hart/priv.priv/trap/PendingIntsM[2]} {wallypipelinedsoc/hart/priv.priv/trap/PendingIntsM[3]} {wallypipelinedsoc/hart/priv.priv/trap/PendingIntsM[4]} {wallypipelinedsoc/hart/priv.priv/trap/PendingIntsM[5]} {wallypipelinedsoc/hart/priv.priv/trap/PendingIntsM[6]} {wallypipelinedsoc/hart/priv.priv/trap/PendingIntsM[7]} {wallypipelinedsoc/hart/priv.priv/trap/PendingIntsM[8]} {wallypipelinedsoc/hart/priv.priv/trap/PendingIntsM[9]} {wallypipelinedsoc/hart/priv.priv/trap/PendingIntsM[10]} {wallypipelinedsoc/hart/priv.priv/trap/PendingIntsM[11]} ]]
+connect_debug_port u_ila_0/probe26 [get_nets [list {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[0]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[1]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[2]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[3]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[4]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[5]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[6]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[7]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[8]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[9]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[10]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[11]} ]]
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe27]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27]
-connect_debug_port u_ila_0/probe27 [get_nets [list {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[0]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[1]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[2]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[3]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[4]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[5]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[6]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[7]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[8]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[9]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[10]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[11]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[12]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[13]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[14]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[15]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[16]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[17]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[18]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[19]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[20]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[21]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[22]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[23]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[24]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[25]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[26]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[27]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[28]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[29]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[30]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[31]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[32]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[33]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[34]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[35]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[36]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[37]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[38]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[39]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[40]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[41]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[42]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[43]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[44]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[45]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[46]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[47]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[48]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[49]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[50]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[51]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[52]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[53]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[54]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[55]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[56]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[57]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[58]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[59]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[60]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[61]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[62]} {wallypipelinedsoc/hart/priv.priv/trap/MEPC_REGW[63]} ]]
+connect_debug_port u_ila_0/probe27 [get_nets [list {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[0]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[1]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[2]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[3]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[4]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[5]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[6]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[7]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[8]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[9]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[10]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[11]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[12]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[13]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[14]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[15]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[16]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[17]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[18]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[19]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[20]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[21]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[22]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[23]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[24]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[25]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[26]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[27]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[28]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[29]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[30]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[31]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[32]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[33]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[34]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[35]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[36]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[37]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[38]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[39]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[40]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[41]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[42]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[43]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[44]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[45]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[46]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[47]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[48]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[49]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[50]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[51]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[52]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[53]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[54]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[55]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[56]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[57]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[58]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[59]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[60]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[61]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[62]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[63]} ]]
 create_debug_port u_ila_0 probe
 set_property port_width 6 [get_debug_ports u_ila_0/probe28]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28]
-connect_debug_port u_ila_0/probe28 [get_nets [list {wallypipelinedsoc/hart/priv.priv/trap/MIE_REGW[1]} {wallypipelinedsoc/hart/priv.priv/trap/MIE_REGW[3]} {wallypipelinedsoc/hart/priv.priv/trap/MIE_REGW[5]} {wallypipelinedsoc/hart/priv.priv/trap/MIE_REGW[7]} {wallypipelinedsoc/hart/priv.priv/trap/MIE_REGW[9]} {wallypipelinedsoc/hart/priv.priv/trap/MIE_REGW[11]} ]]
+connect_debug_port u_ila_0/probe28 [get_nets [list {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[1]} {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[3]} {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[5]} {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[7]} {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[9]} {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[11]} ]]
 create_debug_port u_ila_0 probe
 set_property port_width 4 [get_debug_ports u_ila_0/probe29]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29]
@@ -142,23 +142,23 @@ connect_debug_port u_ila_0/probe30 [get_nets [list {wallypipelinedsoc/uncore/sdc
 create_debug_port u_ila_0 probe
 set_property port_width 2 [get_debug_ports u_ila_0/probe31]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31]
-connect_debug_port u_ila_0/probe31 [get_nets [list {wallypipelinedsoc/hart/lsu/LSUBusSize[0]} {wallypipelinedsoc/hart/lsu/LSUBusSize[1]} ]]
+connect_debug_port u_ila_0/probe31 [get_nets [list {wallypipelinedsoc/core/lsu/LSUBusSize[0]} {wallypipelinedsoc/core/lsu/LSUBusSize[1]} ]]
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe32]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32]
-connect_debug_port u_ila_0/probe32 [get_nets [list wallypipelinedsoc/hart/lsu/LSUBusAck ]]
+connect_debug_port u_ila_0/probe32 [get_nets [list wallypipelinedsoc/core/lsu/LSUBusAck ]]
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe33]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33]
-connect_debug_port u_ila_0/probe33 [get_nets [list wallypipelinedsoc/hart/lsu/LSUBusRead ]]
+connect_debug_port u_ila_0/probe33 [get_nets [list wallypipelinedsoc/core/lsu/LSUBusRead ]]
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe34]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34]
-connect_debug_port u_ila_0/probe34 [get_nets [list wallypipelinedsoc/hart/lsu/LSUBusWrite ]]
+connect_debug_port u_ila_0/probe34 [get_nets [list wallypipelinedsoc/core/lsu/LSUBusWrite ]]
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe35]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35]
-connect_debug_port u_ila_0/probe35 [get_nets [list wallypipelinedsoc/hart/priv.priv/trap/BreakpointFaultM ]]
+connect_debug_port u_ila_0/probe35 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/BreakpointFaultM ]]
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe36]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36]
@@ -166,7 +166,7 @@ connect_debug_port u_ila_0/probe36 [get_nets [list wallypipelinedsoc/uncore/uart
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe37]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37]
-connect_debug_port u_ila_0/probe37 [get_nets [list wallypipelinedsoc/hart/priv.priv/trap/EcallFaultM ]]
+connect_debug_port u_ila_0/probe37 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/EcallFaultM ]]
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe38]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38]
@@ -186,19 +186,19 @@ connect_debug_port u_ila_0/probe41 [get_nets [list wallypipelinedsoc/uncore/sdc.
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe42]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe42]
-connect_debug_port u_ila_0/probe42 [get_nets [list wallypipelinedsoc/hart/priv.priv/trap/IllegalInstrFaultM ]]
+connect_debug_port u_ila_0/probe42 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/IllegalInstrFaultM ]]
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe43]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe43]
-connect_debug_port u_ila_0/probe43 [get_nets [list wallypipelinedsoc/hart/priv.priv/trap/InstrAccessFaultM ]]
+connect_debug_port u_ila_0/probe43 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/InstrAccessFaultM ]]
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe44]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe44]
-connect_debug_port u_ila_0/probe44 [get_nets [list wallypipelinedsoc/hart/priv.priv/trap/InstrPageFaultM ]]
+connect_debug_port u_ila_0/probe44 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/InstrPageFaultM ]]
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe45]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe45]
-connect_debug_port u_ila_0/probe45 [get_nets [list wallypipelinedsoc/hart/InstrValidM ]]
+connect_debug_port u_ila_0/probe45 [get_nets [list wallypipelinedsoc/core/InstrValidM ]]
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe46]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe46]
@@ -206,19 +206,19 @@ connect_debug_port u_ila_0/probe46 [get_nets [list wallypipelinedsoc/uncore/uart
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe47]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe47]
-connect_debug_port u_ila_0/probe47 [get_nets [list wallypipelinedsoc/hart/priv.priv/trap/LoadAccessFaultM ]]
+connect_debug_port u_ila_0/probe47 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/LoadAccessFaultM ]]
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe48]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe48]
-connect_debug_port u_ila_0/probe48 [get_nets [list wallypipelinedsoc/hart/priv.priv/trap/LoadMisalignedFaultM ]]
+connect_debug_port u_ila_0/probe48 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/LoadMisalignedFaultM ]]
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe49]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe49]
-connect_debug_port u_ila_0/probe49 [get_nets [list wallypipelinedsoc/hart/priv.priv/trap/LoadPageFaultM ]]
+connect_debug_port u_ila_0/probe49 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/LoadPageFaultM ]]
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe50]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe50]
-connect_debug_port u_ila_0/probe50 [get_nets [list wallypipelinedsoc/hart/priv.priv/trap/mretM ]]
+connect_debug_port u_ila_0/probe50 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/mretM ]]
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe51]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe51]
@@ -270,23 +270,23 @@ connect_debug_port u_ila_0/probe62 [get_nets [list wallypipelinedsoc/uncore/uart
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe63]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe63]
-connect_debug_port u_ila_0/probe63 [get_nets [list wallypipelinedsoc/hart/priv.priv/trap/sretM ]]
+connect_debug_port u_ila_0/probe63 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/sretM ]]
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe64]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe64]
-connect_debug_port u_ila_0/probe64 [get_nets [list wallypipelinedsoc/hart/priv.priv/trap/StoreAccessFaultM ]]
+connect_debug_port u_ila_0/probe64 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/StoreAccessFaultM ]]
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe65]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe65]
-connect_debug_port u_ila_0/probe65 [get_nets [list wallypipelinedsoc/hart/priv.priv/trap/StoreMisalignedFaultM ]]
+connect_debug_port u_ila_0/probe65 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/StoreMisalignedFaultM ]]
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe66]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe66]
-connect_debug_port u_ila_0/probe66 [get_nets [list wallypipelinedsoc/hart/priv.priv/trap/StorePageFaultM ]]
+connect_debug_port u_ila_0/probe66 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/StorePageFaultM ]]
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe67]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe67]
-connect_debug_port u_ila_0/probe67 [get_nets [list wallypipelinedsoc/hart/TrapM ]]
+connect_debug_port u_ila_0/probe67 [get_nets [list wallypipelinedsoc/core/TrapM ]]
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe68]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe68]
@@ -310,322 +310,321 @@ connect_debug_port u_ila_0/probe71 [get_nets [list wallypipelinedsoc/uncore/sdc.
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe72]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe72]
-connect_debug_port u_ila_0/probe72 [get_nets [list wallypipelinedsoc/hart/hzu/BPPredWrongE ]]
+connect_debug_port u_ila_0/probe72 [get_nets [list wallypipelinedsoc/core/hzu/BPPredWrongE ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe73]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe73]
-connect_debug_port u_ila_0/probe73 [get_nets [list wallypipelinedsoc/hart/hzu/CSRWritePendingDEM ]]
+connect_debug_port u_ila_0/probe73 [get_nets [list wallypipelinedsoc/core/hzu/CSRWritePendingDEM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe74]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe74]
-connect_debug_port u_ila_0/probe74 [get_nets [list wallypipelinedsoc/hart/hzu/RetM ]]
+connect_debug_port u_ila_0/probe74 [get_nets [list wallypipelinedsoc/core/hzu/RetM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe75]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe75]
-connect_debug_port u_ila_0/probe75 [get_nets [list wallypipelinedsoc/hart/hzu/TrapM ]]
+connect_debug_port u_ila_0/probe75 [get_nets [list wallypipelinedsoc/core/hzu/TrapM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe76]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe76]
-connect_debug_port u_ila_0/probe76 [get_nets [list wallypipelinedsoc/hart/hzu/LoadStallD ]]
+connect_debug_port u_ila_0/probe76 [get_nets [list wallypipelinedsoc/core/hzu/LoadStallD ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe77]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe77]
-connect_debug_port u_ila_0/probe77 [get_nets [list wallypipelinedsoc/hart/hzu/StoreStallD ]]
+connect_debug_port u_ila_0/probe77 [get_nets [list wallypipelinedsoc/core/hzu/StoreStallD ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe78]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe78]
-connect_debug_port u_ila_0/probe78 [get_nets [list wallypipelinedsoc/hart/hzu/MDUStallD ]]
+connect_debug_port u_ila_0/probe78 [get_nets [list wallypipelinedsoc/core/hzu/MDUStallD ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe79]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe79]
-connect_debug_port u_ila_0/probe79 [get_nets [list wallypipelinedsoc/hart/hzu/CSRRdStallD ]]
+connect_debug_port u_ila_0/probe79 [get_nets [list wallypipelinedsoc/core/hzu/CSRRdStallD ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe80]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe80]
-connect_debug_port u_ila_0/probe80 [get_nets [list wallypipelinedsoc/hart/hzu/LSUStallM ]]
+connect_debug_port u_ila_0/probe80 [get_nets [list wallypipelinedsoc/core/hzu/LSUStallM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe81]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe81]
-connect_debug_port u_ila_0/probe81 [get_nets [list wallypipelinedsoc/hart/hzu/IFUStallF ]]
+connect_debug_port u_ila_0/probe81 [get_nets [list wallypipelinedsoc/core/hzu/IFUStallF ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe82]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe82]
-connect_debug_port u_ila_0/probe82 [get_nets [list wallypipelinedsoc/hart/hzu/FPUStallD ]]
+connect_debug_port u_ila_0/probe82 [get_nets [list wallypipelinedsoc/core/hzu/FPUStallD ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe83]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe83]
-connect_debug_port u_ila_0/probe83 [get_nets [list wallypipelinedsoc/hart/hzu/FStallD ]]
+connect_debug_port u_ila_0/probe83 [get_nets [list wallypipelinedsoc/core/hzu/FStallD ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe84]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe84]
-connect_debug_port u_ila_0/probe84 [get_nets [list wallypipelinedsoc/hart/hzu/DivBusyE ]]
+connect_debug_port u_ila_0/probe84 [get_nets [list wallypipelinedsoc/core/hzu/DivBusyE ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe85]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe85]
-connect_debug_port u_ila_0/probe85 [get_nets [list wallypipelinedsoc/hart/hzu/FDivBusyE ]]
+connect_debug_port u_ila_0/probe85 [get_nets [list wallypipelinedsoc/core/hzu/FDivBusyE ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe86]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe86]
-connect_debug_port u_ila_0/probe86 [get_nets [list wallypipelinedsoc/hart/hzu/EcallFaultM ]]
+connect_debug_port u_ila_0/probe86 [get_nets [list wallypipelinedsoc/core/hzu/EcallFaultM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe87]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe87]
-connect_debug_port u_ila_0/probe87 [get_nets [list wallypipelinedsoc/hart/hzu/BreakpointFaultM ]]
+connect_debug_port u_ila_0/probe87 [get_nets [list wallypipelinedsoc/core/hzu/BreakpointFaultM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe88]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe88]
-connect_debug_port u_ila_0/probe88 [get_nets [list wallypipelinedsoc/hart/hzu/InvalidateICacheM ]]
+connect_debug_port u_ila_0/probe88 [get_nets [list wallypipelinedsoc/core/hzu/InvalidateICacheM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe89]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe89]
-connect_debug_port u_ila_0/probe89 [get_nets [list wallypipelinedsoc/hart/hzu/StallF ]]
+connect_debug_port u_ila_0/probe89 [get_nets [list wallypipelinedsoc/core/hzu/StallF ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe90]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe90]
-connect_debug_port u_ila_0/probe90 [get_nets [list wallypipelinedsoc/hart/hzu/StallD ]]
+connect_debug_port u_ila_0/probe90 [get_nets [list wallypipelinedsoc/core/hzu/StallD ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe91]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe91]
-connect_debug_port u_ila_0/probe91 [get_nets [list wallypipelinedsoc/hart/hzu/StallE ]]
+connect_debug_port u_ila_0/probe91 [get_nets [list wallypipelinedsoc/core/hzu/StallE ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe92]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe92]
-connect_debug_port u_ila_0/probe92 [get_nets [list wallypipelinedsoc/hart/hzu/StallM ]]
+connect_debug_port u_ila_0/probe92 [get_nets [list wallypipelinedsoc/core/hzu/StallM ]]
 
 # StallW is StallM.  trying to connect to StallW causes issues.
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe93]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe93]
-connect_debug_port u_ila_0/probe93 [get_nets [list wallypipelinedsoc/hart/hzu/StallM ]]
+connect_debug_port u_ila_0/probe93 [get_nets [list wallypipelinedsoc/core/hzu/StallM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe94]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe94]
-connect_debug_port u_ila_0/probe94 [get_nets [list wallypipelinedsoc/hart/hzu/FlushF ]]
+connect_debug_port u_ila_0/probe94 [get_nets [list wallypipelinedsoc/core/hzu/FlushF ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe95]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe95]
-connect_debug_port u_ila_0/probe95 [get_nets [list wallypipelinedsoc/hart/hzu/FlushD ]]
+connect_debug_port u_ila_0/probe95 [get_nets [list wallypipelinedsoc/core/hzu/FlushD ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe96]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe96]
-connect_debug_port u_ila_0/probe96 [get_nets [list wallypipelinedsoc/hart/hzu/FlushE ]]
+connect_debug_port u_ila_0/probe96 [get_nets [list wallypipelinedsoc/core/hzu/FlushE ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe97]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe97]
-connect_debug_port u_ila_0/probe97 [get_nets [list wallypipelinedsoc/hart/hzu/FlushM ]]
+connect_debug_port u_ila_0/probe97 [get_nets [list wallypipelinedsoc/core/hzu/FlushM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe98]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe98]
-connect_debug_port u_ila_0/probe98 [get_nets [list wallypipelinedsoc/hart/hzu/FlushW ]]
+connect_debug_port u_ila_0/probe98 [get_nets [list wallypipelinedsoc/core/hzu/FlushW ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 4 [get_debug_ports u_ila_0/probe99]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe99]
-connect_debug_port u_ila_0/probe99 [get_nets [list {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[0]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[1]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[2]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[3]}]]
+connect_debug_port u_ila_0/probe99 [get_nets [list {wallypipelinedsoc/core/ifu/icache.icache/cachefsm/CurrState[0]} {wallypipelinedsoc/core/ifu/icache.icache/cachefsm/CurrState[1]} {wallypipelinedsoc/core/ifu/icache.icache/cachefsm/CurrState[2]} {wallypipelinedsoc/core/ifu/icache.icache/cachefsm/CurrState[3]}]]
 
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe100]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe100]
-connect_debug_port u_ila_0/probe100 [get_nets [list {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[0]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[1]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[2]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[3]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[4]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[5]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[6]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[7]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[8]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[9]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[10]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[11]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[12]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[13]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[14]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[15]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[16]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[17]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[18]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[19]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[20]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[21]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[22]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[23]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[24]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[25]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[26]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[27]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[28]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[29]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[30]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[31]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[32]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[33]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[34]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[35]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[36]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[37]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[38]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[39]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[40]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[41]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[42]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[43]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[44]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[45]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[46]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[47]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[48]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[49]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[50]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[51]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[52]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[53]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[54]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[55]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[56]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[57]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[58]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[59]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[60]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[61]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[62]} {wallypipelinedsoc/hart/ifu/IFUBusHRDATA[63]}]]
+connect_debug_port u_ila_0/probe100 [get_nets [list {wallypipelinedsoc/core/ifu/IFUBusHRDATA[0]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[1]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[2]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[3]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[4]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[5]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[6]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[7]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[8]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[9]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[10]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[11]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[12]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[13]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[14]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[15]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[16]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[17]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[18]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[19]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[20]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[21]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[22]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[23]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[24]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[25]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[26]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[27]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[28]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[29]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[30]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[31]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[32]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[33]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[34]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[35]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[36]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[37]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[38]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[39]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[40]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[41]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[42]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[43]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[44]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[45]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[46]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[47]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[48]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[49]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[50]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[51]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[52]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[53]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[54]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[55]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[56]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[57]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[58]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[59]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[60]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[61]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[62]} {wallypipelinedsoc/core/ifu/IFUBusHRDATA[63]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe101]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe101]
-connect_debug_port u_ila_0/probe101 [get_nets [list wallypipelinedsoc/hart/ifu/IFUBusAck ]]
+connect_debug_port u_ila_0/probe101 [get_nets [list wallypipelinedsoc/core/ifu/IFUBusAck ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 32 [get_debug_ports u_ila_0/probe102]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe102]
-connect_debug_port u_ila_0/probe102 [get_nets [list {wallypipelinedsoc/hart/ifu/IFUBusAdr[0]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[1]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[2]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[3]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[4]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[5]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[6]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[7]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[8]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[9]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[10]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[11]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[12]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[13]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[14]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[15]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[16]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[17]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[18]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[19]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[20]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[21]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[22]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[23]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[24]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[25]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[26]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[27]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[28]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[29]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[30]} {wallypipelinedsoc/hart/ifu/IFUBusAdr[31]}]]
+connect_debug_port u_ila_0/probe102 [get_nets [list {wallypipelinedsoc/core/ifu/IFUBusAdr[0]} {wallypipelinedsoc/core/ifu/IFUBusAdr[1]} {wallypipelinedsoc/core/ifu/IFUBusAdr[2]} {wallypipelinedsoc/core/ifu/IFUBusAdr[3]} {wallypipelinedsoc/core/ifu/IFUBusAdr[4]} {wallypipelinedsoc/core/ifu/IFUBusAdr[5]} {wallypipelinedsoc/core/ifu/IFUBusAdr[6]} {wallypipelinedsoc/core/ifu/IFUBusAdr[7]} {wallypipelinedsoc/core/ifu/IFUBusAdr[8]} {wallypipelinedsoc/core/ifu/IFUBusAdr[9]} {wallypipelinedsoc/core/ifu/IFUBusAdr[10]} {wallypipelinedsoc/core/ifu/IFUBusAdr[11]} {wallypipelinedsoc/core/ifu/IFUBusAdr[12]} {wallypipelinedsoc/core/ifu/IFUBusAdr[13]} {wallypipelinedsoc/core/ifu/IFUBusAdr[14]} {wallypipelinedsoc/core/ifu/IFUBusAdr[15]} {wallypipelinedsoc/core/ifu/IFUBusAdr[16]} {wallypipelinedsoc/core/ifu/IFUBusAdr[17]} {wallypipelinedsoc/core/ifu/IFUBusAdr[18]} {wallypipelinedsoc/core/ifu/IFUBusAdr[19]} {wallypipelinedsoc/core/ifu/IFUBusAdr[20]} {wallypipelinedsoc/core/ifu/IFUBusAdr[21]} {wallypipelinedsoc/core/ifu/IFUBusAdr[22]} {wallypipelinedsoc/core/ifu/IFUBusAdr[23]} {wallypipelinedsoc/core/ifu/IFUBusAdr[24]} {wallypipelinedsoc/core/ifu/IFUBusAdr[25]} {wallypipelinedsoc/core/ifu/IFUBusAdr[26]} {wallypipelinedsoc/core/ifu/IFUBusAdr[27]} {wallypipelinedsoc/core/ifu/IFUBusAdr[28]} {wallypipelinedsoc/core/ifu/IFUBusAdr[29]} {wallypipelinedsoc/core/ifu/IFUBusAdr[30]} {wallypipelinedsoc/core/ifu/IFUBusAdr[31]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe103]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe103]
-connect_debug_port u_ila_0/probe103 [get_nets [list wallypipelinedsoc/hart/ifu/IFUBusRead ]]
+connect_debug_port u_ila_0/probe103 [get_nets [list wallypipelinedsoc/core/ifu/IFUBusRead ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe104]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe104]
-connect_debug_port u_ila_0/probe104 [get_nets [list {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[0]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[1]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[2]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[3]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[4]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[5]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[6]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[7]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[8]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[9]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[10]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[11]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[12]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[13]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[14]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[15]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[16]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[17]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[18]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[19]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[20]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[21]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[22]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[23]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[24]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[25]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[26]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[27]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[28]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[29]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[30]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[31]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[32]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[33]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[34]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[35]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[36]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[37]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[38]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[39]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[40]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[41]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[42]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[43]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[44]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[45]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[46]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[47]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[48]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[49]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[50]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[51]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[52]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[53]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[54]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[55]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[56]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[57]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[58]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[59]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[60]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[61]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[62]} {wallypipelinedsoc/hart/priv.priv/csr/counters/counters.INSTRET_REGW[63]}]]
+connect_debug_port u_ila_0/probe104 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[63]}]]
 
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe105]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe105]
-connect_debug_port u_ila_0/probe105 [get_nets [list {wallypipelinedsoc/hart/ebu/HRDATA[0]} {wallypipelinedsoc/hart/ebu/HRDATA[1]} {wallypipelinedsoc/hart/ebu/HRDATA[2]} {wallypipelinedsoc/hart/ebu/HRDATA[3]} {wallypipelinedsoc/hart/ebu/HRDATA[4]} {wallypipelinedsoc/hart/ebu/HRDATA[5]} {wallypipelinedsoc/hart/ebu/HRDATA[6]} {wallypipelinedsoc/hart/ebu/HRDATA[7]} {wallypipelinedsoc/hart/ebu/HRDATA[8]} {wallypipelinedsoc/hart/ebu/HRDATA[9]} {wallypipelinedsoc/hart/ebu/HRDATA[10]} {wallypipelinedsoc/hart/ebu/HRDATA[11]} {wallypipelinedsoc/hart/ebu/HRDATA[12]} {wallypipelinedsoc/hart/ebu/HRDATA[13]} {wallypipelinedsoc/hart/ebu/HRDATA[14]} {wallypipelinedsoc/hart/ebu/HRDATA[15]} {wallypipelinedsoc/hart/ebu/HRDATA[16]} {wallypipelinedsoc/hart/ebu/HRDATA[17]} {wallypipelinedsoc/hart/ebu/HRDATA[18]} {wallypipelinedsoc/hart/ebu/HRDATA[19]} {wallypipelinedsoc/hart/ebu/HRDATA[20]} {wallypipelinedsoc/hart/ebu/HRDATA[21]} {wallypipelinedsoc/hart/ebu/HRDATA[22]} {wallypipelinedsoc/hart/ebu/HRDATA[23]} {wallypipelinedsoc/hart/ebu/HRDATA[24]} {wallypipelinedsoc/hart/ebu/HRDATA[25]} {wallypipelinedsoc/hart/ebu/HRDATA[26]} {wallypipelinedsoc/hart/ebu/HRDATA[27]} {wallypipelinedsoc/hart/ebu/HRDATA[28]} {wallypipelinedsoc/hart/ebu/HRDATA[29]} {wallypipelinedsoc/hart/ebu/HRDATA[30]} {wallypipelinedsoc/hart/ebu/HRDATA[31]} {wallypipelinedsoc/hart/ebu/HRDATA[32]} {wallypipelinedsoc/hart/ebu/HRDATA[33]} {wallypipelinedsoc/hart/ebu/HRDATA[34]} {wallypipelinedsoc/hart/ebu/HRDATA[35]} {wallypipelinedsoc/hart/ebu/HRDATA[36]} {wallypipelinedsoc/hart/ebu/HRDATA[37]} {wallypipelinedsoc/hart/ebu/HRDATA[38]} {wallypipelinedsoc/hart/ebu/HRDATA[39]} {wallypipelinedsoc/hart/ebu/HRDATA[40]} {wallypipelinedsoc/hart/ebu/HRDATA[41]} {wallypipelinedsoc/hart/ebu/HRDATA[42]} {wallypipelinedsoc/hart/ebu/HRDATA[43]} {wallypipelinedsoc/hart/ebu/HRDATA[44]} {wallypipelinedsoc/hart/ebu/HRDATA[45]} {wallypipelinedsoc/hart/ebu/HRDATA[46]} {wallypipelinedsoc/hart/ebu/HRDATA[47]} {wallypipelinedsoc/hart/ebu/HRDATA[48]} {wallypipelinedsoc/hart/ebu/HRDATA[49]} {wallypipelinedsoc/hart/ebu/HRDATA[50]} {wallypipelinedsoc/hart/ebu/HRDATA[51]} {wallypipelinedsoc/hart/ebu/HRDATA[52]} {wallypipelinedsoc/hart/ebu/HRDATA[53]} {wallypipelinedsoc/hart/ebu/HRDATA[54]} {wallypipelinedsoc/hart/ebu/HRDATA[55]} {wallypipelinedsoc/hart/ebu/HRDATA[56]} {wallypipelinedsoc/hart/ebu/HRDATA[57]} {wallypipelinedsoc/hart/ebu/HRDATA[58]} {wallypipelinedsoc/hart/ebu/HRDATA[59]} {wallypipelinedsoc/hart/ebu/HRDATA[60]} {wallypipelinedsoc/hart/ebu/HRDATA[61]} {wallypipelinedsoc/hart/ebu/HRDATA[62]} {wallypipelinedsoc/hart/ebu/HRDATA[63]}]]
+connect_debug_port u_ila_0/probe105 [get_nets [list {wallypipelinedsoc/core/ebu/HRDATA[0]} {wallypipelinedsoc/core/ebu/HRDATA[1]} {wallypipelinedsoc/core/ebu/HRDATA[2]} {wallypipelinedsoc/core/ebu/HRDATA[3]} {wallypipelinedsoc/core/ebu/HRDATA[4]} {wallypipelinedsoc/core/ebu/HRDATA[5]} {wallypipelinedsoc/core/ebu/HRDATA[6]} {wallypipelinedsoc/core/ebu/HRDATA[7]} {wallypipelinedsoc/core/ebu/HRDATA[8]} {wallypipelinedsoc/core/ebu/HRDATA[9]} {wallypipelinedsoc/core/ebu/HRDATA[10]} {wallypipelinedsoc/core/ebu/HRDATA[11]} {wallypipelinedsoc/core/ebu/HRDATA[12]} {wallypipelinedsoc/core/ebu/HRDATA[13]} {wallypipelinedsoc/core/ebu/HRDATA[14]} {wallypipelinedsoc/core/ebu/HRDATA[15]} {wallypipelinedsoc/core/ebu/HRDATA[16]} {wallypipelinedsoc/core/ebu/HRDATA[17]} {wallypipelinedsoc/core/ebu/HRDATA[18]} {wallypipelinedsoc/core/ebu/HRDATA[19]} {wallypipelinedsoc/core/ebu/HRDATA[20]} {wallypipelinedsoc/core/ebu/HRDATA[21]} {wallypipelinedsoc/core/ebu/HRDATA[22]} {wallypipelinedsoc/core/ebu/HRDATA[23]} {wallypipelinedsoc/core/ebu/HRDATA[24]} {wallypipelinedsoc/core/ebu/HRDATA[25]} {wallypipelinedsoc/core/ebu/HRDATA[26]} {wallypipelinedsoc/core/ebu/HRDATA[27]} {wallypipelinedsoc/core/ebu/HRDATA[28]} {wallypipelinedsoc/core/ebu/HRDATA[29]} {wallypipelinedsoc/core/ebu/HRDATA[30]} {wallypipelinedsoc/core/ebu/HRDATA[31]} {wallypipelinedsoc/core/ebu/HRDATA[32]} {wallypipelinedsoc/core/ebu/HRDATA[33]} {wallypipelinedsoc/core/ebu/HRDATA[34]} {wallypipelinedsoc/core/ebu/HRDATA[35]} {wallypipelinedsoc/core/ebu/HRDATA[36]} {wallypipelinedsoc/core/ebu/HRDATA[37]} {wallypipelinedsoc/core/ebu/HRDATA[38]} {wallypipelinedsoc/core/ebu/HRDATA[39]} {wallypipelinedsoc/core/ebu/HRDATA[40]} {wallypipelinedsoc/core/ebu/HRDATA[41]} {wallypipelinedsoc/core/ebu/HRDATA[42]} {wallypipelinedsoc/core/ebu/HRDATA[43]} {wallypipelinedsoc/core/ebu/HRDATA[44]} {wallypipelinedsoc/core/ebu/HRDATA[45]} {wallypipelinedsoc/core/ebu/HRDATA[46]} {wallypipelinedsoc/core/ebu/HRDATA[47]} {wallypipelinedsoc/core/ebu/HRDATA[48]} {wallypipelinedsoc/core/ebu/HRDATA[49]} {wallypipelinedsoc/core/ebu/HRDATA[50]} {wallypipelinedsoc/core/ebu/HRDATA[51]} {wallypipelinedsoc/core/ebu/HRDATA[52]} {wallypipelinedsoc/core/ebu/HRDATA[53]} {wallypipelinedsoc/core/ebu/HRDATA[54]} {wallypipelinedsoc/core/ebu/HRDATA[55]} {wallypipelinedsoc/core/ebu/HRDATA[56]} {wallypipelinedsoc/core/ebu/HRDATA[57]} {wallypipelinedsoc/core/ebu/HRDATA[58]} {wallypipelinedsoc/core/ebu/HRDATA[59]} {wallypipelinedsoc/core/ebu/HRDATA[60]} {wallypipelinedsoc/core/ebu/HRDATA[61]} {wallypipelinedsoc/core/ebu/HRDATA[62]} {wallypipelinedsoc/core/ebu/HRDATA[63]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe106]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe106]
-connect_debug_port u_ila_0/probe106 [get_nets [list {wallypipelinedsoc/hart/ebu/HWDATA[0]} {wallypipelinedsoc/hart/ebu/HWDATA[1]} {wallypipelinedsoc/hart/ebu/HWDATA[2]} {wallypipelinedsoc/hart/ebu/HWDATA[3]} {wallypipelinedsoc/hart/ebu/HWDATA[4]} {wallypipelinedsoc/hart/ebu/HWDATA[5]} {wallypipelinedsoc/hart/ebu/HWDATA[6]} {wallypipelinedsoc/hart/ebu/HWDATA[7]} {wallypipelinedsoc/hart/ebu/HWDATA[8]} {wallypipelinedsoc/hart/ebu/HWDATA[9]} {wallypipelinedsoc/hart/ebu/HWDATA[10]} {wallypipelinedsoc/hart/ebu/HWDATA[11]} {wallypipelinedsoc/hart/ebu/HWDATA[12]} {wallypipelinedsoc/hart/ebu/HWDATA[13]} {wallypipelinedsoc/hart/ebu/HWDATA[14]} {wallypipelinedsoc/hart/ebu/HWDATA[15]} {wallypipelinedsoc/hart/ebu/HWDATA[16]} {wallypipelinedsoc/hart/ebu/HWDATA[17]} {wallypipelinedsoc/hart/ebu/HWDATA[18]} {wallypipelinedsoc/hart/ebu/HWDATA[19]} {wallypipelinedsoc/hart/ebu/HWDATA[20]} {wallypipelinedsoc/hart/ebu/HWDATA[21]} {wallypipelinedsoc/hart/ebu/HWDATA[22]} {wallypipelinedsoc/hart/ebu/HWDATA[23]} {wallypipelinedsoc/hart/ebu/HWDATA[24]} {wallypipelinedsoc/hart/ebu/HWDATA[25]} {wallypipelinedsoc/hart/ebu/HWDATA[26]} {wallypipelinedsoc/hart/ebu/HWDATA[27]} {wallypipelinedsoc/hart/ebu/HWDATA[28]} {wallypipelinedsoc/hart/ebu/HWDATA[29]} {wallypipelinedsoc/hart/ebu/HWDATA[30]} {wallypipelinedsoc/hart/ebu/HWDATA[31]} {wallypipelinedsoc/hart/ebu/HWDATA[32]} {wallypipelinedsoc/hart/ebu/HWDATA[33]} {wallypipelinedsoc/hart/ebu/HWDATA[34]} {wallypipelinedsoc/hart/ebu/HWDATA[35]} {wallypipelinedsoc/hart/ebu/HWDATA[36]} {wallypipelinedsoc/hart/ebu/HWDATA[37]} {wallypipelinedsoc/hart/ebu/HWDATA[38]} {wallypipelinedsoc/hart/ebu/HWDATA[39]} {wallypipelinedsoc/hart/ebu/HWDATA[40]} {wallypipelinedsoc/hart/ebu/HWDATA[41]} {wallypipelinedsoc/hart/ebu/HWDATA[42]} {wallypipelinedsoc/hart/ebu/HWDATA[43]} {wallypipelinedsoc/hart/ebu/HWDATA[44]} {wallypipelinedsoc/hart/ebu/HWDATA[45]} {wallypipelinedsoc/hart/ebu/HWDATA[46]} {wallypipelinedsoc/hart/ebu/HWDATA[47]} {wallypipelinedsoc/hart/ebu/HWDATA[48]} {wallypipelinedsoc/hart/ebu/HWDATA[49]} {wallypipelinedsoc/hart/ebu/HWDATA[50]} {wallypipelinedsoc/hart/ebu/HWDATA[51]} {wallypipelinedsoc/hart/ebu/HWDATA[52]} {wallypipelinedsoc/hart/ebu/HWDATA[53]} {wallypipelinedsoc/hart/ebu/HWDATA[54]} {wallypipelinedsoc/hart/ebu/HWDATA[55]} {wallypipelinedsoc/hart/ebu/HWDATA[56]} {wallypipelinedsoc/hart/ebu/HWDATA[57]} {wallypipelinedsoc/hart/ebu/HWDATA[58]} {wallypipelinedsoc/hart/ebu/HWDATA[59]} {wallypipelinedsoc/hart/ebu/HWDATA[60]} {wallypipelinedsoc/hart/ebu/HWDATA[61]} {wallypipelinedsoc/hart/ebu/HWDATA[62]} {wallypipelinedsoc/hart/ebu/HWDATA[63]}]]
+connect_debug_port u_ila_0/probe106 [get_nets [list {wallypipelinedsoc/core/ebu/HWDATA[0]} {wallypipelinedsoc/core/ebu/HWDATA[1]} {wallypipelinedsoc/core/ebu/HWDATA[2]} {wallypipelinedsoc/core/ebu/HWDATA[3]} {wallypipelinedsoc/core/ebu/HWDATA[4]} {wallypipelinedsoc/core/ebu/HWDATA[5]} {wallypipelinedsoc/core/ebu/HWDATA[6]} {wallypipelinedsoc/core/ebu/HWDATA[7]} {wallypipelinedsoc/core/ebu/HWDATA[8]} {wallypipelinedsoc/core/ebu/HWDATA[9]} {wallypipelinedsoc/core/ebu/HWDATA[10]} {wallypipelinedsoc/core/ebu/HWDATA[11]} {wallypipelinedsoc/core/ebu/HWDATA[12]} {wallypipelinedsoc/core/ebu/HWDATA[13]} {wallypipelinedsoc/core/ebu/HWDATA[14]} {wallypipelinedsoc/core/ebu/HWDATA[15]} {wallypipelinedsoc/core/ebu/HWDATA[16]} {wallypipelinedsoc/core/ebu/HWDATA[17]} {wallypipelinedsoc/core/ebu/HWDATA[18]} {wallypipelinedsoc/core/ebu/HWDATA[19]} {wallypipelinedsoc/core/ebu/HWDATA[20]} {wallypipelinedsoc/core/ebu/HWDATA[21]} {wallypipelinedsoc/core/ebu/HWDATA[22]} {wallypipelinedsoc/core/ebu/HWDATA[23]} {wallypipelinedsoc/core/ebu/HWDATA[24]} {wallypipelinedsoc/core/ebu/HWDATA[25]} {wallypipelinedsoc/core/ebu/HWDATA[26]} {wallypipelinedsoc/core/ebu/HWDATA[27]} {wallypipelinedsoc/core/ebu/HWDATA[28]} {wallypipelinedsoc/core/ebu/HWDATA[29]} {wallypipelinedsoc/core/ebu/HWDATA[30]} {wallypipelinedsoc/core/ebu/HWDATA[31]} {wallypipelinedsoc/core/ebu/HWDATA[32]} {wallypipelinedsoc/core/ebu/HWDATA[33]} {wallypipelinedsoc/core/ebu/HWDATA[34]} {wallypipelinedsoc/core/ebu/HWDATA[35]} {wallypipelinedsoc/core/ebu/HWDATA[36]} {wallypipelinedsoc/core/ebu/HWDATA[37]} {wallypipelinedsoc/core/ebu/HWDATA[38]} {wallypipelinedsoc/core/ebu/HWDATA[39]} {wallypipelinedsoc/core/ebu/HWDATA[40]} {wallypipelinedsoc/core/ebu/HWDATA[41]} {wallypipelinedsoc/core/ebu/HWDATA[42]} {wallypipelinedsoc/core/ebu/HWDATA[43]} {wallypipelinedsoc/core/ebu/HWDATA[44]} {wallypipelinedsoc/core/ebu/HWDATA[45]} {wallypipelinedsoc/core/ebu/HWDATA[46]} {wallypipelinedsoc/core/ebu/HWDATA[47]} {wallypipelinedsoc/core/ebu/HWDATA[48]} {wallypipelinedsoc/core/ebu/HWDATA[49]} {wallypipelinedsoc/core/ebu/HWDATA[50]} {wallypipelinedsoc/core/ebu/HWDATA[51]} {wallypipelinedsoc/core/ebu/HWDATA[52]} {wallypipelinedsoc/core/ebu/HWDATA[53]} {wallypipelinedsoc/core/ebu/HWDATA[54]} {wallypipelinedsoc/core/ebu/HWDATA[55]} {wallypipelinedsoc/core/ebu/HWDATA[56]} {wallypipelinedsoc/core/ebu/HWDATA[57]} {wallypipelinedsoc/core/ebu/HWDATA[58]} {wallypipelinedsoc/core/ebu/HWDATA[59]} {wallypipelinedsoc/core/ebu/HWDATA[60]} {wallypipelinedsoc/core/ebu/HWDATA[61]} {wallypipelinedsoc/core/ebu/HWDATA[62]} {wallypipelinedsoc/core/ebu/HWDATA[63]}]]
 
 
 create_debug_port u_ila_0 probe
 set_property port_width 32 [get_debug_ports u_ila_0/probe107]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe107]
-connect_debug_port u_ila_0/probe107 [get_nets [list {wallypipelinedsoc/hart/ebu/HADDR[0]} {wallypipelinedsoc/hart/ebu/HADDR[1]} {wallypipelinedsoc/hart/ebu/HADDR[2]} {wallypipelinedsoc/hart/ebu/HADDR[3]} {wallypipelinedsoc/hart/ebu/HADDR[4]} {wallypipelinedsoc/hart/ebu/HADDR[5]} {wallypipelinedsoc/hart/ebu/HADDR[6]} {wallypipelinedsoc/hart/ebu/HADDR[7]} {wallypipelinedsoc/hart/ebu/HADDR[8]} {wallypipelinedsoc/hart/ebu/HADDR[9]} {wallypipelinedsoc/hart/ebu/HADDR[10]} {wallypipelinedsoc/hart/ebu/HADDR[11]} {wallypipelinedsoc/hart/ebu/HADDR[12]} {wallypipelinedsoc/hart/ebu/HADDR[13]} {wallypipelinedsoc/hart/ebu/HADDR[14]} {wallypipelinedsoc/hart/ebu/HADDR[15]} {wallypipelinedsoc/hart/ebu/HADDR[16]} {wallypipelinedsoc/hart/ebu/HADDR[17]} {wallypipelinedsoc/hart/ebu/HADDR[18]} {wallypipelinedsoc/hart/ebu/HADDR[19]} {wallypipelinedsoc/hart/ebu/HADDR[20]} {wallypipelinedsoc/hart/ebu/HADDR[21]} {wallypipelinedsoc/hart/ebu/HADDR[22]} {wallypipelinedsoc/hart/ebu/HADDR[23]} {wallypipelinedsoc/hart/ebu/HADDR[24]} {wallypipelinedsoc/hart/ebu/HADDR[25]} {wallypipelinedsoc/hart/ebu/HADDR[26]} {wallypipelinedsoc/hart/ebu/HADDR[27]} {wallypipelinedsoc/hart/ebu/HADDR[28]} {wallypipelinedsoc/hart/ebu/HADDR[29]} {wallypipelinedsoc/hart/ebu/HADDR[30]} {wallypipelinedsoc/hart/ebu/HADDR[31]}]]
+connect_debug_port u_ila_0/probe107 [get_nets [list {wallypipelinedsoc/core/ebu/HADDR[0]} {wallypipelinedsoc/core/ebu/HADDR[1]} {wallypipelinedsoc/core/ebu/HADDR[2]} {wallypipelinedsoc/core/ebu/HADDR[3]} {wallypipelinedsoc/core/ebu/HADDR[4]} {wallypipelinedsoc/core/ebu/HADDR[5]} {wallypipelinedsoc/core/ebu/HADDR[6]} {wallypipelinedsoc/core/ebu/HADDR[7]} {wallypipelinedsoc/core/ebu/HADDR[8]} {wallypipelinedsoc/core/ebu/HADDR[9]} {wallypipelinedsoc/core/ebu/HADDR[10]} {wallypipelinedsoc/core/ebu/HADDR[11]} {wallypipelinedsoc/core/ebu/HADDR[12]} {wallypipelinedsoc/core/ebu/HADDR[13]} {wallypipelinedsoc/core/ebu/HADDR[14]} {wallypipelinedsoc/core/ebu/HADDR[15]} {wallypipelinedsoc/core/ebu/HADDR[16]} {wallypipelinedsoc/core/ebu/HADDR[17]} {wallypipelinedsoc/core/ebu/HADDR[18]} {wallypipelinedsoc/core/ebu/HADDR[19]} {wallypipelinedsoc/core/ebu/HADDR[20]} {wallypipelinedsoc/core/ebu/HADDR[21]} {wallypipelinedsoc/core/ebu/HADDR[22]} {wallypipelinedsoc/core/ebu/HADDR[23]} {wallypipelinedsoc/core/ebu/HADDR[24]} {wallypipelinedsoc/core/ebu/HADDR[25]} {wallypipelinedsoc/core/ebu/HADDR[26]} {wallypipelinedsoc/core/ebu/HADDR[27]} {wallypipelinedsoc/core/ebu/HADDR[28]} {wallypipelinedsoc/core/ebu/HADDR[29]} {wallypipelinedsoc/core/ebu/HADDR[30]} {wallypipelinedsoc/core/ebu/HADDR[31]}]]
 
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe108]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe108]
-connect_debug_port u_ila_0/probe108 [get_nets [list {wallypipelinedsoc/hart/ebu/HREADY}]]
+connect_debug_port u_ila_0/probe108 [get_nets [list {wallypipelinedsoc/core/ebu/HREADY}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe109]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe109]
-connect_debug_port u_ila_0/probe109 [get_nets [list {wallypipelinedsoc/hart/ebu/HRESP}]]
+connect_debug_port u_ila_0/probe109 [get_nets [list {wallypipelinedsoc/core/ebu/HRESP}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe110]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe110]
-connect_debug_port u_ila_0/probe110 [get_nets [list {wallypipelinedsoc/hart/ebu/HWRITE}]]
+connect_debug_port u_ila_0/probe110 [get_nets [list {wallypipelinedsoc/core/ebu/HWRITE}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 3 [get_debug_ports u_ila_0/probe111]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe111]
-connect_debug_port u_ila_0/probe111 [get_nets [list {wallypipelinedsoc/hart/ebu/HSIZE[0]} {wallypipelinedsoc/hart/ebu/HSIZE[1]} {wallypipelinedsoc/hart/ebu/HSIZE[2]}]]
+connect_debug_port u_ila_0/probe111 [get_nets [list {wallypipelinedsoc/core/ebu/HSIZE[0]} {wallypipelinedsoc/core/ebu/HSIZE[1]} {wallypipelinedsoc/core/ebu/HSIZE[2]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 3 [get_debug_ports u_ila_0/probe112]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe112]
-connect_debug_port u_ila_0/probe112 [get_nets [list {wallypipelinedsoc/hart/ebu/HBURST[0]} {wallypipelinedsoc/hart/ebu/HBURST[1]} {wallypipelinedsoc/hart/ebu/HBURST[2]}]]
+connect_debug_port u_ila_0/probe112 [get_nets [list {wallypipelinedsoc/core/ebu/HBURST[0]} {wallypipelinedsoc/core/ebu/HBURST[1]} {wallypipelinedsoc/core/ebu/HBURST[2]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 4 [get_debug_ports u_ila_0/probe113]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe113]
-connect_debug_port u_ila_0/probe113 [get_nets [list {wallypipelinedsoc/hart/ebu/HPROT[0]} {wallypipelinedsoc/hart/ebu/HPROT[1]} {wallypipelinedsoc/hart/ebu/HPROT[2]} {wallypipelinedsoc/hart/ebu/HPROT[3]}]]
+connect_debug_port u_ila_0/probe113 [get_nets [list {wallypipelinedsoc/core/ebu/HPROT[0]} {wallypipelinedsoc/core/ebu/HPROT[1]} {wallypipelinedsoc/core/ebu/HPROT[2]} {wallypipelinedsoc/core/ebu/HPROT[3]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe114]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe114]
-connect_debug_port u_ila_0/probe114 [get_nets [list {wallypipelinedsoc/hart/ebu/HMASTLOCK}]]
+connect_debug_port u_ila_0/probe114 [get_nets [list {wallypipelinedsoc/core/ebu/HMASTLOCK}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe115]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe115]
-connect_debug_port u_ila_0/probe115 [get_nets [list {wallypipelinedsoc/hart/priv.priv/InterruptM}]]
+connect_debug_port u_ila_0/probe115 [get_nets [list {wallypipelinedsoc/core/priv.priv/InterruptM}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe116]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe116]
-connect_debug_port u_ila_0/probe116 [get_nets [list wallypipelinedsoc/hart/lsu/ITLBMissF]]
+connect_debug_port u_ila_0/probe116 [get_nets [list wallypipelinedsoc/core/lsu/ITLBMissF]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe117]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe117]
-connect_debug_port u_ila_0/probe117 [get_nets [list wallypipelinedsoc/hart/lsu/DTLBMissM]]
+connect_debug_port u_ila_0/probe117 [get_nets [list wallypipelinedsoc/core/lsu/DTLBMissM]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe118]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe118]
-connect_debug_port u_ila_0/probe118 [get_nets [list wallypipelinedsoc/hart/lsu/ITLBWriteF]]
+connect_debug_port u_ila_0/probe118 [get_nets [list wallypipelinedsoc/core/lsu/ITLBWriteF]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe119]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe119]
-connect_debug_port u_ila_0/probe119 [get_nets [list wallypipelinedsoc/hart/lsu/DTLBWriteM]]
+connect_debug_port u_ila_0/probe119 [get_nets [list wallypipelinedsoc/core/lsu/DTLBWriteM]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 11 [get_debug_ports u_ila_0/probe120]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe120]
-connect_debug_port u_ila_0/probe120 [get_nets [list {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM.hptw/WalkerState[0]} {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM.hptw/WalkerState[1]} {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM.hptw/WalkerState[2]} {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM.hptw/WalkerState[3]} {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM.hptw/WalkerState[4]} {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM.hptw/WalkerState[5]} {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM.hptw/WalkerState[6]} {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM.hptw/WalkerState[7]} {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM.hptw/WalkerState[8]} {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM.hptw/WalkerState[9]} {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM.hptw/WalkerState[10]}]]
+connect_debug_port u_ila_0/probe120 [get_nets [list {wallypipelinedsoc/core/lsu/MEM_VIRTMEM.hptw/WalkerState[0]} {wallypipelinedsoc/core/lsu/MEM_VIRTMEM.hptw/WalkerState[1]} {wallypipelinedsoc/core/lsu/MEM_VIRTMEM.hptw/WalkerState[2]} {wallypipelinedsoc/core/lsu/MEM_VIRTMEM.hptw/WalkerState[3]} {wallypipelinedsoc/core/lsu/MEM_VIRTMEM.hptw/WalkerState[4]} {wallypipelinedsoc/core/lsu/MEM_VIRTMEM.hptw/WalkerState[5]} {wallypipelinedsoc/core/lsu/MEM_VIRTMEM.hptw/WalkerState[6]} {wallypipelinedsoc/core/lsu/MEM_VIRTMEM.hptw/WalkerState[7]} {wallypipelinedsoc/core/lsu/MEM_VIRTMEM.hptw/WalkerState[8]} {wallypipelinedsoc/core/lsu/MEM_VIRTMEM.hptw/WalkerState[9]} {wallypipelinedsoc/core/lsu/MEM_VIRTMEM.hptw/WalkerState[10]}]]
 
 
 create_debug_port u_ila_0 probe
 set_property port_width 56 [get_debug_ports u_ila_0/probe121]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe121]
-connect_debug_port u_ila_0/probe121 [get_nets [list {wallypipelinedsoc/hart/lsu/IEUAdrM[0]} {wallypipelinedsoc/hart/lsu/IEUAdrM[1]} {wallypipelinedsoc/hart/lsu/IEUAdrM[2]} {wallypipelinedsoc/hart/lsu/IEUAdrM[3]} {wallypipelinedsoc/hart/lsu/IEUAdrM[4]} {wallypipelinedsoc/hart/lsu/IEUAdrM[5]} {wallypipelinedsoc/hart/lsu/IEUAdrM[6]} {wallypipelinedsoc/hart/lsu/IEUAdrM[7]} {wallypipelinedsoc/hart/lsu/IEUAdrM[8]} {wallypipelinedsoc/hart/lsu/IEUAdrM[9]} {wallypipelinedsoc/hart/lsu/IEUAdrM[10]} {wallypipelinedsoc/hart/lsu/IEUAdrM[11]} {wallypipelinedsoc/hart/lsu/IEUAdrM[12]} {wallypipelinedsoc/hart/lsu/IEUAdrM[13]} {wallypipelinedsoc/hart/lsu/IEUAdrM[14]} {wallypipelinedsoc/hart/lsu/IEUAdrM[15]} {wallypipelinedsoc/hart/lsu/IEUAdrM[16]} {wallypipelinedsoc/hart/lsu/IEUAdrM[17]} {wallypipelinedsoc/hart/lsu/IEUAdrM[18]} {wallypipelinedsoc/hart/lsu/IEUAdrM[19]} {wallypipelinedsoc/hart/lsu/IEUAdrM[20]} {wallypipelinedsoc/hart/lsu/IEUAdrM[21]} {wallypipelinedsoc/hart/lsu/IEUAdrM[22]} {wallypipelinedsoc/hart/lsu/IEUAdrM[23]} {wallypipelinedsoc/hart/lsu/IEUAdrM[24]} {wallypipelinedsoc/hart/lsu/IEUAdrM[25]} {wallypipelinedsoc/hart/lsu/IEUAdrM[26]} {wallypipelinedsoc/hart/lsu/IEUAdrM[27]} {wallypipelinedsoc/hart/lsu/IEUAdrM[28]} {wallypipelinedsoc/hart/lsu/IEUAdrM[29]} {wallypipelinedsoc/hart/lsu/IEUAdrM[30]} {wallypipelinedsoc/hart/lsu/IEUAdrM[31]} {wallypipelinedsoc/hart/lsu/IEUAdrM[32]} {wallypipelinedsoc/hart/lsu/IEUAdrM[33]} {wallypipelinedsoc/hart/lsu/IEUAdrM[34]} {wallypipelinedsoc/hart/lsu/IEUAdrM[35]} {wallypipelinedsoc/hart/lsu/IEUAdrM[36]} {wallypipelinedsoc/hart/lsu/IEUAdrM[37]} {wallypipelinedsoc/hart/lsu/IEUAdrM[38]} {wallypipelinedsoc/hart/lsu/IEUAdrM[39]} {wallypipelinedsoc/hart/lsu/IEUAdrM[40]} {wallypipelinedsoc/hart/lsu/IEUAdrM[41]} {wallypipelinedsoc/hart/lsu/IEUAdrM[42]} {wallypipelinedsoc/hart/lsu/IEUAdrM[43]} {wallypipelinedsoc/hart/lsu/IEUAdrM[44]} {wallypipelinedsoc/hart/lsu/IEUAdrM[45]} {wallypipelinedsoc/hart/lsu/IEUAdrM[46]} {wallypipelinedsoc/hart/lsu/IEUAdrM[47]} {wallypipelinedsoc/hart/lsu/IEUAdrM[48]} {wallypipelinedsoc/hart/lsu/IEUAdrM[49]} {wallypipelinedsoc/hart/lsu/IEUAdrM[50]} {wallypipelinedsoc/hart/lsu/IEUAdrM[51]} {wallypipelinedsoc/hart/lsu/IEUAdrM[52]} {wallypipelinedsoc/hart/lsu/IEUAdrM[53]} {wallypipelinedsoc/hart/lsu/IEUAdrM[54]} {wallypipelinedsoc/hart/lsu/IEUAdrM[55]} ]]
+connect_debug_port u_ila_0/probe121 [get_nets [list {wallypipelinedsoc/core/lsu/IEUAdrM[0]} {wallypipelinedsoc/core/lsu/IEUAdrM[1]} {wallypipelinedsoc/core/lsu/IEUAdrM[2]} {wallypipelinedsoc/core/lsu/IEUAdrM[3]} {wallypipelinedsoc/core/lsu/IEUAdrM[4]} {wallypipelinedsoc/core/lsu/IEUAdrM[5]} {wallypipelinedsoc/core/lsu/IEUAdrM[6]} {wallypipelinedsoc/core/lsu/IEUAdrM[7]} {wallypipelinedsoc/core/lsu/IEUAdrM[8]} {wallypipelinedsoc/core/lsu/IEUAdrM[9]} {wallypipelinedsoc/core/lsu/IEUAdrM[10]} {wallypipelinedsoc/core/lsu/IEUAdrM[11]} {wallypipelinedsoc/core/lsu/IEUAdrM[12]} {wallypipelinedsoc/core/lsu/IEUAdrM[13]} {wallypipelinedsoc/core/lsu/IEUAdrM[14]} {wallypipelinedsoc/core/lsu/IEUAdrM[15]} {wallypipelinedsoc/core/lsu/IEUAdrM[16]} {wallypipelinedsoc/core/lsu/IEUAdrM[17]} {wallypipelinedsoc/core/lsu/IEUAdrM[18]} {wallypipelinedsoc/core/lsu/IEUAdrM[19]} {wallypipelinedsoc/core/lsu/IEUAdrM[20]} {wallypipelinedsoc/core/lsu/IEUAdrM[21]} {wallypipelinedsoc/core/lsu/IEUAdrM[22]} {wallypipelinedsoc/core/lsu/IEUAdrM[23]} {wallypipelinedsoc/core/lsu/IEUAdrM[24]} {wallypipelinedsoc/core/lsu/IEUAdrM[25]} {wallypipelinedsoc/core/lsu/IEUAdrM[26]} {wallypipelinedsoc/core/lsu/IEUAdrM[27]} {wallypipelinedsoc/core/lsu/IEUAdrM[28]} {wallypipelinedsoc/core/lsu/IEUAdrM[29]} {wallypipelinedsoc/core/lsu/IEUAdrM[30]} {wallypipelinedsoc/core/lsu/IEUAdrM[31]} {wallypipelinedsoc/core/lsu/IEUAdrM[32]} {wallypipelinedsoc/core/lsu/IEUAdrM[33]} {wallypipelinedsoc/core/lsu/IEUAdrM[34]} {wallypipelinedsoc/core/lsu/IEUAdrM[35]} {wallypipelinedsoc/core/lsu/IEUAdrM[36]} {wallypipelinedsoc/core/lsu/IEUAdrM[37]} {wallypipelinedsoc/core/lsu/IEUAdrM[38]} {wallypipelinedsoc/core/lsu/IEUAdrM[39]} {wallypipelinedsoc/core/lsu/IEUAdrM[40]} {wallypipelinedsoc/core/lsu/IEUAdrM[41]} {wallypipelinedsoc/core/lsu/IEUAdrM[42]} {wallypipelinedsoc/core/lsu/IEUAdrM[43]} {wallypipelinedsoc/core/lsu/IEUAdrM[44]} {wallypipelinedsoc/core/lsu/IEUAdrM[45]} {wallypipelinedsoc/core/lsu/IEUAdrM[46]} {wallypipelinedsoc/core/lsu/IEUAdrM[47]} {wallypipelinedsoc/core/lsu/IEUAdrM[48]} {wallypipelinedsoc/core/lsu/IEUAdrM[49]} {wallypipelinedsoc/core/lsu/IEUAdrM[50]} {wallypipelinedsoc/core/lsu/IEUAdrM[51]} {wallypipelinedsoc/core/lsu/IEUAdrM[52]} {wallypipelinedsoc/core/lsu/IEUAdrM[53]} {wallypipelinedsoc/core/lsu/IEUAdrM[54]} {wallypipelinedsoc/core/lsu/IEUAdrM[55]} ]]
 
 
 create_debug_port u_ila_0 probe
 set_property port_width 56 [get_debug_ports u_ila_0/probe122]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe122]
-connect_debug_port u_ila_0/probe122 [get_nets [list {wallypipelinedsoc/hart/ifu/PCPF[0]} {wallypipelinedsoc/hart/ifu/PCPF[1]} {wallypipelinedsoc/hart/ifu/PCPF[2]} {wallypipelinedsoc/hart/ifu/PCPF[3]} {wallypipelinedsoc/hart/ifu/PCPF[4]} {wallypipelinedsoc/hart/ifu/PCPF[5]} {wallypipelinedsoc/hart/ifu/PCPF[6]} {wallypipelinedsoc/hart/ifu/PCPF[7]} {wallypipelinedsoc/hart/ifu/PCPF[8]} {wallypipelinedsoc/hart/ifu/PCPF[9]} {wallypipelinedsoc/hart/ifu/PCPF[10]} {wallypipelinedsoc/hart/ifu/PCPF[11]} {wallypipelinedsoc/hart/ifu/PCPF[12]} {wallypipelinedsoc/hart/ifu/PCPF[13]} {wallypipelinedsoc/hart/ifu/PCPF[14]} {wallypipelinedsoc/hart/ifu/PCPF[15]} {wallypipelinedsoc/hart/ifu/PCPF[16]} {wallypipelinedsoc/hart/ifu/PCPF[17]} {wallypipelinedsoc/hart/ifu/PCPF[18]} {wallypipelinedsoc/hart/ifu/PCPF[19]} {wallypipelinedsoc/hart/ifu/PCPF[20]} {wallypipelinedsoc/hart/ifu/PCPF[21]} {wallypipelinedsoc/hart/ifu/PCPF[22]} {wallypipelinedsoc/hart/ifu/PCPF[23]} {wallypipelinedsoc/hart/ifu/PCPF[24]} {wallypipelinedsoc/hart/ifu/PCPF[25]} {wallypipelinedsoc/hart/ifu/PCPF[26]} {wallypipelinedsoc/hart/ifu/PCPF[27]} {wallypipelinedsoc/hart/ifu/PCPF[28]} {wallypipelinedsoc/hart/ifu/PCPF[29]} {wallypipelinedsoc/hart/ifu/PCPF[30]} {wallypipelinedsoc/hart/ifu/PCPF[31]} {wallypipelinedsoc/hart/ifu/PCPF[32]} {wallypipelinedsoc/hart/ifu/PCPF[33]} {wallypipelinedsoc/hart/ifu/PCPF[34]} {wallypipelinedsoc/hart/ifu/PCPF[35]} {wallypipelinedsoc/hart/ifu/PCPF[36]} {wallypipelinedsoc/hart/ifu/PCPF[37]} {wallypipelinedsoc/hart/ifu/PCPF[38]} {wallypipelinedsoc/hart/ifu/PCPF[39]} {wallypipelinedsoc/hart/ifu/PCPF[40]} {wallypipelinedsoc/hart/ifu/PCPF[41]} {wallypipelinedsoc/hart/ifu/PCPF[42]} {wallypipelinedsoc/hart/ifu/PCPF[43]} {wallypipelinedsoc/hart/ifu/PCPF[44]} {wallypipelinedsoc/hart/ifu/PCPF[45]} {wallypipelinedsoc/hart/ifu/PCPF[46]} {wallypipelinedsoc/hart/ifu/PCPF[47]} {wallypipelinedsoc/hart/ifu/PCPF[48]} {wallypipelinedsoc/hart/ifu/PCPF[49]} {wallypipelinedsoc/hart/ifu/PCPF[50]} {wallypipelinedsoc/hart/ifu/PCPF[51]} {wallypipelinedsoc/hart/ifu/PCPF[52]} {wallypipelinedsoc/hart/ifu/PCPF[53]} {wallypipelinedsoc/hart/ifu/PCPF[54]} {wallypipelinedsoc/hart/ifu/PCPF[55]} ]]
+connect_debug_port u_ila_0/probe122 [get_nets [list {wallypipelinedsoc/core/ifu/PCPF[0]} {wallypipelinedsoc/core/ifu/PCPF[1]} {wallypipelinedsoc/core/ifu/PCPF[2]} {wallypipelinedsoc/core/ifu/PCPF[3]} {wallypipelinedsoc/core/ifu/PCPF[4]} {wallypipelinedsoc/core/ifu/PCPF[5]} {wallypipelinedsoc/core/ifu/PCPF[6]} {wallypipelinedsoc/core/ifu/PCPF[7]} {wallypipelinedsoc/core/ifu/PCPF[8]} {wallypipelinedsoc/core/ifu/PCPF[9]} {wallypipelinedsoc/core/ifu/PCPF[10]} {wallypipelinedsoc/core/ifu/PCPF[11]} {wallypipelinedsoc/core/ifu/PCPF[12]} {wallypipelinedsoc/core/ifu/PCPF[13]} {wallypipelinedsoc/core/ifu/PCPF[14]} {wallypipelinedsoc/core/ifu/PCPF[15]} {wallypipelinedsoc/core/ifu/PCPF[16]} {wallypipelinedsoc/core/ifu/PCPF[17]} {wallypipelinedsoc/core/ifu/PCPF[18]} {wallypipelinedsoc/core/ifu/PCPF[19]} {wallypipelinedsoc/core/ifu/PCPF[20]} {wallypipelinedsoc/core/ifu/PCPF[21]} {wallypipelinedsoc/core/ifu/PCPF[22]} {wallypipelinedsoc/core/ifu/PCPF[23]} {wallypipelinedsoc/core/ifu/PCPF[24]} {wallypipelinedsoc/core/ifu/PCPF[25]} {wallypipelinedsoc/core/ifu/PCPF[26]} {wallypipelinedsoc/core/ifu/PCPF[27]} {wallypipelinedsoc/core/ifu/PCPF[28]} {wallypipelinedsoc/core/ifu/PCPF[29]} {wallypipelinedsoc/core/ifu/PCPF[30]} {wallypipelinedsoc/core/ifu/PCPF[31]} {wallypipelinedsoc/core/ifu/PCPF[32]} {wallypipelinedsoc/core/ifu/PCPF[33]} {wallypipelinedsoc/core/ifu/PCPF[34]} {wallypipelinedsoc/core/ifu/PCPF[35]} {wallypipelinedsoc/core/ifu/PCPF[36]} {wallypipelinedsoc/core/ifu/PCPF[37]} {wallypipelinedsoc/core/ifu/PCPF[38]} {wallypipelinedsoc/core/ifu/PCPF[39]} {wallypipelinedsoc/core/ifu/PCPF[40]} {wallypipelinedsoc/core/ifu/PCPF[41]} {wallypipelinedsoc/core/ifu/PCPF[42]} {wallypipelinedsoc/core/ifu/PCPF[43]} {wallypipelinedsoc/core/ifu/PCPF[44]} {wallypipelinedsoc/core/ifu/PCPF[45]} {wallypipelinedsoc/core/ifu/PCPF[46]} {wallypipelinedsoc/core/ifu/PCPF[47]} {wallypipelinedsoc/core/ifu/PCPF[48]} {wallypipelinedsoc/core/ifu/PCPF[49]} {wallypipelinedsoc/core/ifu/PCPF[50]} {wallypipelinedsoc/core/ifu/PCPF[51]} {wallypipelinedsoc/core/ifu/PCPF[52]} {wallypipelinedsoc/core/ifu/PCPF[53]} {wallypipelinedsoc/core/ifu/PCPF[54]} {wallypipelinedsoc/core/ifu/PCPF[55]} ]]
 
 
 
 create_debug_port u_ila_0 probe
 set_property port_width 3 [get_debug_ports u_ila_0/probe123]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe123]
-connect_debug_port u_ila_0/probe123 [get_nets [list {wallypipelinedsoc/hart/ifu/bus.busfsm/BusCurrState[0]} {wallypipelinedsoc/hart/ifu/bus.busfsm/BusCurrState[1]} {wallypipelinedsoc/hart/ifu/bus.busfsm/BusCurrState[2]} ]]
+connect_debug_port u_ila_0/probe123 [get_nets [list {wallypipelinedsoc/core/ifu/bus.busfsm/BusCurrState[0]} {wallypipelinedsoc/core/ifu/bus.busfsm/BusCurrState[1]} {wallypipelinedsoc/core/ifu/bus.busfsm/BusCurrState[2]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe124]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe124]
-connect_debug_port u_ila_0/probe124 [get_nets [list wallypipelinedsoc/hart/ifu/SpillSupport.CurrState[0] ]]
+connect_debug_port u_ila_0/probe124 [get_nets [list wallypipelinedsoc/core/ifu/SpillSupport.CurrState[0] ]]
 
 
 create_debug_port u_ila_0 probe
 set_property port_width 3 [get_debug_ports u_ila_0/probe125]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe125]
-connect_debug_port u_ila_0/probe125 [get_nets [list {wallypipelinedsoc/hart/lsu/bus.busfsm/BusCurrState[0]} {wallypipelinedsoc/hart/lsu/bus.busfsm/BusCurrState[1]} {wallypipelinedsoc/hart/lsu/bus.busfsm/BusCurrState[2]} ]]
+connect_debug_port u_ila_0/probe125 [get_nets [list {wallypipelinedsoc/core/lsu/bus.busfsm/BusCurrState[0]} {wallypipelinedsoc/core/lsu/bus.busfsm/BusCurrState[1]} {wallypipelinedsoc/core/lsu/bus.busfsm/BusCurrState[2]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 3 [get_debug_ports u_ila_0/probe126]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe126]
-connect_debug_port u_ila_0/probe126 [get_nets [list {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM.interlockfsm/InterlockCurrState[0]} {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM.interlockfsm/InterlockCurrState[1]} {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM.interlockfsm/InterlockCurrState[2]} ]]
+connect_debug_port u_ila_0/probe126 [get_nets [list {wallypipelinedsoc/core/lsu/MEM_VIRTMEM.interlockfsm/InterlockCurrState[0]} {wallypipelinedsoc/core/lsu/MEM_VIRTMEM.interlockfsm/InterlockCurrState[1]} {wallypipelinedsoc/core/lsu/MEM_VIRTMEM.interlockfsm/InterlockCurrState[2]} ]]
 
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe127]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe127]
-connect_debug_port u_ila_0/probe127 [get_nets [list {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[0]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[1]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[2]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[3]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[4]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[5]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[6]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[7]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[8]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[9]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[10]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[11]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[12]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[13]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[14]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[15]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[16]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[17]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[18]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[19]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[20]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[21]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[22]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[23]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[24]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[25]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[26]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[27]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[28]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[29]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[30]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[31]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[32]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[33]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[34]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[35]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[36]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[37]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[38]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[39]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[40]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[41]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[42]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[43]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[44]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[45]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[46]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[47]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[48]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[49]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[50]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[51]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[52]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[53]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[54]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[55]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[56]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[57]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[58]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[59]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[60]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[61]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[62]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[63]} ]]
+connect_debug_port u_ila_0/probe127 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[63]} ]]
 
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe128]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe128]
-connect_debug_port u_ila_0/probe128 [get_nets [list {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[0]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[1]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[2]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[3]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[4]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[5]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[6]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[7]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[8]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[9]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[10]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[11]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[12]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[13]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[14]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[15]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[16]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[17]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[18]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[19]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[20]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[21]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[22]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[23]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[24]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[25]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[26]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[27]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[28]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[29]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[30]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[31]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[32]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[33]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[34]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[35]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[36]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[37]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[38]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[39]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[40]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[41]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[42]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[43]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[44]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[45]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[46]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[47]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[48]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[49]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[50]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[51]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[52]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[53]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[54]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[55]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[56]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[57]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[58]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[59]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[60]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[61]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[62]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[63]} ]]
+connect_debug_port u_ila_0/probe128 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[63]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe129]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe129]
-connect_debug_port u_ila_0/probe129 [get_nets [list {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[0]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[1]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[2]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[3]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[4]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[5]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[6]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[7]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[8]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[9]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[10]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[11]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[12]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[13]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[14]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[15]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[16]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[17]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[18]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[19]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[20]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[21]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[22]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[23]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[24]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[25]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[26]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[27]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[28]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[29]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[30]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[31]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[32]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[33]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[34]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[35]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[36]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[37]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[38]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[39]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[40]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[41]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[42]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[43]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[44]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[45]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[46]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[47]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[48]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[49]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[50]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[51]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[52]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[53]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[54]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[55]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[56]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[57]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[58]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[59]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[60]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[61]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[62]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[63]} ]]
+connect_debug_port u_ila_0/probe129 [get_nets [list {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[0]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[1]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[2]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[3]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[4]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[5]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[6]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[7]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[8]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[9]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[10]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[11]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[12]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[13]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[14]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[15]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[16]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[17]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[18]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[19]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[20]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[21]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[22]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[23]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[24]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[25]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[26]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[27]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[28]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[29]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[30]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[31]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[32]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[33]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[34]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[35]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[36]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[37]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[38]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[39]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[40]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[41]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[42]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[43]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[44]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[45]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[46]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[47]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[48]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[49]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[50]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[51]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[52]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[53]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[54]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[55]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[56]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[57]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[58]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[59]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[60]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[61]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[62]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[63]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe130]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe130]
-connect_debug_port u_ila_0/probe130 [get_nets [list wallypipelinedsoc/hart/ieu/dp/RegWriteW]]
+connect_debug_port u_ila_0/probe130 [get_nets [list wallypipelinedsoc/core/ieu/dp/RegWriteW]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe131]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe131]
-connect_debug_port u_ila_0/probe131 [get_nets [list {wallypipelinedsoc/hart/priv.priv/CSRWriteM} ]]
+connect_debug_port u_ila_0/probe131 [get_nets [list {wallypipelinedsoc/core/priv.priv/CSRWriteM} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 32 [get_debug_ports u_ila_0/probe132]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe132]
-connect_debug_port u_ila_0/probe132 [get_nets [list {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[0]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[1]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[2]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[3]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[4]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[5]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[6]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[7]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[8]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[9]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[10]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[11]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[12]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[13]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[14]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[15]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[16]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[17]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[18]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[19]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[20]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[21]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[22]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[23]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[24]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[25]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[26]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[27]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[28]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[29]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[30]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[31]} ]]
+connect_debug_port u_ila_0/probe132 [get_nets [list {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[0]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[1]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[2]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[3]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[4]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[5]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[6]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[7]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[8]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[9]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[10]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[11]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[12]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[13]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[14]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[15]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[16]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[17]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[18]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[19]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[20]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[21]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[22]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[23]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[24]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[25]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[26]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[27]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[28]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[29]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[30]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[31]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe133]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe133]
-connect_debug_port u_ila_0/probe133 [get_nets [list {wallypipelinedsoc/hart/ifu/PCNextF[0]} {wallypipelinedsoc/hart/ifu/PCNextF[1]} {wallypipelinedsoc/hart/ifu/PCNextF[2]} {wallypipelinedsoc/hart/ifu/PCNextF[3]} {wallypipelinedsoc/hart/ifu/PCNextF[4]} {wallypipelinedsoc/hart/ifu/PCNextF[5]} {wallypipelinedsoc/hart/ifu/PCNextF[6]} {wallypipelinedsoc/hart/ifu/PCNextF[7]} {wallypipelinedsoc/hart/ifu/PCNextF[8]} {wallypipelinedsoc/hart/ifu/PCNextF[9]} {wallypipelinedsoc/hart/ifu/PCNextF[10]} {wallypipelinedsoc/hart/ifu/PCNextF[11]} {wallypipelinedsoc/hart/ifu/PCNextF[12]} {wallypipelinedsoc/hart/ifu/PCNextF[13]} {wallypipelinedsoc/hart/ifu/PCNextF[14]} {wallypipelinedsoc/hart/ifu/PCNextF[15]} {wallypipelinedsoc/hart/ifu/PCNextF[16]} {wallypipelinedsoc/hart/ifu/PCNextF[17]} {wallypipelinedsoc/hart/ifu/PCNextF[18]} {wallypipelinedsoc/hart/ifu/PCNextF[19]} {wallypipelinedsoc/hart/ifu/PCNextF[20]} {wallypipelinedsoc/hart/ifu/PCNextF[21]} {wallypipelinedsoc/hart/ifu/PCNextF[22]} {wallypipelinedsoc/hart/ifu/PCNextF[23]} {wallypipelinedsoc/hart/ifu/PCNextF[24]} {wallypipelinedsoc/hart/ifu/PCNextF[25]} {wallypipelinedsoc/hart/ifu/PCNextF[26]} {wallypipelinedsoc/hart/ifu/PCNextF[27]} {wallypipelinedsoc/hart/ifu/PCNextF[28]} {wallypipelinedsoc/hart/ifu/PCNextF[29]} {wallypipelinedsoc/hart/ifu/PCNextF[30]} {wallypipelinedsoc/hart/ifu/PCNextF[31]} {wallypipelinedsoc/hart/ifu/PCNextF[32]} {wallypipelinedsoc/hart/ifu/PCNextF[33]} {wallypipelinedsoc/hart/ifu/PCNextF[34]} {wallypipelinedsoc/hart/ifu/PCNextF[35]} {wallypipelinedsoc/hart/ifu/PCNextF[36]} {wallypipelinedsoc/hart/ifu/PCNextF[37]} {wallypipelinedsoc/hart/ifu/PCNextF[38]} {wallypipelinedsoc/hart/ifu/PCNextF[39]} {wallypipelinedsoc/hart/ifu/PCNextF[40]} {wallypipelinedsoc/hart/ifu/PCNextF[41]} {wallypipelinedsoc/hart/ifu/PCNextF[42]} {wallypipelinedsoc/hart/ifu/PCNextF[43]} {wallypipelinedsoc/hart/ifu/PCNextF[44]} {wallypipelinedsoc/hart/ifu/PCNextF[45]} {wallypipelinedsoc/hart/ifu/PCNextF[46]} {wallypipelinedsoc/hart/ifu/PCNextF[47]} {wallypipelinedsoc/hart/ifu/PCNextF[48]} {wallypipelinedsoc/hart/ifu/PCNextF[49]} {wallypipelinedsoc/hart/ifu/PCNextF[50]} {wallypipelinedsoc/hart/ifu/PCNextF[51]} {wallypipelinedsoc/hart/ifu/PCNextF[52]} {wallypipelinedsoc/hart/ifu/PCNextF[53]} {wallypipelinedsoc/hart/ifu/PCNextF[54]} {wallypipelinedsoc/hart/ifu/PCNextF[55]} {wallypipelinedsoc/hart/ifu/PCNextF[56]} {wallypipelinedsoc/hart/ifu/PCNextF[57]} {wallypipelinedsoc/hart/ifu/PCNextF[58]} {wallypipelinedsoc/hart/ifu/PCNextF[59]} {wallypipelinedsoc/hart/ifu/PCNextF[60]} {wallypipelinedsoc/hart/ifu/PCNextF[61]} {wallypipelinedsoc/hart/ifu/PCNextF[62]} {wallypipelinedsoc/hart/ifu/PCNextF[63]}]]
-
+connect_debug_port u_ila_0/probe133 [get_nets [list {wallypipelinedsoc/core/ifu/PCNextF[0]} {wallypipelinedsoc/core/ifu/PCNextF[1]} {wallypipelinedsoc/core/ifu/PCNextF[2]} {wallypipelinedsoc/core/ifu/PCNextF[3]} {wallypipelinedsoc/core/ifu/PCNextF[4]} {wallypipelinedsoc/core/ifu/PCNextF[5]} {wallypipelinedsoc/core/ifu/PCNextF[6]} {wallypipelinedsoc/core/ifu/PCNextF[7]} {wallypipelinedsoc/core/ifu/PCNextF[8]} {wallypipelinedsoc/core/ifu/PCNextF[9]} {wallypipelinedsoc/core/ifu/PCNextF[10]} {wallypipelinedsoc/core/ifu/PCNextF[11]} {wallypipelinedsoc/core/ifu/PCNextF[12]} {wallypipelinedsoc/core/ifu/PCNextF[13]} {wallypipelinedsoc/core/ifu/PCNextF[14]} {wallypipelinedsoc/core/ifu/PCNextF[15]} {wallypipelinedsoc/core/ifu/PCNextF[16]} {wallypipelinedsoc/core/ifu/PCNextF[17]} {wallypipelinedsoc/core/ifu/PCNextF[18]} {wallypipelinedsoc/core/ifu/PCNextF[19]} {wallypipelinedsoc/core/ifu/PCNextF[20]} {wallypipelinedsoc/core/ifu/PCNextF[21]} {wallypipelinedsoc/core/ifu/PCNextF[22]} {wallypipelinedsoc/core/ifu/PCNextF[23]} {wallypipelinedsoc/core/ifu/PCNextF[24]} {wallypipelinedsoc/core/ifu/PCNextF[25]} {wallypipelinedsoc/core/ifu/PCNextF[26]} {wallypipelinedsoc/core/ifu/PCNextF[27]} {wallypipelinedsoc/core/ifu/PCNextF[28]} {wallypipelinedsoc/core/ifu/PCNextF[29]} {wallypipelinedsoc/core/ifu/PCNextF[30]} {wallypipelinedsoc/core/ifu/PCNextF[31]} {wallypipelinedsoc/core/ifu/PCNextF[32]} {wallypipelinedsoc/core/ifu/PCNextF[33]} {wallypipelinedsoc/core/ifu/PCNextF[34]} {wallypipelinedsoc/core/ifu/PCNextF[35]} {wallypipelinedsoc/core/ifu/PCNextF[36]} {wallypipelinedsoc/core/ifu/PCNextF[37]} {wallypipelinedsoc/core/ifu/PCNextF[38]} {wallypipelinedsoc/core/ifu/PCNextF[39]} {wallypipelinedsoc/core/ifu/PCNextF[40]} {wallypipelinedsoc/core/ifu/PCNextF[41]} {wallypipelinedsoc/core/ifu/PCNextF[42]} {wallypipelinedsoc/core/ifu/PCNextF[43]} {wallypipelinedsoc/core/ifu/PCNextF[44]} {wallypipelinedsoc/core/ifu/PCNextF[45]} {wallypipelinedsoc/core/ifu/PCNextF[46]} {wallypipelinedsoc/core/ifu/PCNextF[47]} {wallypipelinedsoc/core/ifu/PCNextF[48]} {wallypipelinedsoc/core/ifu/PCNextF[49]} {wallypipelinedsoc/core/ifu/PCNextF[50]} {wallypipelinedsoc/core/ifu/PCNextF[51]} {wallypipelinedsoc/core/ifu/PCNextF[52]} {wallypipelinedsoc/core/ifu/PCNextF[53]} {wallypipelinedsoc/core/ifu/PCNextF[54]} {wallypipelinedsoc/core/ifu/PCNextF[55]} {wallypipelinedsoc/core/ifu/PCNextF[56]} {wallypipelinedsoc/core/ifu/PCNextF[57]} {wallypipelinedsoc/core/ifu/PCNextF[58]} {wallypipelinedsoc/core/ifu/PCNextF[59]} {wallypipelinedsoc/core/ifu/PCNextF[60]} {wallypipelinedsoc/core/ifu/PCNextF[61]} {wallypipelinedsoc/core/ifu/PCNextF[62]} {wallypipelinedsoc/core/ifu/PCNextF[63]}]]

fpga/generator/dcache-miss-evict-dirty-deadlock.tsm

@@ -15,7 +15,7 @@
 #
 ##################################################
 state state_reset:
-    if(wallypipelinedsoc/hart/lsu.bus.dcache.dcache/cachefsm/CurrState == 32'h00000003) then
+    if(wallypipelinedsoc/core/lsu.bus.dcache.dcache/cachefsm/CurrState == 32'h00000003) then
         reset_counter $counter0;
         goto state_begin_count;
         #goto state_trigger;
@@ -26,7 +26,7 @@ state state_reset:
 state state_begin_count:
     if($counter0 == 16'h0164) then
         goto state_trigger;
-    elseif(wallypipelinedsoc/hart/lsu.bus.dcache.dcache/cachefsm/CurrState == 32'h00000003) then
+    elseif(wallypipelinedsoc/core/lsu.bus.dcache.dcache/cachefsm/CurrState == 32'h00000003) then
         increment_counter $counter0;
         goto state_begin_count;
     else

fpga/generator/trigger.tsm

@@ -15,7 +15,7 @@
 #
 ##################################################
 state state_reset:
-    if(wallypipelinedsoc/hart/lsu.bus.dcache/dcachefsm/CurrState == 32'h00000015) then
+    if(wallypipelinedsoc/core/lsu.bus.dcache/dcachefsm/CurrState == 32'h00000015) then
         reset_counter $counter0;
         goto state_begin_count;
     else
@@ -25,7 +25,7 @@ state state_reset:
 state state_begin_count:
     if($counter0 == 16'h0064) then
         goto state_trigger;
-    elseif(wallypipelinedsoc/hart/lsu.bus.dcache/dcachefsm/CurrState == 32'h00000015) then
+    elseif(wallypipelinedsoc/core/lsu.bus.dcache/dcachefsm/CurrState == 32'h00000015) then
         increment_counter $counter0;
         goto state_begin_count;
     else

fpga/trigger_issues.tsm

@@ -15,7 +15,7 @@
 #
 ##################################################
 state state_reset:
-    if(wallypipelinedsoc/hart/lsu.bus.dcache/dcachefsm/CurrState == 32'h00000015) then
+    if(wallypipelinedsoc/core/lsu.bus.dcache/dcachefsm/CurrState == 32'h00000015) then
         reset_counter $counter0;
         goto state_begin_count;
     else
@@ -25,7 +25,7 @@ state state_reset:
 state state_begin_count:
     if($counter0 == 16'h0064) then
         goto state_trigger;
-    elseif(wallypipelinedsoc/hart/lsu.bus.dcache/dcachefsm/CurrState == 32'h00000015) then
+    elseif(wallypipelinedsoc/core/lsu.bus.dcache/dcachefsm/CurrState == 32'h00000015) then
         increment_counter $counter0;
         goto state_begin_count;
     else

pipelined/regression/Makefile

@@ -5,11 +5,12 @@ make allclean:
 make clean:
 	make clean -C ../../addins/riscv-arch-test
 	make clean -C ../../tests/wally-riscv-arch-test
+	make allclean -C ../../tests/imperas-riscv-tests
 
 make all:
 	# *** Build old tests/imperas-riscv-tests for now;
 	# Delete this part when the privileged tests transition over to tests/wally-riscv-arch-test
-	# Also delete exe2memfile at that point
+	# Also delete bin/exe2memfile at that point
 	make -C ../../tests/imperas-riscv-tests
 	make -C ../../tests/imperas-riscv-tests XLEN=64
 	cd ../../tests/imperas-riscv-tests; exe2memfile.pl work/*/*.elf

pipelined/regression/fpga-wave.do

@@ -4,440 +4,440 @@ add wave -noupdate /testbench/clk
 add wave -noupdate /testbench/reset
 add wave -noupdate /testbench/test
 add wave -noupdate /testbench/memfilename
-add wave -noupdate /testbench/dut/wallypipelinedsoc/hart/SATP_REGW
-add wave -noupdate -expand -group {Execution Stage} /testbench/dut/wallypipelinedsoc/hart/ifu/PCE
+add wave -noupdate /testbench/dut/wallypipelinedsoc/core/SATP_REGW
+add wave -noupdate -expand -group {Execution Stage} /testbench/dut/wallypipelinedsoc/core/ifu/PCE
 add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
-add wave -noupdate -expand -group {Execution Stage} /testbench/dut/wallypipelinedsoc/hart/ifu/InstrE
-add wave -noupdate -expand -group {Memory Stage} /testbench/dut/wallypipelinedsoc/hart/priv/trap/InstrValidM
-add wave -noupdate -expand -group {Memory Stage} /testbench/dut/wallypipelinedsoc/hart/PCM
+add wave -noupdate -expand -group {Execution Stage} /testbench/dut/wallypipelinedsoc/core/ifu/InstrE
+add wave -noupdate -expand -group {Memory Stage} /testbench/dut/wallypipelinedsoc/core/priv/trap/InstrValidM
+add wave -noupdate -expand -group {Memory Stage} /testbench/dut/wallypipelinedsoc/core/PCM
 add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName
-add wave -noupdate -expand -group {Memory Stage} /testbench/dut/wallypipelinedsoc/hart/InstrM
-add wave -noupdate -expand -group {Memory Stage} /testbench/dut/wallypipelinedsoc/hart/lsu/MemAdrM
-add wave -noupdate /testbench/dut/wallypipelinedsoc/hart/ieu/dp/ResultM
-add wave -noupdate /testbench/dut/wallypipelinedsoc/hart/ieu/dp/ResultW
-add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/hart/priv/trap/InstrMisalignedFaultM
-add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/hart/priv/trap/InstrAccessFaultM
-add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/hart/priv/trap/IllegalInstrFaultM
-add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/hart/priv/trap/BreakpointFaultM
-add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/hart/priv/trap/LoadMisalignedFaultM
-add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/hart/priv/trap/StoreMisalignedFaultM
-add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/hart/priv/trap/LoadAccessFaultM
-add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/hart/priv/trap/StoreAccessFaultM
-add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/hart/priv/trap/EcallFaultM
-add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/hart/priv/trap/InstrPageFaultM
-add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/hart/priv/trap/LoadPageFaultM
-add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/hart/priv/trap/StorePageFaultM
-add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/hart/priv/trap/InterruptM
-add wave -noupdate -group HDU -group interrupts /testbench/dut/wallypipelinedsoc/hart/priv/trap/PendingIntsM
-add wave -noupdate -group HDU -group interrupts /testbench/dut/wallypipelinedsoc/hart/priv/trap/CommittedM
-add wave -noupdate -group HDU -group interrupts /testbench/dut/wallypipelinedsoc/hart/priv/trap/InstrValidM
-add wave -noupdate -group HDU -group hazards /testbench/dut/wallypipelinedsoc/hart/hzu/BPPredWrongE
-add wave -noupdate -group HDU -group hazards /testbench/dut/wallypipelinedsoc/hart/hzu/CSRWritePendingDEM
-add wave -noupdate -group HDU -group hazards /testbench/dut/wallypipelinedsoc/hart/hzu/RetM
-add wave -noupdate -group HDU -group hazards /testbench/dut/wallypipelinedsoc/hart/hzu/TrapM
-add wave -noupdate -group HDU -group hazards /testbench/dut/wallypipelinedsoc/hart/hzu/LoadStallD
-add wave -noupdate -group HDU -group hazards /testbench/dut/wallypipelinedsoc/hart/hzu/StoreStallD
-add wave -noupdate -group HDU -group hazards /testbench/dut/wallypipelinedsoc/hart/hzu/ICacheStallF
-add wave -noupdate -group HDU -group hazards /testbench/dut/wallypipelinedsoc/hart/hzu/LSUStallM
-add wave -noupdate -group HDU -group hazards /testbench/dut/wallypipelinedsoc/hart/MulDivStallD
-add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/wallypipelinedsoc/hart/hzu/FlushF
-add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/wallypipelinedsoc/hart/FlushD
-add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/wallypipelinedsoc/hart/FlushE
-add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/wallypipelinedsoc/hart/FlushM
-add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/wallypipelinedsoc/hart/FlushW
-add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/wallypipelinedsoc/hart/StallF
-add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/wallypipelinedsoc/hart/StallD
-add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/wallypipelinedsoc/hart/StallE
-add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/wallypipelinedsoc/hart/StallM
-add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/wallypipelinedsoc/hart/StallW
-add wave -noupdate -group Bpred -color Orange /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR
-add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF
-add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]}
-add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPInstrClassE[0]}
-add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredDirWrongE
+add wave -noupdate -expand -group {Memory Stage} /testbench/dut/wallypipelinedsoc/core/InstrM
+add wave -noupdate -expand -group {Memory Stage} /testbench/dut/wallypipelinedsoc/core/lsu/MemAdrM
+add wave -noupdate /testbench/dut/wallypipelinedsoc/core/ieu/dp/ResultM
+add wave -noupdate /testbench/dut/wallypipelinedsoc/core/ieu/dp/ResultW
+add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/core/priv/trap/InstrMisalignedFaultM
+add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/core/priv/trap/InstrAccessFaultM
+add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/core/priv/trap/IllegalInstrFaultM
+add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/core/priv/trap/BreakpointFaultM
+add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/core/priv/trap/LoadMisalignedFaultM
+add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/core/priv/trap/StoreMisalignedFaultM
+add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/core/priv/trap/LoadAccessFaultM
+add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/core/priv/trap/StoreAccessFaultM
+add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/core/priv/trap/EcallFaultM
+add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/core/priv/trap/InstrPageFaultM
+add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/core/priv/trap/LoadPageFaultM
+add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/core/priv/trap/StorePageFaultM
+add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/core/priv/trap/InterruptM
+add wave -noupdate -group HDU -group interrupts /testbench/dut/wallypipelinedsoc/core/priv/trap/PendingIntsM
+add wave -noupdate -group HDU -group interrupts /testbench/dut/wallypipelinedsoc/core/priv/trap/CommittedM
+add wave -noupdate -group HDU -group interrupts /testbench/dut/wallypipelinedsoc/core/priv/trap/InstrValidM
+add wave -noupdate -group HDU -group hazards /testbench/dut/wallypipelinedsoc/core/hzu/BPPredWrongE
+add wave -noupdate -group HDU -group hazards /testbench/dut/wallypipelinedsoc/core/hzu/CSRWritePendingDEM
+add wave -noupdate -group HDU -group hazards /testbench/dut/wallypipelinedsoc/core/hzu/RetM
+add wave -noupdate -group HDU -group hazards /testbench/dut/wallypipelinedsoc/core/hzu/TrapM
+add wave -noupdate -group HDU -group hazards /testbench/dut/wallypipelinedsoc/core/hzu/LoadStallD
+add wave -noupdate -group HDU -group hazards /testbench/dut/wallypipelinedsoc/core/hzu/StoreStallD
+add wave -noupdate -group HDU -group hazards /testbench/dut/wallypipelinedsoc/core/hzu/ICacheStallF
+add wave -noupdate -group HDU -group hazards /testbench/dut/wallypipelinedsoc/core/hzu/LSUStallM
+add wave -noupdate -group HDU -group hazards /testbench/dut/wallypipelinedsoc/core/MulDivStallD
+add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/wallypipelinedsoc/core/hzu/FlushF
+add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/wallypipelinedsoc/core/FlushD
+add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/wallypipelinedsoc/core/FlushE
+add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/wallypipelinedsoc/core/FlushM
+add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/wallypipelinedsoc/core/FlushW
+add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/wallypipelinedsoc/core/StallF
+add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/wallypipelinedsoc/core/StallD
+add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/wallypipelinedsoc/core/StallE
+add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/wallypipelinedsoc/core/StallM
+add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/wallypipelinedsoc/core/StallW
+add wave -noupdate -group Bpred -color Orange /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/GHR
+add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF
+add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]}
+add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/BPInstrClassE[0]}
+add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/BPPredDirWrongE
 add wave -noupdate -group Bpred -expand -group {branch update selection inputs} -divider {class check}
-add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightNonCFI
-add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassWrongCFI
-add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassWrongNonCFI
-add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPRight
-add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPWrong
-add wave -noupdate -group Bpred -radix hexadecimal -childformat {{{/testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} -radix binary} {{/testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} -radix binary} {{/testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} -radix binary} {{/testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} -radix binary} {{/testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} -radix binary} {{/testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} -radix binary} {{/testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} -radix binary}} -subitemconfig {{/testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} {-height 16 -radix binary} {/testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} {-height 16 -radix binary} {/testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} {-height 16 -radix binary} {/testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} {-height 16 -radix binary} {/testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} {-height 16 -radix binary} {/testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} {-height 16 -radix binary} {/testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} {-height 16 -radix binary}} /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel
-add wave -noupdate -group Bpred /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRNext
-add wave -noupdate -group Bpred /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRUpdateEN
-add wave -noupdate -group Bpred /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr
-add wave -noupdate -group Bpred /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr0
-add wave -noupdate -group Bpred /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr1
-add wave -noupdate -group Bpred /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateEN
-add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRLookup
-add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/PCNextF
-add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/PHT/RA1
-add wave -noupdate -group Bpred -expand -group prediction -radix binary /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/BPPredF
-add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/BTBValidF
-add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/BPInstrClassF
-add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/BTBPredPCF
-add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/RASPCF
-add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/TargetPredictor/LookUpPCIndex
-add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/TargetPredictor/TargetPC
-add wave -noupdate -group Bpred -expand -group prediction -expand -group ex -radix binary /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/BPPredE
-add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/PCSrcE
-add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/BPPredDirWrongE
-add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/TargetPredictor/UpdatePCIndex
-add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/TargetPredictor/UpdateTarget
-add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/TargetPredictor/UpdateEN
-add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/TargetPredictor/UpdatePC
-add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/TargetPredictor/UpdateTarget
-add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr
-add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/PCE
-add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/PHT/WA1
-add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/TargetWrongE
-add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/FallThroughWrongE
-add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/PredictionPCWrongE
-add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/InstrClassE
-add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/PredictionInstrClassWrongE
-add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/BPPredClassNonCFIWrongE
-add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/BPPredWrongE
-add wave -noupdate -group Bpred /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/BPPredWrongE
+add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightNonCFI
+add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassWrongCFI
+add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassWrongNonCFI
+add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPRight
+add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPWrong
+add wave -noupdate -group Bpred -radix hexadecimal -childformat {{{/testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} -radix binary} {{/testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} -radix binary} {{/testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} -radix binary} {{/testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} -radix binary} {{/testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} -radix binary} {{/testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} -radix binary} {{/testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} -radix binary}} -subitemconfig {{/testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} {-height 16 -radix binary} {/testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} {-height 16 -radix binary} {/testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} {-height 16 -radix binary} {/testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} {-height 16 -radix binary} {/testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} {-height 16 -radix binary} {/testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} {-height 16 -radix binary} {/testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} {-height 16 -radix binary}} /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel
+add wave -noupdate -group Bpred /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNext
+add wave -noupdate -group Bpred /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRUpdateEN
+add wave -noupdate -group Bpred /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr
+add wave -noupdate -group Bpred /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr0
+add wave -noupdate -group Bpred /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr1
+add wave -noupdate -group Bpred /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateEN
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRLookup
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/PCNextF
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/PHT/RA1
+add wave -noupdate -group Bpred -expand -group prediction -radix binary /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/BPPredF
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/BTBValidF
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/BPInstrClassF
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/BTBPredPCF
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/RASPCF
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/TargetPredictor/LookUpPCIndex
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/TargetPredictor/TargetPC
+add wave -noupdate -group Bpred -expand -group prediction -expand -group ex -radix binary /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/BPPredE
+add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/PCSrcE
+add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/BPPredDirWrongE
+add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/TargetPredictor/UpdatePCIndex
+add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/TargetPredictor/UpdateTarget
+add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/TargetPredictor/UpdateEN
+add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/TargetPredictor/UpdatePC
+add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/TargetPredictor/UpdateTarget
+add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr
+add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/PCE
+add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/PHT/WA1
+add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/TargetWrongE
+add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/FallThroughWrongE
+add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/PredictionPCWrongE
+add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/InstrClassE
+add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/PredictionInstrClassWrongE
+add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/BPPredClassNonCFIWrongE
+add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/BPPredWrongE
+add wave -noupdate -group Bpred /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/BPPredWrongE
 add wave -noupdate -group {instruction pipeline} /testbench/InstrFName
-add wave -noupdate -group {instruction pipeline} /testbench/dut/wallypipelinedsoc/hart/ifu/icache/FinalInstrRawF
-add wave -noupdate -group {instruction pipeline} /testbench/dut/wallypipelinedsoc/hart/ifu/InstrD
-add wave -noupdate -group {instruction pipeline} /testbench/dut/wallypipelinedsoc/hart/ifu/InstrE
-add wave -noupdate -group {instruction pipeline} /testbench/dut/wallypipelinedsoc/hart/ifu/InstrM
+add wave -noupdate -group {instruction pipeline} /testbench/dut/wallypipelinedsoc/core/ifu/icache/FinalInstrRawF
+add wave -noupdate -group {instruction pipeline} /testbench/dut/wallypipelinedsoc/core/ifu/InstrD
+add wave -noupdate -group {instruction pipeline} /testbench/dut/wallypipelinedsoc/core/ifu/InstrE
+add wave -noupdate -group {instruction pipeline} /testbench/dut/wallypipelinedsoc/core/ifu/InstrM
 add wave -noupdate -group {instruction pipeline} /testbench/InstrW
-add wave -noupdate -group {PCNext Generation} /testbench/dut/wallypipelinedsoc/hart/ifu/PCNextF
-add wave -noupdate -group {PCNext Generation} /testbench/dut/wallypipelinedsoc/hart/ifu/PCF
-add wave -noupdate -group {PCNext Generation} /testbench/dut/wallypipelinedsoc/hart/ifu/PCPlus2or4F
-add wave -noupdate -group {PCNext Generation} /testbench/dut/wallypipelinedsoc/hart/ifu/BPPredPCF
-add wave -noupdate -group {PCNext Generation} /testbench/dut/wallypipelinedsoc/hart/ifu/PCNext0F
-add wave -noupdate -group {PCNext Generation} /testbench/dut/wallypipelinedsoc/hart/ifu/PCNext1F
-add wave -noupdate -group {PCNext Generation} /testbench/dut/wallypipelinedsoc/hart/ifu/SelBPPredF
-add wave -noupdate -group {PCNext Generation} /testbench/dut/wallypipelinedsoc/hart/ifu/BPPredWrongE
-add wave -noupdate -group {PCNext Generation} /testbench/dut/wallypipelinedsoc/hart/ifu/PrivilegedChangePCM
-add wave -noupdate -group {Decode Stage} /testbench/dut/wallypipelinedsoc/hart/ifu/InstrD
+add wave -noupdate -group {PCNext Generation} /testbench/dut/wallypipelinedsoc/core/ifu/PCNextF
+add wave -noupdate -group {PCNext Generation} /testbench/dut/wallypipelinedsoc/core/ifu/PCF
+add wave -noupdate -group {PCNext Generation} /testbench/dut/wallypipelinedsoc/core/ifu/PCPlus2or4F
+add wave -noupdate -group {PCNext Generation} /testbench/dut/wallypipelinedsoc/core/ifu/BPPredPCF
+add wave -noupdate -group {PCNext Generation} /testbench/dut/wallypipelinedsoc/core/ifu/PCNext0F
+add wave -noupdate -group {PCNext Generation} /testbench/dut/wallypipelinedsoc/core/ifu/PCNext1F
+add wave -noupdate -group {PCNext Generation} /testbench/dut/wallypipelinedsoc/core/ifu/SelBPPredF
+add wave -noupdate -group {PCNext Generation} /testbench/dut/wallypipelinedsoc/core/ifu/BPPredWrongE
+add wave -noupdate -group {PCNext Generation} /testbench/dut/wallypipelinedsoc/core/ifu/PrivilegedChangePCM
+add wave -noupdate -group {Decode Stage} /testbench/dut/wallypipelinedsoc/core/ifu/InstrD
 add wave -noupdate -group {Decode Stage} /testbench/InstrDName
-add wave -noupdate -group {Decode Stage} /testbench/dut/wallypipelinedsoc/hart/ieu/c/RegWriteD
-add wave -noupdate -group {Decode Stage} /testbench/dut/wallypipelinedsoc/hart/ieu/dp/RdD
-add wave -noupdate -group {Decode Stage} /testbench/dut/wallypipelinedsoc/hart/ieu/dp/Rs1D
-add wave -noupdate -group {Decode Stage} /testbench/dut/wallypipelinedsoc/hart/ieu/dp/Rs2D
-add wave -noupdate -group RegFile -expand /testbench/dut/wallypipelinedsoc/hart/ieu/dp/regf/rf
-add wave -noupdate -group RegFile /testbench/dut/wallypipelinedsoc/hart/ieu/dp/regf/a1
-add wave -noupdate -group RegFile /testbench/dut/wallypipelinedsoc/hart/ieu/dp/regf/a2
-add wave -noupdate -group RegFile /testbench/dut/wallypipelinedsoc/hart/ieu/dp/regf/a3
-add wave -noupdate -group RegFile /testbench/dut/wallypipelinedsoc/hart/ieu/dp/regf/rd1
-add wave -noupdate -group RegFile /testbench/dut/wallypipelinedsoc/hart/ieu/dp/regf/rd2
-add wave -noupdate -group RegFile /testbench/dut/wallypipelinedsoc/hart/ieu/dp/regf/we3
-add wave -noupdate -group RegFile /testbench/dut/wallypipelinedsoc/hart/ieu/dp/regf/wd3
-add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/wallypipelinedsoc/hart/ieu/dp/IntResultW
-add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/wallypipelinedsoc/hart/ieu/dp/ReadDataW
-add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/wallypipelinedsoc/hart/ieu/dp/CSRReadValW
-add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/wallypipelinedsoc/hart/ieu/dp/ResultSrcW
-add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/wallypipelinedsoc/hart/ieu/dp/ResultW
-add wave -noupdate -group alu /testbench/dut/wallypipelinedsoc/hart/ieu/dp/alu/A
-add wave -noupdate -group alu /testbench/dut/wallypipelinedsoc/hart/ieu/dp/alu/B
-add wave -noupdate -group alu /testbench/dut/wallypipelinedsoc/hart/ieu/dp/alu/ALUControl
-add wave -noupdate -group alu /testbench/dut/wallypipelinedsoc/hart/ieu/dp/alu/result
-add wave -noupdate -group alu /testbench/dut/wallypipelinedsoc/hart/ieu/dp/alu/FlagsEEEEE
+add wave -noupdate -group {Decode Stage} /testbench/dut/wallypipelinedsoc/core/ieu/c/RegWriteD
+add wave -noupdate -group {Decode Stage} /testbench/dut/wallypipelinedsoc/core/ieu/dp/RdD
+add wave -noupdate -group {Decode Stage} /testbench/dut/wallypipelinedsoc/core/ieu/dp/Rs1D
+add wave -noupdate -group {Decode Stage} /testbench/dut/wallypipelinedsoc/core/ieu/dp/Rs2D
+add wave -noupdate -group RegFile -expand /testbench/dut/wallypipelinedsoc/core/ieu/dp/regf/rf
+add wave -noupdate -group RegFile /testbench/dut/wallypipelinedsoc/core/ieu/dp/regf/a1
+add wave -noupdate -group RegFile /testbench/dut/wallypipelinedsoc/core/ieu/dp/regf/a2
+add wave -noupdate -group RegFile /testbench/dut/wallypipelinedsoc/core/ieu/dp/regf/a3
+add wave -noupdate -group RegFile /testbench/dut/wallypipelinedsoc/core/ieu/dp/regf/rd1
+add wave -noupdate -group RegFile /testbench/dut/wallypipelinedsoc/core/ieu/dp/regf/rd2
+add wave -noupdate -group RegFile /testbench/dut/wallypipelinedsoc/core/ieu/dp/regf/we3
+add wave -noupdate -group RegFile /testbench/dut/wallypipelinedsoc/core/ieu/dp/regf/wd3
+add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/wallypipelinedsoc/core/ieu/dp/IntResultW
+add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/wallypipelinedsoc/core/ieu/dp/ReadDataW
+add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/wallypipelinedsoc/core/ieu/dp/CSRReadValW
+add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/wallypipelinedsoc/core/ieu/dp/ResultSrcW
+add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/wallypipelinedsoc/core/ieu/dp/ResultW
+add wave -noupdate -group alu /testbench/dut/wallypipelinedsoc/core/ieu/dp/alu/A
+add wave -noupdate -group alu /testbench/dut/wallypipelinedsoc/core/ieu/dp/alu/B
+add wave -noupdate -group alu /testbench/dut/wallypipelinedsoc/core/ieu/dp/alu/ALUControl
+add wave -noupdate -group alu /testbench/dut/wallypipelinedsoc/core/ieu/dp/alu/result
+add wave -noupdate -group alu /testbench/dut/wallypipelinedsoc/core/ieu/dp/alu/FlagsEEEEE
 add wave -noupdate -group alu -divider internals
-add wave -noupdate -group Forward /testbench/dut/wallypipelinedsoc/hart/ieu/fw/Rs1D
-add wave -noupdate -group Forward /testbench/dut/wallypipelinedsoc/hart/ieu/fw/Rs2D
-add wave -noupdate -group Forward /testbench/dut/wallypipelinedsoc/hart/ieu/fw/Rs1E
-add wave -noupdate -group Forward /testbench/dut/wallypipelinedsoc/hart/ieu/fw/Rs2E
-add wave -noupdate -group Forward /testbench/dut/wallypipelinedsoc/hart/ieu/fw/RdE
-add wave -noupdate -group Forward /testbench/dut/wallypipelinedsoc/hart/ieu/fw/RdM
-add wave -noupdate -group Forward /testbench/dut/wallypipelinedsoc/hart/ieu/fw/RdW
-add wave -noupdate -group Forward /testbench/dut/wallypipelinedsoc/hart/ieu/fw/MemReadE
-add wave -noupdate -group Forward /testbench/dut/wallypipelinedsoc/hart/ieu/fw/RegWriteM
-add wave -noupdate -group Forward /testbench/dut/wallypipelinedsoc/hart/ieu/fw/RegWriteW
-add wave -noupdate -group Forward -color Thistle /testbench/dut/wallypipelinedsoc/hart/ieu/fw/ForwardAE
-add wave -noupdate -group Forward -color Thistle /testbench/dut/wallypipelinedsoc/hart/ieu/fw/ForwardBE
-add wave -noupdate -group Forward -color Thistle /testbench/dut/wallypipelinedsoc/hart/ieu/fw/LoadStallD
-add wave -noupdate -group {alu execution stage} /testbench/dut/wallypipelinedsoc/hart/ieu/dp/WriteDataE
-add wave -noupdate -group {alu execution stage} /testbench/dut/wallypipelinedsoc/hart/ieu/dp/ALUResultE
-add wave -noupdate -group {alu execution stage} /testbench/dut/wallypipelinedsoc/hart/ieu/dp/SrcAE
-add wave -noupdate -group {alu execution stage} /testbench/dut/wallypipelinedsoc/hart/ieu/dp/SrcBE
-add wave -noupdate -group PCS /testbench/dut/wallypipelinedsoc/hart/ifu/PCNextF
-add wave -noupdate -group PCS /testbench/dut/wallypipelinedsoc/hart/PCF
-add wave -noupdate -group PCS /testbench/dut/wallypipelinedsoc/hart/ifu/PCD
-add wave -noupdate -group PCS /testbench/dut/wallypipelinedsoc/hart/PCE
-add wave -noupdate -group PCS /testbench/dut/wallypipelinedsoc/hart/PCM
+add wave -noupdate -group Forward /testbench/dut/wallypipelinedsoc/core/ieu/fw/Rs1D
+add wave -noupdate -group Forward /testbench/dut/wallypipelinedsoc/core/ieu/fw/Rs2D
+add wave -noupdate -group Forward /testbench/dut/wallypipelinedsoc/core/ieu/fw/Rs1E
+add wave -noupdate -group Forward /testbench/dut/wallypipelinedsoc/core/ieu/fw/Rs2E
+add wave -noupdate -group Forward /testbench/dut/wallypipelinedsoc/core/ieu/fw/RdE
+add wave -noupdate -group Forward /testbench/dut/wallypipelinedsoc/core/ieu/fw/RdM
+add wave -noupdate -group Forward /testbench/dut/wallypipelinedsoc/core/ieu/fw/RdW
+add wave -noupdate -group Forward /testbench/dut/wallypipelinedsoc/core/ieu/fw/MemReadE
+add wave -noupdate -group Forward /testbench/dut/wallypipelinedsoc/core/ieu/fw/RegWriteM
+add wave -noupdate -group Forward /testbench/dut/wallypipelinedsoc/core/ieu/fw/RegWriteW
+add wave -noupdate -group Forward -color Thistle /testbench/dut/wallypipelinedsoc/core/ieu/fw/ForwardAE
+add wave -noupdate -group Forward -color Thistle /testbench/dut/wallypipelinedsoc/core/ieu/fw/ForwardBE
+add wave -noupdate -group Forward -color Thistle /testbench/dut/wallypipelinedsoc/core/ieu/fw/LoadStallD
+add wave -noupdate -group {alu execution stage} /testbench/dut/wallypipelinedsoc/core/ieu/dp/WriteDataE
+add wave -noupdate -group {alu execution stage} /testbench/dut/wallypipelinedsoc/core/ieu/dp/ALUResultE
+add wave -noupdate -group {alu execution stage} /testbench/dut/wallypipelinedsoc/core/ieu/dp/SrcAE
+add wave -noupdate -group {alu execution stage} /testbench/dut/wallypipelinedsoc/core/ieu/dp/SrcBE
+add wave -noupdate -group PCS /testbench/dut/wallypipelinedsoc/core/ifu/PCNextF
+add wave -noupdate -group PCS /testbench/dut/wallypipelinedsoc/core/PCF
+add wave -noupdate -group PCS /testbench/dut/wallypipelinedsoc/core/ifu/PCD
+add wave -noupdate -group PCS /testbench/dut/wallypipelinedsoc/core/PCE
+add wave -noupdate -group PCS /testbench/dut/wallypipelinedsoc/core/PCM
 add wave -noupdate -group PCS /testbench/PCW
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-add wave -noupdate -group muldiv /testbench/dut/wallypipelinedsoc/hart/mdu/ForwardedSrcBE
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-add wave -noupdate -group muldiv /testbench/dut/wallypipelinedsoc/hart/mdu/StallM
-add wave -noupdate -group muldiv /testbench/dut/wallypipelinedsoc/hart/mdu/StallW
-add wave -noupdate -group muldiv /testbench/dut/wallypipelinedsoc/hart/mdu/FlushM
-add wave -noupdate -group muldiv /testbench/dut/wallypipelinedsoc/hart/mdu/FlushW
-add wave -noupdate -group muldiv /testbench/dut/wallypipelinedsoc/hart/mdu/MulDivResultW
-add wave -noupdate -group muldiv /testbench/dut/wallypipelinedsoc/hart/mdu/DivBusyE
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-add wave -noupdate -group icache /testbench/dut/wallypipelinedsoc/hart/ifu/icache/BasePAdrF
-add wave -noupdate -group icache /testbench/dut/wallypipelinedsoc/hart/ifu/icache/WayHit
-add wave -noupdate -group icache /testbench/dut/wallypipelinedsoc/hart/ifu/icache/genblk1/cachereplacementpolicy/BlockReplacementBits
-add wave -noupdate -group icache /testbench/dut/wallypipelinedsoc/hart/ifu/icache/genblk1/cachereplacementpolicy/EncVicWay
-add wave -noupdate -group icache /testbench/dut/wallypipelinedsoc/hart/ifu/icache/VictimWay
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[0]/WriteEnable}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[0]/SetValid}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[0]/CacheTagMem/StoredData}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[0]/ValidBits}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[0]/word[0]/CacheDataMem/StoredData}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[0]/word[1]/CacheDataMem/StoredData}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word2 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word2 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[0]/word[2]/CacheDataMem/StoredData}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[0]/word[3]/CacheDataMem/StoredData}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[1]/WriteEnable}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[1]/WriteWordEnable}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[1]/CacheTagMem/StoredData}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[1]/ValidBits}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[1]/word[0]/CacheDataMem/StoredData}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[1]/word[1]/CacheDataMem/StoredData}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[1]/word[2]/CacheDataMem/StoredData}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[1]/word[3]/CacheDataMem/StoredData}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[2]/WriteEnable}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[2]/SetValid}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[2]/CacheTagMem/StoredData}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[2]/ValidBits}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[2]/word[0]/CacheDataMem/StoredData}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[2]/word[1]/CacheDataMem/StoredData}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[2]/word[2]/CacheDataMem/StoredData}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[2]/word[3]/CacheDataMem/StoredData}
-add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[3]/WriteEnable}
-add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[3]/SetValid}
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-add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[3]/ValidBits}
-add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[3]/word[0]/CacheDataMem/StoredData}
-add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
-add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[3]/word[1]/CacheDataMem/StoredData}
-add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
-add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
-add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[3]/word[2]/CacheDataMem/StoredData}
-add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
-add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/wallypipelinedsoc/hart/ifu/icache/MemWay[3]/word[3]/CacheDataMem/StoredData}
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-add wave -noupdate -group icache /testbench/dut/wallypipelinedsoc/hart/ifu/icache/ITLBWriteF
-add wave -noupdate -group icache /testbench/dut/wallypipelinedsoc/hart/ifu/icache/ReadLineF
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-add wave -noupdate -group icache -expand -group memory /testbench/dut/wallypipelinedsoc/hart/ifu/icache/FetchCount
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-add wave -noupdate -group AHB /testbench/dut/wallypipelinedsoc/hart/ebu/HREADY
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-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[0]/word[2]/CacheDataMem/StoredData}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[0]/word[3]/CacheDataMem/StoredData}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[1]/DirtyBits}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[1]/SetDirty}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[1]/WriteEnable}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[1]/WriteWordEnable}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[1]/CacheTagMem/StoredData}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[1]/word[0]/CacheDataMem/StoredData}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[1]/word[1]/CacheDataMem/StoredData}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[1]/word[2]/CacheDataMem/StoredData}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[1]/word[3]/CacheDataMem/StoredData}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[2]/WriteEnable}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[2]/SetValid}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[2]/SetDirty}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[2]/CacheTagMem/StoredData}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[2]/DirtyBits}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[2]/ValidBits}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[2]/word[0]/CacheDataMem/StoredData}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[2]/word[1]/CacheDataMem/StoredData}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[2]/word[2]/CacheDataMem/StoredData}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[2]/word[3]/CacheDataMem/StoredData}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[3]/WriteEnable}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[3]/SetValid}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[3]/SetDirty}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[3]/CacheTagMem/StoredData}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[3]/DirtyBits}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[3]/ValidBits}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[3]/word[0]/CacheDataMem/StoredData}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[3]/word[1]/CacheDataMem/StoredData}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[3]/word[2]/CacheDataMem/StoredData}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[3]/word[3]/CacheDataMem/StoredData}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/SetValid
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/ClearValid
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/SetDirty
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/ClearDirty
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[0]/WayHit}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[0]/Valid}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[0]/Dirty}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[0]/ReadTag}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[1]/WayHit}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[1]/Valid}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[1]/Dirty}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[1]/ReadTag}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[2]/WayHit}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[2]/Valid}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[2]/Dirty}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[2]/ReadTag}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[3]/WayHit}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[3]/Valid}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[3]/Dirty}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemWay[3]/ReadTag}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/WayHit
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/ReadDataBlockWayMaskedM
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/ReadDataWordM
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/ReadDataWordMuxM
-add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/VictimTag
-add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/VictimWay
-add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/VictimDirtyWay
-add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/VictimDirty
-add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemRWM
-add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemAdrE
-add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemPAdrM
-add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/Funct3M
-add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/Funct7M
-add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/AtomicM
-add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/FlushDCacheM
-add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/CacheableM
-add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/WriteDataM
-add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/ReadDataM
-add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/DCacheStallM
-add wave -noupdate -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/FlushAdrFlag
-add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/WayHit
-add wave -noupdate -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/CacheHit
-add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/FetchCount
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/FetchCountFlag
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/AHBPAdr
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/AHBRead
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/AHBWrite
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/AHBAck
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/HRDATA
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/HWDATA
-add wave -noupdate -group lsu -group dtlb /testbench/dut/wallypipelinedsoc/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode
-add wave -noupdate -group lsu -group dtlb /testbench/dut/wallypipelinedsoc/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate
-add wave -noupdate -group lsu -group dtlb /testbench/dut/wallypipelinedsoc/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation
-add wave -noupdate -group lsu -group dtlb /testbench/dut/wallypipelinedsoc/hart/lsu/dmmu/TLBMiss
-add wave -noupdate -group lsu -group dtlb /testbench/dut/wallypipelinedsoc/hart/lsu/dmmu/TLBHit
-add wave -noupdate -group lsu -group dtlb /testbench/dut/wallypipelinedsoc/hart/lsu/dmmu/PhysicalAddress
-add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/wallypipelinedsoc/hart/lsu/dmmu/TLBPageFault
-add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/wallypipelinedsoc/hart/lsu/dmmu/LoadAccessFaultM
-add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/wallypipelinedsoc/hart/lsu/dmmu/StoreAccessFaultM
-add wave -noupdate -group lsu -group dtlb /testbench/dut/wallypipelinedsoc/hart/lsu/dmmu/genblk1/tlb/TLBPAdr
-add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/wallypipelinedsoc/hart/lsu/dmmu/genblk1/tlb/PTE
-add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/wallypipelinedsoc/hart/lsu/dmmu/genblk1/tlb/TLBWrite
-add wave -noupdate -group lsu -group pma /testbench/dut/wallypipelinedsoc/hart/lsu/dmmu/pmachecker/PhysicalAddress
-add wave -noupdate -group lsu -group pma /testbench/dut/wallypipelinedsoc/hart/lsu/dmmu/pmachecker/SelRegions
-add wave -noupdate -group lsu -group pma /testbench/dut/wallypipelinedsoc/hart/lsu/dmmu/Cacheable
-add wave -noupdate -group lsu -group pma /testbench/dut/wallypipelinedsoc/hart/lsu/dmmu/Idempotent
-add wave -noupdate -group lsu -group pma /testbench/dut/wallypipelinedsoc/hart/lsu/dmmu/AtomicAllowed
-add wave -noupdate -group lsu -group pma /testbench/dut/wallypipelinedsoc/hart/lsu/dmmu/pmachecker/PMAAccessFault
-add wave -noupdate -group lsu -group pma /testbench/dut/wallypipelinedsoc/hart/lsu/dmmu/PMAInstrAccessFaultF
-add wave -noupdate -group lsu -group pma /testbench/dut/wallypipelinedsoc/hart/lsu/dmmu/PMALoadAccessFaultM
-add wave -noupdate -group lsu -group pma /testbench/dut/wallypipelinedsoc/hart/lsu/dmmu/PMAStoreAccessFaultM
-add wave -noupdate -group lsu -group pmp /testbench/dut/wallypipelinedsoc/hart/lsu/dmmu/PMPInstrAccessFaultF
-add wave -noupdate -group lsu -group pmp /testbench/dut/wallypipelinedsoc/hart/lsu/dmmu/PMPLoadAccessFaultM
-add wave -noupdate -group lsu -group pmp /testbench/dut/wallypipelinedsoc/hart/lsu/dmmu/PMPStoreAccessFaultM
-add wave -noupdate -group lsu -group ptwalker -color Gold /testbench/dut/wallypipelinedsoc/hart/lsu/hptw/genblk1/WalkerState
-add wave -noupdate -group lsu -group ptwalker /testbench/dut/wallypipelinedsoc/hart/lsu/hptw/PCF
-add wave -noupdate -group lsu -group ptwalker /testbench/dut/wallypipelinedsoc/hart/lsu/hptw/genblk1/TranslationVAdr
-add wave -noupdate -group lsu -group ptwalker /testbench/dut/wallypipelinedsoc/hart/lsu/hptw/TranslationPAdr
-add wave -noupdate -group lsu -group ptwalker /testbench/dut/wallypipelinedsoc/hart/lsu/hptw/HPTWReadPTE
-add wave -noupdate -group lsu -group ptwalker /testbench/dut/wallypipelinedsoc/hart/lsu/hptw/PTE
-add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/wallypipelinedsoc/hart/lsu/hptw/ITLBMissF
-add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/wallypipelinedsoc/hart/lsu/hptw/DTLBMissM
-add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/wallypipelinedsoc/hart/lsu/hptw/ITLBWriteF
-add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/wallypipelinedsoc/hart/lsu/hptw/DTLBWriteM
-add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/wallypipelinedsoc/hart/lsu/hptw/WalkerInstrPageFaultF
-add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/wallypipelinedsoc/hart/lsu/hptw/WalkerLoadPageFaultM
-add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/wallypipelinedsoc/hart/lsu/hptw/WalkerStorePageFaultM
-add wave -noupdate -group csr /testbench/dut/wallypipelinedsoc/hart/priv/csr/MIP_REGW
-add wave -noupdate -group itlb /testbench/dut/wallypipelinedsoc/hart/ifu/immu/TLBWrite
-add wave -noupdate -group itlb /testbench/dut/wallypipelinedsoc/hart/ifu/ITLBMissF
-add wave -noupdate -group itlb /testbench/dut/wallypipelinedsoc/hart/ifu/immu/PhysicalAddress
-add wave -noupdate /testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/VAdr
-add wave -noupdate /testbench/dut/wallypipelinedsoc/hart/lsu.bus.dcache/MemPAdrM
+add wave -noupdate -group muldiv /testbench/dut/wallypipelinedsoc/core/mdu/InstrD
+add wave -noupdate -group muldiv /testbench/dut/wallypipelinedsoc/core/mdu/ForwardedSrcAE
+add wave -noupdate -group muldiv /testbench/dut/wallypipelinedsoc/core/mdu/ForwardedSrcBE
+add wave -noupdate -group muldiv /testbench/dut/wallypipelinedsoc/core/mdu/Funct3E
+add wave -noupdate -group muldiv /testbench/dut/wallypipelinedsoc/core/mdu/MulDivE
+add wave -noupdate -group muldiv /testbench/dut/wallypipelinedsoc/core/mdu/W64E
+add wave -noupdate -group muldiv /testbench/dut/wallypipelinedsoc/core/mdu/StallM
+add wave -noupdate -group muldiv /testbench/dut/wallypipelinedsoc/core/mdu/StallW
+add wave -noupdate -group muldiv /testbench/dut/wallypipelinedsoc/core/mdu/FlushM
+add wave -noupdate -group muldiv /testbench/dut/wallypipelinedsoc/core/mdu/FlushW
+add wave -noupdate -group muldiv /testbench/dut/wallypipelinedsoc/core/mdu/MulDivResultW
+add wave -noupdate -group muldiv /testbench/dut/wallypipelinedsoc/core/mdu/DivBusyE
+add wave -noupdate -group icache -color Gold /testbench/dut/wallypipelinedsoc/core/ifu/icache/controller/CurrState
+add wave -noupdate -group icache /testbench/dut/wallypipelinedsoc/core/ifu/icache/BasePAdrF
+add wave -noupdate -group icache /testbench/dut/wallypipelinedsoc/core/ifu/icache/WayHit
+add wave -noupdate -group icache /testbench/dut/wallypipelinedsoc/core/ifu/icache/genblk1/cachereplacementpolicy/BlockReplacementBits
+add wave -noupdate -group icache /testbench/dut/wallypipelinedsoc/core/ifu/icache/genblk1/cachereplacementpolicy/EncVicWay
+add wave -noupdate -group icache /testbench/dut/wallypipelinedsoc/core/ifu/icache/VictimWay
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 {/testbench/dut/wallypipelinedsoc/core/ifu/icache/MemWay[0]/WriteEnable}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 {/testbench/dut/wallypipelinedsoc/core/ifu/icache/MemWay[0]/SetValid}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/wallypipelinedsoc/core/ifu/icache/MemWay[0]/CacheTagMem/StoredData}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 {/testbench/dut/wallypipelinedsoc/core/ifu/icache/MemWay[0]/ValidBits}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/wallypipelinedsoc/core/ifu/icache/MemWay[0]/word[0]/CacheDataMem/StoredData}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/wallypipelinedsoc/core/ifu/icache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/wallypipelinedsoc/core/ifu/icache/MemWay[0]/word[1]/CacheDataMem/StoredData}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/wallypipelinedsoc/core/ifu/icache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word2 {/testbench/dut/wallypipelinedsoc/core/ifu/icache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word2 {/testbench/dut/wallypipelinedsoc/core/ifu/icache/MemWay[0]/word[2]/CacheDataMem/StoredData}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/wallypipelinedsoc/core/ifu/icache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/wallypipelinedsoc/core/ifu/icache/MemWay[0]/word[3]/CacheDataMem/StoredData}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 {/testbench/dut/wallypipelinedsoc/core/ifu/icache/MemWay[1]/WriteEnable}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 {/testbench/dut/wallypipelinedsoc/core/ifu/icache/MemWay[1]/WriteWordEnable}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/wallypipelinedsoc/core/ifu/icache/MemWay[1]/CacheTagMem/StoredData}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 {/testbench/dut/wallypipelinedsoc/core/ifu/icache/MemWay[1]/ValidBits}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/wallypipelinedsoc/core/ifu/icache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/wallypipelinedsoc/core/ifu/icache/MemWay[1]/word[0]/CacheDataMem/StoredData}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/wallypipelinedsoc/core/ifu/icache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/wallypipelinedsoc/core/ifu/icache/MemWay[1]/word[1]/CacheDataMem/StoredData}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/wallypipelinedsoc/core/ifu/icache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/wallypipelinedsoc/core/ifu/icache/MemWay[1]/word[2]/CacheDataMem/StoredData}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/wallypipelinedsoc/core/ifu/icache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/wallypipelinedsoc/core/ifu/icache/MemWay[1]/word[3]/CacheDataMem/StoredData}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 {/testbench/dut/wallypipelinedsoc/core/ifu/icache/MemWay[2]/WriteEnable}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 {/testbench/dut/wallypipelinedsoc/core/ifu/icache/MemWay[2]/SetValid}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/wallypipelinedsoc/core/ifu/icache/MemWay[2]/CacheTagMem/StoredData}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 {/testbench/dut/wallypipelinedsoc/core/ifu/icache/MemWay[2]/ValidBits}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/wallypipelinedsoc/core/ifu/icache/MemWay[2]/word[0]/CacheDataMem/StoredData}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/wallypipelinedsoc/core/ifu/icache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/wallypipelinedsoc/core/ifu/icache/MemWay[2]/word[1]/CacheDataMem/StoredData}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/wallypipelinedsoc/core/ifu/icache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/wallypipelinedsoc/core/ifu/icache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/wallypipelinedsoc/core/ifu/icache/MemWay[2]/word[2]/CacheDataMem/StoredData}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/wallypipelinedsoc/core/ifu/icache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/wallypipelinedsoc/core/ifu/icache/MemWay[2]/word[3]/CacheDataMem/StoredData}
+add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/ifu/icache/MemWay[3]/WriteEnable}
+add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/ifu/icache/MemWay[3]/SetValid}
+add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/wallypipelinedsoc/core/ifu/icache/MemWay[3]/CacheTagMem/StoredData}
+add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/ifu/icache/MemWay[3]/DirtyBits}
+add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/ifu/icache/MemWay[3]/ValidBits}
+add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/wallypipelinedsoc/core/ifu/icache/MemWay[3]/word[0]/CacheDataMem/StoredData}
+add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/wallypipelinedsoc/core/ifu/icache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
+add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/wallypipelinedsoc/core/ifu/icache/MemWay[3]/word[1]/CacheDataMem/StoredData}
+add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/wallypipelinedsoc/core/ifu/icache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
+add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/wallypipelinedsoc/core/ifu/icache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
+add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/wallypipelinedsoc/core/ifu/icache/MemWay[3]/word[2]/CacheDataMem/StoredData}
+add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/wallypipelinedsoc/core/ifu/icache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
+add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/wallypipelinedsoc/core/ifu/icache/MemWay[3]/word[3]/CacheDataMem/StoredData}
+add wave -noupdate -group icache /testbench/dut/wallypipelinedsoc/core/ifu/icache/controller/NextState
+add wave -noupdate -group icache /testbench/dut/wallypipelinedsoc/core/ifu/ITLBMissF
+add wave -noupdate -group icache /testbench/dut/wallypipelinedsoc/core/ifu/icache/ITLBWriteF
+add wave -noupdate -group icache /testbench/dut/wallypipelinedsoc/core/ifu/icache/ReadLineF
+add wave -noupdate -group icache /testbench/dut/wallypipelinedsoc/core/ifu/icache/PCNextIndexF
+add wave -noupdate -group icache /testbench/dut/wallypipelinedsoc/core/ifu/icache/ReadLineF
+add wave -noupdate -group icache /testbench/dut/wallypipelinedsoc/core/ifu/icache/BasePAdrF
+add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/wallypipelinedsoc/core/ifu/icache/controller/hit
+add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/wallypipelinedsoc/core/ifu/icache/controller/spill
+add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/wallypipelinedsoc/core/ifu/icache/controller/ICacheStallF
+add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/wallypipelinedsoc/core/ifu/icache/controller/SavePC
+add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/wallypipelinedsoc/core/ifu/icache/controller/spillSave
+add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/wallypipelinedsoc/core/ifu/icache/controller/UnalignedSelect
+add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/wallypipelinedsoc/core/ifu/icache/controller/spillSave
+add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/wallypipelinedsoc/core/ifu/icache/controller/CntReset
+add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/wallypipelinedsoc/core/ifu/icache/controller/PreCntEn
+add wave -noupdate -group icache -group {fsm out and control} /testbench/dut/wallypipelinedsoc/core/ifu/icache/controller/CntEn
+add wave -noupdate -group icache -expand -group memory /testbench/dut/wallypipelinedsoc/core/ifu/icache/InstrPAdrF
+add wave -noupdate -group icache -expand -group memory /testbench/dut/wallypipelinedsoc/core/ifu/icache/InstrInF
+add wave -noupdate -group icache -expand -group memory /testbench/dut/wallypipelinedsoc/core/ifu/icache/controller/FetchCountFlag
+add wave -noupdate -group icache -expand -group memory /testbench/dut/wallypipelinedsoc/core/ifu/icache/FetchCount
+add wave -noupdate -group icache -expand -group memory /testbench/dut/wallypipelinedsoc/core/ifu/icache/controller/InstrReadF
+add wave -noupdate -group icache -expand -group memory /testbench/dut/wallypipelinedsoc/core/ifu/icache/controller/InstrAckF
+add wave -noupdate -group icache -expand -group memory /testbench/dut/wallypipelinedsoc/core/ifu/icache/controller/ICacheMemWriteEnable
+add wave -noupdate -group icache -expand -group memory /testbench/dut/wallypipelinedsoc/core/ifu/icache/ICacheMemWriteData
+add wave -noupdate -group AHB -color Gold /testbench/dut/wallypipelinedsoc/core/ebu/BusState
+add wave -noupdate -group AHB /testbench/dut/wallypipelinedsoc/core/ebu/NextBusState
+add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/wallypipelinedsoc/core/ebu/AtomicMaskedM
+add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/wallypipelinedsoc/core/ebu/InstrReadF
+add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/wallypipelinedsoc/core/ebu/MemSizeM
+add wave -noupdate -group AHB /testbench/dut/wallypipelinedsoc/core/ebu/HCLK
+add wave -noupdate -group AHB /testbench/dut/wallypipelinedsoc/core/ebu/HRESETn
+add wave -noupdate -group AHB /testbench/dut/wallypipelinedsoc/core/ebu/HRDATA
+add wave -noupdate -group AHB /testbench/dut/wallypipelinedsoc/core/ebu/HREADY
+add wave -noupdate -group AHB /testbench/dut/wallypipelinedsoc/core/ebu/HRESP
+add wave -noupdate -group AHB /testbench/dut/wallypipelinedsoc/core/ebu/HADDR
+add wave -noupdate -group AHB /testbench/dut/wallypipelinedsoc/core/ebu/HWDATA
+add wave -noupdate -group AHB /testbench/dut/wallypipelinedsoc/core/ebu/HWRITE
+add wave -noupdate -group AHB /testbench/dut/wallypipelinedsoc/core/ebu/HSIZE
+add wave -noupdate -group AHB /testbench/dut/wallypipelinedsoc/core/ebu/HBURST
+add wave -noupdate -group AHB /testbench/dut/wallypipelinedsoc/core/ebu/HPROT
+add wave -noupdate -group AHB /testbench/dut/wallypipelinedsoc/core/ebu/HTRANS
+add wave -noupdate -group AHB /testbench/dut/wallypipelinedsoc/core/ebu/HMASTLOCK
+add wave -noupdate -group AHB /testbench/dut/wallypipelinedsoc/core/ebu/HADDRD
+add wave -noupdate -group AHB /testbench/dut/wallypipelinedsoc/core/ebu/HSIZED
+add wave -noupdate -group AHB /testbench/dut/wallypipelinedsoc/core/ebu/HWRITED
+add wave -noupdate -group AHB /testbench/dut/wallypipelinedsoc/core/ebu/StallW
+add wave -noupdate -group lsu -expand -group {LSU ARB} /testbench/dut/wallypipelinedsoc/core/lsu/arbiter/SelPTW
+add wave -noupdate -group lsu -expand -group dcache -color Gold /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/dcachefsm/CurrState
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/WalkerPageFaultM
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/WriteDataM
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/SRAMBlockWriteEnableM
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/SRAMWordWriteEnableM
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/SRAMWayWriteEnable
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/SRAMWordEnable
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/SRAMBlockWayWriteEnableM
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/SelAdrM
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/ReadDataBlockM
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/DCacheMemWriteData
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/FlushWay
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/VictimDirty
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/VDWriteEnableWay
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/ClearDirty
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[0]/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[0]/SetValid}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[0]/SetDirty}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[0]/CacheTagMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[0]/DirtyBits}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[0]/ValidBits}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[0]/word[0]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[0]/word[1]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[0]/word[2]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[0]/word[3]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[1]/DirtyBits}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[1]/SetDirty}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[1]/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[1]/WriteWordEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[1]/CacheTagMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[1]/word[0]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[1]/word[1]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[1]/word[2]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[1]/word[3]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[2]/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[2]/SetValid}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[2]/SetDirty}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[2]/CacheTagMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[2]/DirtyBits}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[2]/ValidBits}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[2]/word[0]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[2]/word[1]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[2]/word[2]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[2]/word[3]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[3]/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[3]/SetValid}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[3]/SetDirty}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[3]/CacheTagMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[3]/DirtyBits}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[3]/ValidBits}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[3]/word[0]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[3]/word[1]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[3]/word[2]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[3]/word[3]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/SetValid
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/ClearValid
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/SetDirty
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/ClearDirty
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[0]/WayHit}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[0]/Valid}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[0]/Dirty}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[0]/ReadTag}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[1]/WayHit}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[1]/Valid}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[1]/Dirty}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[1]/ReadTag}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[2]/WayHit}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[2]/Valid}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[2]/Dirty}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[2]/ReadTag}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[3]/WayHit}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[3]/Valid}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[3]/Dirty}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[3]/ReadTag}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/WayHit
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/ReadDataBlockWayMaskedM
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/ReadDataWordM
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/ReadDataWordMuxM
+add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/VictimTag
+add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/VictimWay
+add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/VictimDirtyWay
+add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/VictimDirty
+add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemRWM
+add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemAdrE
+add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemPAdrM
+add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/Funct3M
+add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/Funct7M
+add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/AtomicM
+add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/FlushDCacheM
+add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheableM
+add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/WriteDataM
+add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/ReadDataM
+add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/DCacheStallM
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/FlushAdrFlag
+add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/WayHit
+add wave -noupdate -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheHit
+add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/FetchCount
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/FetchCountFlag
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/AHBPAdr
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/AHBRead
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/AHBWrite
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/AHBAck
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/HRDATA
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/HWDATA
+add wave -noupdate -group lsu -group dtlb /testbench/dut/wallypipelinedsoc/core/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode
+add wave -noupdate -group lsu -group dtlb /testbench/dut/wallypipelinedsoc/core/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate
+add wave -noupdate -group lsu -group dtlb /testbench/dut/wallypipelinedsoc/core/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation
+add wave -noupdate -group lsu -group dtlb /testbench/dut/wallypipelinedsoc/core/lsu/dmmu/TLBMiss
+add wave -noupdate -group lsu -group dtlb /testbench/dut/wallypipelinedsoc/core/lsu/dmmu/TLBHit
+add wave -noupdate -group lsu -group dtlb /testbench/dut/wallypipelinedsoc/core/lsu/dmmu/PhysicalAddress
+add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/wallypipelinedsoc/core/lsu/dmmu/TLBPageFault
+add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/wallypipelinedsoc/core/lsu/dmmu/LoadAccessFaultM
+add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/wallypipelinedsoc/core/lsu/dmmu/StoreAccessFaultM
+add wave -noupdate -group lsu -group dtlb /testbench/dut/wallypipelinedsoc/core/lsu/dmmu/genblk1/tlb/TLBPAdr
+add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/wallypipelinedsoc/core/lsu/dmmu/genblk1/tlb/PTE
+add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/wallypipelinedsoc/core/lsu/dmmu/genblk1/tlb/TLBWrite
+add wave -noupdate -group lsu -group pma /testbench/dut/wallypipelinedsoc/core/lsu/dmmu/pmachecker/PhysicalAddress
+add wave -noupdate -group lsu -group pma /testbench/dut/wallypipelinedsoc/core/lsu/dmmu/pmachecker/SelRegions
+add wave -noupdate -group lsu -group pma /testbench/dut/wallypipelinedsoc/core/lsu/dmmu/Cacheable
+add wave -noupdate -group lsu -group pma /testbench/dut/wallypipelinedsoc/core/lsu/dmmu/Idempotent
+add wave -noupdate -group lsu -group pma /testbench/dut/wallypipelinedsoc/core/lsu/dmmu/AtomicAllowed
+add wave -noupdate -group lsu -group pma /testbench/dut/wallypipelinedsoc/core/lsu/dmmu/pmachecker/PMAAccessFault
+add wave -noupdate -group lsu -group pma /testbench/dut/wallypipelinedsoc/core/lsu/dmmu/PMAInstrAccessFaultF
+add wave -noupdate -group lsu -group pma /testbench/dut/wallypipelinedsoc/core/lsu/dmmu/PMALoadAccessFaultM
+add wave -noupdate -group lsu -group pma /testbench/dut/wallypipelinedsoc/core/lsu/dmmu/PMAStoreAccessFaultM
+add wave -noupdate -group lsu -group pmp /testbench/dut/wallypipelinedsoc/core/lsu/dmmu/PMPInstrAccessFaultF
+add wave -noupdate -group lsu -group pmp /testbench/dut/wallypipelinedsoc/core/lsu/dmmu/PMPLoadAccessFaultM
+add wave -noupdate -group lsu -group pmp /testbench/dut/wallypipelinedsoc/core/lsu/dmmu/PMPStoreAccessFaultM
+add wave -noupdate -group lsu -group ptwalker -color Gold /testbench/dut/wallypipelinedsoc/core/lsu/hptw/genblk1/WalkerState
+add wave -noupdate -group lsu -group ptwalker /testbench/dut/wallypipelinedsoc/core/lsu/hptw/PCF
+add wave -noupdate -group lsu -group ptwalker /testbench/dut/wallypipelinedsoc/core/lsu/hptw/genblk1/TranslationVAdr
+add wave -noupdate -group lsu -group ptwalker /testbench/dut/wallypipelinedsoc/core/lsu/hptw/TranslationPAdr
+add wave -noupdate -group lsu -group ptwalker /testbench/dut/wallypipelinedsoc/core/lsu/hptw/HPTWReadPTE
+add wave -noupdate -group lsu -group ptwalker /testbench/dut/wallypipelinedsoc/core/lsu/hptw/PTE
+add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/wallypipelinedsoc/core/lsu/hptw/ITLBMissF
+add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/wallypipelinedsoc/core/lsu/hptw/DTLBMissM
+add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/wallypipelinedsoc/core/lsu/hptw/ITLBWriteF
+add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/wallypipelinedsoc/core/lsu/hptw/DTLBWriteM
+add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/wallypipelinedsoc/core/lsu/hptw/WalkerInstrPageFaultF
+add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/wallypipelinedsoc/core/lsu/hptw/WalkerLoadPageFaultM
+add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/wallypipelinedsoc/core/lsu/hptw/WalkerStorePageFaultM
+add wave -noupdate -group csr /testbench/dut/wallypipelinedsoc/core/priv/csr/MIP_REGW
+add wave -noupdate -group itlb /testbench/dut/wallypipelinedsoc/core/ifu/immu/TLBWrite
+add wave -noupdate -group itlb /testbench/dut/wallypipelinedsoc/core/ifu/ITLBMissF
+add wave -noupdate -group itlb /testbench/dut/wallypipelinedsoc/core/ifu/immu/PhysicalAddress
+add wave -noupdate /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/VAdr
+add wave -noupdate /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemPAdrM
 add wave -noupdate -group plic /testbench/dut/wallypipelinedsoc/uncore/plic/plic/HCLK
 add wave -noupdate -group plic /testbench/dut/wallypipelinedsoc/uncore/plic/plic/HSELPLIC
 add wave -noupdate -group plic /testbench/dut/wallypipelinedsoc/uncore/plic/plic/HADDR

pipelined/regression/linux-wave.do

@@ -1,71 +1,71 @@
 onerror {resume}
-quietly virtual function -install /testbench/dut/hart/ifu -env /testbench/dut/hart/ifu { &{/testbench/dut/hart/ifu/BPPredWrongM, /testbench/dut/hart/ifu/InvalidateICacheM }} temp
+quietly virtual function -install /testbench/dut/core/ifu -env /testbench/dut/core/ifu { &{/testbench/dut/core/ifu/BPPredWrongM, /testbench/dut/core/ifu/InvalidateICacheM }} temp
 quietly WaveActivateNextPane {} 0
 add wave -noupdate /testbench/clk
 add wave -noupdate /testbench/reset
 add wave -noupdate /testbench/reset_ext
 add wave -noupdate -radix unsigned /testbench/InstrCountW
-add wave -noupdate /testbench/dut/hart/SATP_REGW
-add wave -noupdate /testbench/dut/hart/IllegalFPUInstrD
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
-add wave -noupdate -group HDU -expand -group hazards -color Pink /testbench/dut/hart/hzu/TrapM
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/StoreStallD
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LSUStallM
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/DivBusyE
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/trap/ExceptionM
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/trap/InstrMisalignedFaultM
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/trap/InstrAccessFaultM
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/trap/IllegalInstrFaultM
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/trap/LoadAccessFaultM
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/trap/StoreMisalignedFaultM
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/trap/InstrPageFaultM
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/trap/LoadPageFaultM
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/trap/StorePageFaultM
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/trap/BreakpointFaultM
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/trap/EcallFaultM
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/trap/LoadMisalignedFaultM
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/trap/StoreAccessFaultM
-add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
-add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD
-add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE
-add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM
-add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW
-add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
-add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
-add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
-add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
-add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
+add wave -noupdate /testbench/dut/core/SATP_REGW
+add wave -noupdate /testbench/dut/core/IllegalFPUInstrD
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/BPPredWrongE
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/CSRWritePendingDEM
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM
+add wave -noupdate -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LoadStallD
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/StoreStallD
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/ExceptionM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreMisalignedFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StorePageFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAccessFaultM
+add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/hzu/FlushF
+add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushD
+add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushE
+add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushM
+add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushW
+add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallF
+add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallD
+add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallE
+add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallM
+add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallW
 add wave -noupdate -group {instruction pipeline} /testbench/InstrFName
-add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/FinalInstrRawF
-add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrD
-add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrE
-add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrM
-add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ifu/PCD
-add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ifu/InstrD
+add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/FinalInstrRawF
+add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD
+add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrE
+add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrM
+add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/PCD
+add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/InstrD
 add wave -noupdate -group {Decode Stage} /testbench/InstrDName
-add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/c/InstrValidD
-add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD
-add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/RdD
-add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs1D
-add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs2D
-add wave -noupdate -group {Execution Stage} /testbench/dut/hart/ifu/PCE
+add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/InstrValidD
+add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/RegWriteD
+add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/RdD
+add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs1D
+add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs2D
+add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/PCE
 add wave -noupdate -group {Execution Stage} /testbench/ExpectedPCE
 add wave -noupdate -group {Execution Stage} /testbench/MepcExpected
-add wave -noupdate -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
+add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/InstrE
 add wave -noupdate -group {Execution Stage} /testbench/InstrEName
-add wave -noupdate -group {Execution Stage} /testbench/dut/hart/ieu/c/InstrValidE
+add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE
 add wave -noupdate -group {Execution Stage} /testbench/textE
 add wave -noupdate -group {Execution Stage} -color {Cornflower Blue} /testbench/FunctionName/FunctionName
 add wave -noupdate -expand -group {Memory Stage} /testbench/checkInstrM
-add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/PCM
+add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM
 add wave -noupdate -expand -group {Memory Stage} /testbench/ExpectedPCM
-add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/InstrM
+add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM
 add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName
 add wave -noupdate -expand -group {Memory Stage} /testbench/textM
-add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/lsu/IEUAdrM
+add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM
 add wave -noupdate -group {WriteBack stage} /testbench/checkInstrW
 add wave -noupdate -group {WriteBack stage} /testbench/InstrValidW
 add wave -noupdate -group {WriteBack stage} /testbench/PCW
@@ -73,307 +73,307 @@ add wave -noupdate -group {WriteBack stage} /testbench/ExpectedPCW
 add wave -noupdate -group {WriteBack stage} /testbench/InstrW
 add wave -noupdate -group {WriteBack stage} /testbench/InstrWName
 add wave -noupdate -group {WriteBack stage} /testbench/textW
-add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR
-add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF
-add wave -noupdate -group Bpred -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]}
-add wave -noupdate -group Bpred -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPInstrClassE[0]}
-add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredDirWrongE
+add wave -noupdate -group Bpred -color Orange /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHR
+add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF
+add wave -noupdate -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]}
+add wave -noupdate -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPInstrClassE[0]}
+add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPPredDirWrongE
 add wave -noupdate -group Bpred -group {branch update selection inputs} -divider {class check}
-add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightNonCFI
-add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassWrongCFI
-add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassWrongNonCFI
-add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPRight
-add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPWrong
-add wave -noupdate -group Bpred -radix hexadecimal -childformat {{{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} -radix binary} {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} -radix binary} {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} -radix binary} {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} -radix binary} {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} -radix binary} {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} -radix binary} {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} -radix binary}} -subitemconfig {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} {-height 16 -radix binary} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} {-height 16 -radix binary} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} {-height 16 -radix binary} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} {-height 16 -radix binary} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} {-height 16 -radix binary} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} {-height 16 -radix binary} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} {-height 16 -radix binary}} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel
-add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRNext
-add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRUpdateEN
-add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr
-add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr0
-add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr1
-add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateEN
-add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRLookup
-add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/PCNextF
-add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/PHT/RA1
-add wave -noupdate -group Bpred -expand -group prediction -radix binary /testbench/dut/hart/ifu/bpred/bpred/BPPredF
-add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/BTBValidF
-add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/BPInstrClassF
-add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/BTBPredPCF
-add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/RASPCF
-add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/LookUpPCIndex
-add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/TargetPC
-add wave -noupdate -group Bpred -expand -group prediction -expand -group ex -radix binary /testbench/dut/hart/ifu/bpred/bpred/BPPredE
-add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/hart/ifu/bpred/bpred/PCSrcE
-add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/hart/ifu/bpred/bpred/BPPredDirWrongE
-add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/UpdatePCIndex
-add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/UpdateTarget
-add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/UpdateEN
-add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/UpdatePC
-add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/UpdateTarget
-add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr
-add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/PCE
-add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/PHT/WA1
-add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/TargetWrongE
-add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/FallThroughWrongE
-add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/PredictionPCWrongE
-add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/InstrClassE
-add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/PredictionInstrClassWrongE
-add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/BPPredClassNonCFIWrongE
-add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/BPPredWrongE
-add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/BPPredWrongE
-add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCNextF
-add wave -noupdate -group PCS /testbench/dut/hart/PCF
-add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCD
-add wave -noupdate -group PCS /testbench/dut/hart/PCE
-add wave -noupdate -group PCS /testbench/dut/hart/PCM
+add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightNonCFI
+add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassWrongCFI
+add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassWrongNonCFI
+add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPRight
+add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPWrong
+add wave -noupdate -group Bpred -radix hexadecimal -childformat {{{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} -radix binary}} -subitemconfig {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} {-height 16 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} {-height 16 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} {-height 16 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} {-height 16 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} {-height 16 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} {-height 16 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} {-height 16 -radix binary}} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel
+add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNext
+add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRUpdateEN
+add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr
+add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr0
+add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr1
+add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateEN
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRLookup
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCNextF
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHT/RA1
+add wave -noupdate -group Bpred -expand -group prediction -radix binary /testbench/dut/core/ifu/bpred/bpred/BPPredF
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBValidF
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BPInstrClassF
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBPredPCF
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/LookUpPCIndex
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/TargetPC
+add wave -noupdate -group Bpred -expand -group prediction -expand -group ex -radix binary /testbench/dut/core/ifu/bpred/bpred/BPPredE
+add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE
+add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/BPPredDirWrongE
+add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdatePCIndex
+add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateTarget
+add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateEN
+add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdatePC
+add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateTarget
+add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr
+add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCE
+add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHT/WA1
+add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/TargetWrongE
+add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/FallThroughWrongE
+add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionPCWrongE
+add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/InstrClassE
+add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionInstrClassWrongE
+add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredClassNonCFIWrongE
+add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE
+add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE
+add wave -noupdate -group PCS /testbench/dut/core/ifu/PCNextF
+add wave -noupdate -group PCS /testbench/dut/core/PCF
+add wave -noupdate -group PCS /testbench/dut/core/ifu/PCD
+add wave -noupdate -group PCS /testbench/dut/core/PCE
+add wave -noupdate -group PCS /testbench/dut/core/PCM
 add wave -noupdate -group PCS /testbench/PCW
-add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNextF
-add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCF
-add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCPlus2or4F
-add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredPCF
-add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext0F
-add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext1F
-add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/SelBPPredF
-add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredWrongE
-add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PrivilegedChangePCM
-add wave -noupdate -group RegFile -expand /testbench/dut/hart/ieu/dp/regf/rf
-add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a1
-add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a2
-add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a3
-add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rd1
-add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rd2
-add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/we3
-add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/wd3
-add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ReadDataW
-add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW
-add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW
-add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW
-add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/A
-add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/B
-add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/ALUControl
+add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF
+add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF
+add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCPlus2or4F
+add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/BPPredPCF
+add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNext0F
+add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNext1F
+add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/SelBPPredF
+add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/BPPredWrongE
+add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PrivilegedChangePCM
+add wave -noupdate -group RegFile -expand /testbench/dut/core/ieu/dp/regf/rf
+add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a1
+add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a2
+add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a3
+add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/rd1
+add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/rd2
+add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/we3
+add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/wd3
+add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ReadDataW
+add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/CSRReadValW
+add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ResultSrcW
+add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ResultW
+add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/A
+add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/B
+add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/ALUControl
 add wave -noupdate -group alu -divider internals
-add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1D
-add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs2D
-add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1E
-add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs2E
-add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/RdE
-add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/RdM
-add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/RdW
-add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/MemReadE
-add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/RegWriteM
-add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/RegWriteW
-add wave -noupdate -group Forward -color Thistle /testbench/dut/hart/ieu/fw/ForwardAE
-add wave -noupdate -group Forward -color Thistle /testbench/dut/hart/ieu/fw/ForwardBE
-add wave -noupdate -group Forward -color Thistle /testbench/dut/hart/ieu/fw/LoadStallD
-add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/WriteDataE
-add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/ALUResultE
-add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcAE
-add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcBE
-add wave -noupdate -group icache -color Gold /testbench/dut/hart/ifu/icache/icache/cachefsm/CurrState
-add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/icache/ReadDataWord
-add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/icache/SelAdr
-add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/icache/RAdr
-add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/icache/CacheHit
-add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/icache/CacheStall
-add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/icache/ReadDataLineSets
-add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/icache/CacheMemWriteData
-add wave -noupdate -group icache /testbench/dut/hart/ifu/SpillSupport/SpillDataLine0
-add wave -noupdate -group AHB -color Gold /testbench/dut/hart/ebu/BusState
-add wave -noupdate -group AHB /testbench/dut/hart/ebu/NextBusState
-add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/AtomicMaskedM
-add wave -noupdate -group AHB /testbench/dut/hart/ebu/HCLK
-add wave -noupdate -group AHB /testbench/dut/hart/ebu/HRESETn
-add wave -noupdate -group AHB /testbench/dut/hart/ebu/HRDATA
-add wave -noupdate -group AHB /testbench/dut/hart/ebu/HREADY
-add wave -noupdate -group AHB /testbench/dut/hart/ebu/HRESP
-add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDR
-add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWDATA
-add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITE
-add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZE
-add wave -noupdate -group AHB /testbench/dut/hart/ebu/HBURST
-add wave -noupdate -group AHB /testbench/dut/hart/ebu/HPROT
-add wave -noupdate -group AHB /testbench/dut/hart/ebu/HTRANS
-add wave -noupdate -group AHB /testbench/dut/hart/ebu/HMASTLOCK
-add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDRD
-add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED
-add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED
-add wave -noupdate -group AMO_ALU /testbench/dut/hart/lsu/amo/amoalu/funct
-add wave -noupdate -group AMO_ALU /testbench/dut/hart/lsu/amo/amoalu/result
-add wave -noupdate -group AMO_ALU /testbench/dut/hart/lsu/amo/amoalu/srca
-add wave -noupdate -group AMO_ALU /testbench/dut/hart/lsu/amo/amoalu/srcb
-add wave -noupdate -group AMO_ALU /testbench/dut/hart/lsu/amo/amoalu/width
-add wave -noupdate -expand -group lsu -color Gold /testbench/dut/hart/lsu/MEM_VIRTMEM/interlockfsm/InterlockCurrState
-add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/SelHPTW
-add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/InterlockStall
-add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/LSUStallM
-add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/ReadDataM
-add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/WriteDataM
-add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu.bus.dcache/dcache/cachefsm/CurrState
-add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu.bus.dcache/dcache/FinalWriteData
-add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu.bus.dcache/dcache/SRAMWayWriteEnable
-add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu.bus.dcache/dcache/SRAMWordEnable
-add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu.bus.dcache/dcache/SelAdr
-add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/MEM_VIRTMEM/SelReplayCPURequest
-add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/IEUAdrE
-add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/IEUAdrM
-add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu.bus.dcache/dcache/RAdr
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush -radix unsigned /testbench/dut/hart/lsu.bus.dcache/dcache/FlushAdr
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/hart/lsu.bus.dcache/dcache/VictimDirtyWay
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/hart/lsu.bus.dcache/dcache/VictimTag
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/hart/lsu.bus.dcache/dcache/CacheBusAdr
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/hart/lsu/WordCount
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/hart/lsu.bus.dcache/dcache/FlushAdr
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/hart/lsu.bus.dcache/dcache/FlushWay
-add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu.bus.dcache/dcache/CacheMemWriteData
-add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu.bus.dcache/dcache/WayHit
-add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu.bus.dcache/dcache/IgnoreRequest
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[0]/WriteEnable}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[0]/SetValid}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[0]/SetDirty}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[0]/CacheTagMem/StoredData}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[0]/DirtyBits}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[0]/ValidBits}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[0]/word[0]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[0]/word[1]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[0]/word[2]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[0]/word[3]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[1]/DirtyBits}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[1]/ValidBits}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[1]/SetDirty}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[1]/WriteEnable}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[1]/WriteWordEnable}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[1]/CacheTagMem/StoredData}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[1]/word[0]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[1]/word[1]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[1]/word[2]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[1]/word[3]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[2]/WriteEnable}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[2]/SetValid}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[2]/SetDirty}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[2]/CacheTagMem/StoredData}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[2]/DirtyBits}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[2]/ValidBits}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[2]/word[0]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[2]/word[1]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[2]/word[2]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[2]/word[3]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[3]/WriteEnable}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[3]/SetValid}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[3]/SetDirty}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[3]/ClearDirty}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[3]/VDWriteEnable}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[3]/CacheTagMem/StoredData}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[3]/DirtyBits}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[3]/ValidBits}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[3]/word[0]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[3]/word[1]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[3]/word[2]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[3]/word[3]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu.bus.dcache/dcache/SetValid
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu.bus.dcache/dcache/ClearValid
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu.bus.dcache/dcache/SetDirty
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu.bus.dcache/dcache/ClearDirty
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu.bus.dcache/dcache/RAdr
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[0]/WayHit}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[0]/Valid}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[0]/Dirty}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[0]/ReadTag}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[1]/WayHit}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[1]/Valid}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[1]/Dirty}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[1]/ReadTag}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[2]/WayHit}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[2]/Valid}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[2]/Dirty}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[2]/ReadTag}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[3]/WayHit}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[3]/Valid}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[3]/Dirty}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu.bus.dcache/dcache/MemWay[3]/ReadTag}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu.bus.dcache/dcache/WayHit
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu.bus.dcache/dcache/ReadDataWord
-add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu.bus.dcache/dcache/VictimTag
-add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu.bus.dcache/dcache/VictimWay
-add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu.bus.dcache/dcache/VictimDirtyWay
-add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu.bus.dcache/dcache/VictimDirty
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu.bus.dcache/dcache/RW
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/IEUAdrM
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu.bus.dcache/dcache/FlushCache
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu.bus.dcache/dcache/FinalWriteData
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu.bus.dcache/dcache/ReadDataWord
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu.bus.dcache/dcache/CacheStall
-add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu.bus.dcache/dcache/WayHit
-add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu.bus.dcache/dcache/CacheHit
-add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/WordCount
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu.bus.dcache/dcache/CacheBusAdr
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu.bus.dcache/dcache/CacheFetchLine
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu.bus.dcache/dcache/CacheWriteLine
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu.bus.dcache/dcache/CacheBusAck
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu.bus.dcache/dcache/CacheMemWriteData
-add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode
-add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate
-add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation
-add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/TLBMiss
-add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/TLBHit
-add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/PhysicalAddress
-add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/dmmu/TLBPageFault
-add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/dmmu/LoadAccessFaultM
-add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/dmmu/StoreAccessFaultM
-add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr
-add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/PTE
-add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/TLBWrite
-add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/pmachecker/PhysicalAddress
-add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/pmachecker/SelRegions
-add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/Cacheable
-add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/Idempotent
-add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/AtomicAllowed
-add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/pmachecker/PMAAccessFault
-add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/PMAInstrAccessFaultF
-add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/PMALoadAccessFaultM
-add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/PMAStoreAccessFaultM
-add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/PhysicalAddress
-add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/ReadAccessM
-add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/WriteAccessM
-add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/PMPADDR_ARRAY_REGW
-add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/PMPCFG_ARRAY_REGW
-add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/PMPInstrAccessFaultF
-add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/PMPLoadAccessFaultM
-add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/PMPStoreAccessFaultM
-add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/Match
-add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/FirstMatch
-add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/R
-add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/W
-add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/X
-add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/L
-add wave -noupdate -expand -group lsu -group ptwalker -color Gold /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/WalkerState
-add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/PCF
-add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/HPTWAdr
-add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/HPTWReadPTE
-add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/HPTWAdr
-add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/PTE
-add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/ITLBMissF
-add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/DTLBMissM
-add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/ITLBWriteF
-add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/DTLBWriteM
-add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/TLBWrite
-add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF
-add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress
-add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/PMAInstrAccessFaultF
+add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs1D
+add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs2D
+add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs1E
+add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs2E
+add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdE
+add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdM
+add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdW
+add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/MemReadE
+add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RegWriteM
+add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RegWriteW
+add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/ForwardAE
+add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/ForwardBE
+add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/LoadStallD
+add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/WriteDataE
+add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/ALUResultE
+add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcAE
+add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcBE
+add wave -noupdate -group icache -color Gold /testbench/dut/core/ifu/icache/icache/cachefsm/CurrState
+add wave -noupdate -group icache /testbench/dut/core/ifu/icache/icache/ReadDataWord
+add wave -noupdate -group icache /testbench/dut/core/ifu/icache/icache/SelAdr
+add wave -noupdate -group icache /testbench/dut/core/ifu/icache/icache/RAdr
+add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/icache/icache/CacheHit
+add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/icache/icache/CacheStall
+add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/icache/icache/ReadDataLineSets
+add wave -noupdate -group icache -expand -group memory /testbench/dut/core/ifu/icache/icache/CacheMemWriteData
+add wave -noupdate -group icache /testbench/dut/core/ifu/SpillSupport/SpillDataLine0
+add wave -noupdate -group AHB -color Gold /testbench/dut/core/ebu/BusState
+add wave -noupdate -group AHB /testbench/dut/core/ebu/NextBusState
+add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/core/ebu/AtomicMaskedM
+add wave -noupdate -group AHB /testbench/dut/core/ebu/HCLK
+add wave -noupdate -group AHB /testbench/dut/core/ebu/HRESETn
+add wave -noupdate -group AHB /testbench/dut/core/ebu/HRDATA
+add wave -noupdate -group AHB /testbench/dut/core/ebu/HREADY
+add wave -noupdate -group AHB /testbench/dut/core/ebu/HRESP
+add wave -noupdate -group AHB /testbench/dut/core/ebu/HADDR
+add wave -noupdate -group AHB /testbench/dut/core/ebu/HWDATA
+add wave -noupdate -group AHB /testbench/dut/core/ebu/HWRITE
+add wave -noupdate -group AHB /testbench/dut/core/ebu/HSIZE
+add wave -noupdate -group AHB /testbench/dut/core/ebu/HBURST
+add wave -noupdate -group AHB /testbench/dut/core/ebu/HPROT
+add wave -noupdate -group AHB /testbench/dut/core/ebu/HTRANS
+add wave -noupdate -group AHB /testbench/dut/core/ebu/HMASTLOCK
+add wave -noupdate -group AHB /testbench/dut/core/ebu/HADDRD
+add wave -noupdate -group AHB /testbench/dut/core/ebu/HSIZED
+add wave -noupdate -group AHB /testbench/dut/core/ebu/HWRITED
+add wave -noupdate -group AMO_ALU /testbench/dut/core/lsu/amo/amoalu/funct
+add wave -noupdate -group AMO_ALU /testbench/dut/core/lsu/amo/amoalu/result
+add wave -noupdate -group AMO_ALU /testbench/dut/core/lsu/amo/amoalu/srca
+add wave -noupdate -group AMO_ALU /testbench/dut/core/lsu/amo/amoalu/srcb
+add wave -noupdate -group AMO_ALU /testbench/dut/core/lsu/amo/amoalu/width
+add wave -noupdate -expand -group lsu -color Gold /testbench/dut/core/lsu/MEM_VIRTMEM/interlockfsm/InterlockCurrState
+add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/SelHPTW
+add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/InterlockStall
+add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/LSUStallM
+add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataM
+add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/WriteDataM
+add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu.bus.dcache/dcache/cachefsm/CurrState
+add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/dcache/FinalWriteData
+add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/dcache/SRAMWayWriteEnable
+add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/dcache/SRAMWordEnable
+add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/dcache/SelAdr
+add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/MEM_VIRTMEM/SelReplayCPURequest
+add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrE
+add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrM
+add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/dcache/RAdr
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush -radix unsigned /testbench/dut/core/lsu.bus.dcache/dcache/FlushAdr
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu.bus.dcache/dcache/VictimDirtyWay
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu.bus.dcache/dcache/VictimTag
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu.bus.dcache/dcache/CacheBusAdr
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/WordCount
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu.bus.dcache/dcache/FlushAdr
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu.bus.dcache/dcache/FlushWay
+add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/dcache/CacheMemWriteData
+add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/dcache/WayHit
+add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/dcache/IgnoreRequest
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/SetValid}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/SetDirty}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/CacheTagMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/DirtyBits}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/ValidBits}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/word[0]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/word[1]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/word[2]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/word[3]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/DirtyBits}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/ValidBits}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/SetDirty}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/WriteWordEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/CacheTagMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/word[0]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/word[1]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/word[2]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/word[3]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/SetValid}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/SetDirty}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/CacheTagMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/DirtyBits}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/ValidBits}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/word[0]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/word[1]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/word[2]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/word[3]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/SetValid}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/SetDirty}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/ClearDirty}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/VDWriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/CacheTagMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/DirtyBits}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/ValidBits}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/word[0]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/word[1]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/word[2]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/word[3]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu.bus.dcache/dcache/SetValid
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu.bus.dcache/dcache/ClearValid
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu.bus.dcache/dcache/SetDirty
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu.bus.dcache/dcache/ClearDirty
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu.bus.dcache/dcache/RAdr
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/WayHit}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/Valid}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/Dirty}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/ReadTag}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/WayHit}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/Valid}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/Dirty}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/ReadTag}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/WayHit}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/Valid}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/Dirty}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/ReadTag}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/WayHit}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/Valid}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/Dirty}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/ReadTag}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu.bus.dcache/dcache/WayHit
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu.bus.dcache/dcache/ReadDataWord
+add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu.bus.dcache/dcache/VictimTag
+add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu.bus.dcache/dcache/VictimWay
+add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu.bus.dcache/dcache/VictimDirtyWay
+add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu.bus.dcache/dcache/VictimDirty
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu.bus.dcache/dcache/RW
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/IEUAdrM
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu.bus.dcache/dcache/FlushCache
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu.bus.dcache/dcache/FinalWriteData
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu.bus.dcache/dcache/ReadDataWord
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu.bus.dcache/dcache/CacheStall
+add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/core/lsu.bus.dcache/dcache/WayHit
+add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu.bus.dcache/dcache/CacheHit
+add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/core/lsu/WordCount
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu.bus.dcache/dcache/CacheBusAdr
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu.bus.dcache/dcache/CacheFetchLine
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu.bus.dcache/dcache/CacheWriteLine
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu.bus.dcache/dcache/CacheBusAck
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu.bus.dcache/dcache/CacheMemWriteData
+add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode
+add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate
+add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation
+add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss
+add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit
+add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress
+add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault
+add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM
+add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAccessFaultM
+add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr
+add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
+add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite
+add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress
+add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions
+add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable
+add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent
+add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/AtomicAllowed
+add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault
+add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF
+add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM
+add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAccessFaultM
+add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PhysicalAddress
+add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/ReadAccessM
+add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/WriteAccessM
+add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPADDR_ARRAY_REGW
+add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPCFG_ARRAY_REGW
+add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF
+add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM
+add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAccessFaultM
+add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/pmpchecker/Match
+add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/pmpchecker/FirstMatch
+add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/pmpchecker/R
+add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/pmpchecker/W
+add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/pmpchecker/X
+add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/pmpchecker/L
+add wave -noupdate -expand -group lsu -group ptwalker -color Gold /testbench/dut/core/lsu/MEM_VIRTMEM/hptw/WalkerState
+add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/MEM_VIRTMEM/hptw/PCF
+add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/MEM_VIRTMEM/hptw/HPTWAdr
+add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/MEM_VIRTMEM/hptw/HPTWReadPTE
+add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/MEM_VIRTMEM/hptw/HPTWAdr
+add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/MEM_VIRTMEM/hptw/PTE
+add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/MEM_VIRTMEM/hptw/ITLBMissF
+add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/MEM_VIRTMEM/hptw/DTLBMissM
+add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/MEM_VIRTMEM/hptw/ITLBWriteF
+add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/MEM_VIRTMEM/hptw/DTLBWriteM
+add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/TLBWrite
+add wave -noupdate -group itlb /testbench/dut/core/ifu/ITLBMissF
+add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/PhysicalAddress
+add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/PMAInstrAccessFaultF
 add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HCLK
 add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HSELPLIC
 add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HADDR
@@ -442,39 +442,39 @@ add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HSELUART
 add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HADDR
 add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWRITE
 add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWDATA
-add wave -noupdate -group {debug trace} -expand -group mem -color Yellow /testbench/dut/hart/FlushW
+add wave -noupdate -group {debug trace} -expand -group mem -color Yellow /testbench/dut/core/FlushW
 add wave -noupdate -group {debug trace} -expand -group mem /testbench/checkInstrM
-add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/hart/PCM
+add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/core/PCM
 add wave -noupdate -group {debug trace} -expand -group mem /testbench/ExpectedPCM
 add wave -noupdate -group {debug trace} -expand -group mem /testbench/textM
-add wave -noupdate -group {debug trace} -expand -group mem -color Brown /testbench/dut/hart/hzu/TrapM
+add wave -noupdate -group {debug trace} -expand -group mem -color Brown /testbench/dut/core/hzu/TrapM
 add wave -noupdate -group {debug trace} -expand -group wb /testbench/checkInstrW
 add wave -noupdate -group {debug trace} -expand -group wb /testbench/PCW
 add wave -noupdate -group {debug trace} -expand -group wb /testbench/ExpectedPCW
 add wave -noupdate -group {debug trace} -expand -group wb /testbench/TrapW
 add wave -noupdate -group {debug trace} -expand -group wb /testbench/textW
-add wave -noupdate -group {pc selection} /testbench/dut/hart/ifu/PCNext2F
-add wave -noupdate -group {pc selection} /testbench/dut/hart/ifu/PrivilegedNextPCM
-add wave -noupdate -group {pc selection} /testbench/dut/hart/ifu/PrivilegedChangePCM
-add wave -noupdate /testbench/dut/hart/ifu/PCCorrectE
-add wave -noupdate /testbench/dut/hart/ifu/PCSrcE
-add wave -noupdate /testbench/dut/hart/ieu/c/BranchTakenE
-add wave -noupdate /testbench/dut/hart/ieu/c/BranchE
-add wave -noupdate /testbench/dut/hart/ifu/PCLinkE
-add wave -noupdate /testbench/dut/hart/ifu/PCF
+add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PCNext2F
+add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PrivilegedNextPCM
+add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PrivilegedChangePCM
+add wave -noupdate /testbench/dut/core/ifu/PCCorrectE
+add wave -noupdate /testbench/dut/core/ifu/PCSrcE
+add wave -noupdate /testbench/dut/core/ieu/c/BranchTakenE
+add wave -noupdate /testbench/dut/core/ieu/c/BranchE
+add wave -noupdate /testbench/dut/core/ifu/PCLinkE
+add wave -noupdate /testbench/dut/core/ifu/PCF
 add wave -noupdate /testbench/dut/uncore/uart/uart/u/LSR
 add wave -noupdate /testbench/dut/uncore/uart/uart/u/DLM
 add wave -noupdate /testbench/dut/uncore/uart/uart/u/DLAB
-add wave -noupdate /testbench/dut/hart/ifu/temp
-add wave -noupdate /testbench/dut/hart/ifu/BPPredWrongM
-add wave -noupdate /testbench/dut/hart/ifu/InvalidateICacheM
-add wave -noupdate -expand -group ifu /testbench/dut/hart/ifu/PCF
-add wave -noupdate -expand -group ifu /testbench/dut/hart/ifu/PostSpillInstrRawF
-add wave -noupdate -expand -group ifu -expand -group {Bus FSM} -color Gold /testbench/dut/hart/ifu/busfsm/BusCurrState
-add wave -noupdate -expand -group ifu -expand -group {Bus FSM} /testbench/dut/hart/ifu/BusStall
-add wave -noupdate -expand -group ifu -expand -group Spills /testbench/dut/hart/ifu/SpillSupport/Spill
-add wave -noupdate -expand -group ifu -expand -group Spills -color Gold /testbench/dut/hart/ifu/SpillSupport/CurrState
-add wave -noupdate /testbench/dut/hart/lsu.bus.dcache/dcache/VictimTag
+add wave -noupdate /testbench/dut/core/ifu/temp
+add wave -noupdate /testbench/dut/core/ifu/BPPredWrongM
+add wave -noupdate /testbench/dut/core/ifu/InvalidateICacheM
+add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/PCF
+add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/PostSpillInstrRawF
+add wave -noupdate -expand -group ifu -expand -group {Bus FSM} -color Gold /testbench/dut/core/ifu/busfsm/BusCurrState
+add wave -noupdate -expand -group ifu -expand -group {Bus FSM} /testbench/dut/core/ifu/BusStall
+add wave -noupdate -expand -group ifu -expand -group Spills /testbench/dut/core/ifu/SpillSupport/Spill
+add wave -noupdate -expand -group ifu -expand -group Spills -color Gold /testbench/dut/core/ifu/SpillSupport/CurrState
+add wave -noupdate /testbench/dut/core/lsu.bus.dcache/dcache/VictimTag
 TreeUpdate [SetDefaultTree]
 WaveRestoreCursors {{Cursor 6} {5187387 ns} 1} {{Cursor 5} {88705641 ns} 0}
 quietly wave cursor active 2

pipelined/regression/wave-coremark.do

@@ -4,395 +4,395 @@ add wave -noupdate /testbench/clk
 add wave -noupdate /testbench/reset
 add wave -noupdate /testbench/test
 add wave -noupdate /testbench/memfilename
-add wave -noupdate /testbench/dut/hart/SATP_REGW
-add wave -noupdate -group {Execution Stage} /testbench/dut/hart/ifu/PCE
+add wave -noupdate /testbench/dut/core/SATP_REGW
+add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/PCE
 add wave -noupdate -group {Execution Stage} /testbench/InstrEName
-add wave -noupdate -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
-add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/priv/trap/InstrValidM
-add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/PCM
+add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/InstrE
+add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/priv/trap/InstrValidM
+add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM
 add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName
-add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/InstrM
-add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/lsu/MemAdrM
-add wave -noupdate /testbench/dut/hart/ieu/dp/ResultM
-add wave -noupdate /testbench/dut/hart/ieu/dp/ResultW
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM
-add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM
-add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM
-add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/StoreStallD
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LSUStallM
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD
-add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
-add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushD
-add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushE
-add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushM
-add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushW
-add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/hart/StallF
-add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/hart/StallD
-add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/hart/StallE
-add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/hart/StallM
-add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/hart/StallW
-add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR
-add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF
-add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]}
-add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPInstrClassE[0]}
-add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredDirWrongE
+add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM
+add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/lsu/MemAdrM
+add wave -noupdate /testbench/dut/core/ieu/dp/ResultM
+add wave -noupdate /testbench/dut/core/ieu/dp/ResultW
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/trap/InstrMisalignedFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/trap/InstrAccessFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/trap/IllegalInstrFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/trap/BreakpointFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/trap/LoadMisalignedFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/trap/StoreMisalignedFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/trap/LoadAccessFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/trap/StoreAccessFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/trap/EcallFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/trap/InstrPageFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/trap/LoadPageFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/trap/StorePageFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/trap/InterruptM
+add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/core/priv/trap/PendingIntsM
+add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/core/priv/trap/CommittedM
+add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/core/priv/trap/InstrValidM
+add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/BPPredWrongE
+add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/CSRWritePendingDEM
+add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM
+add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/TrapM
+add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/LoadStallD
+add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/StoreStallD
+add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/ICacheStallF
+add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM
+add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/MulDivStallD
+add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/hzu/FlushF
+add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushD
+add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushE
+add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushM
+add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushW
+add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallF
+add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallD
+add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallE
+add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallM
+add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallW
+add wave -noupdate -group Bpred -color Orange /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHR
+add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF
+add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]}
+add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPInstrClassE[0]}
+add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPPredDirWrongE
 add wave -noupdate -group Bpred -expand -group {branch update selection inputs} -divider {class check}
-add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightNonCFI
-add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassWrongCFI
-add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassWrongNonCFI
-add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPRight
-add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPWrong
-add wave -noupdate -group Bpred -radix hexadecimal -childformat {{{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} -radix binary} {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} -radix binary} {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} -radix binary} {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} -radix binary} {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} -radix binary} {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} -radix binary} {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} -radix binary}} -subitemconfig {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} {-height 16 -radix binary} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} {-height 16 -radix binary} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} {-height 16 -radix binary} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} {-height 16 -radix binary} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} {-height 16 -radix binary} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} {-height 16 -radix binary} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} {-height 16 -radix binary}} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel
-add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRNext
-add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRUpdateEN
-add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr
-add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr0
-add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr1
-add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateEN
-add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRLookup
-add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/PCNextF
-add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/PHT/RA1
-add wave -noupdate -group Bpred -expand -group prediction -radix binary /testbench/dut/hart/ifu/bpred/bpred/BPPredF
-add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/BTBValidF
-add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/BPInstrClassF
-add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/BTBPredPCF
-add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/RASPCF
-add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/LookUpPCIndex
-add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/TargetPC
-add wave -noupdate -group Bpred -expand -group prediction -expand -group ex -radix binary /testbench/dut/hart/ifu/bpred/bpred/BPPredE
-add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/hart/ifu/bpred/bpred/PCSrcE
-add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/hart/ifu/bpred/bpred/BPPredDirWrongE
-add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/UpdatePCIndex
-add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/UpdateTarget
-add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/UpdateEN
-add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/UpdatePC
-add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/UpdateTarget
-add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr
-add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/PCE
-add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/PHT/WA1
-add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/TargetWrongE
-add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/FallThroughWrongE
-add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/PredictionPCWrongE
-add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/InstrClassE
-add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/PredictionInstrClassWrongE
-add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/BPPredClassNonCFIWrongE
-add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/BPPredWrongE
-add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/BPPredWrongE
+add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightNonCFI
+add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassWrongCFI
+add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassWrongNonCFI
+add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPRight
+add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPWrong
+add wave -noupdate -group Bpred -radix hexadecimal -childformat {{{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} -radix binary}} -subitemconfig {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} {-height 16 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} {-height 16 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} {-height 16 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} {-height 16 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} {-height 16 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} {-height 16 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} {-height 16 -radix binary}} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel
+add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNext
+add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRUpdateEN
+add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr
+add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr0
+add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr1
+add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateEN
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRLookup
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCNextF
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHT/RA1
+add wave -noupdate -group Bpred -expand -group prediction -radix binary /testbench/dut/core/ifu/bpred/bpred/BPPredF
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBValidF
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BPInstrClassF
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBPredPCF
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/LookUpPCIndex
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/TargetPC
+add wave -noupdate -group Bpred -expand -group prediction -expand -group ex -radix binary /testbench/dut/core/ifu/bpred/bpred/BPPredE
+add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE
+add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/BPPredDirWrongE
+add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdatePCIndex
+add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateTarget
+add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateEN
+add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdatePC
+add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateTarget
+add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr
+add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCE
+add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHT/WA1
+add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/TargetWrongE
+add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/FallThroughWrongE
+add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionPCWrongE
+add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/InstrClassE
+add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionInstrClassWrongE
+add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredClassNonCFIWrongE
+add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE
+add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE
 add wave -noupdate -group {instruction pipeline} /testbench/InstrFName
-add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/icache/FinalInstrRawF
-add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrD
-add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrE
-add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrM
+add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/icache/FinalInstrRawF
+add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD
+add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrE
+add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrM
 add wave -noupdate -group {instruction pipeline} /testbench/InstrW
-add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNextF
-add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCF
-add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCPlus2or4F
-add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredPCF
-add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext0F
-add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext1F
-add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/SelBPPredF
-add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredWrongE
-add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PrivilegedChangePCM
-add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ifu/InstrD
+add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF
+add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF
+add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCPlus2or4F
+add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/BPPredPCF
+add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNext0F
+add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNext1F
+add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/SelBPPredF
+add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/BPPredWrongE
+add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PrivilegedChangePCM
+add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/InstrD
 add wave -noupdate -group {Decode Stage} /testbench/InstrDName
-add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD
-add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/RdD
-add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs1D
-add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs2D
-add wave -noupdate -group RegFile -expand /testbench/dut/hart/ieu/dp/regf/rf
-add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a1
-add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a2
-add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a3
-add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rd1
-add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rd2
-add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/we3
-add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/wd3
-add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ReadDataW
-add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW
-add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW
-add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW
-add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/A
-add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/B
-add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/ALUControl
-add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/result
-add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/FlagsE
+add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/RegWriteD
+add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/RdD
+add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs1D
+add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs2D
+add wave -noupdate -group RegFile -expand /testbench/dut/core/ieu/dp/regf/rf
+add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a1
+add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a2
+add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a3
+add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/rd1
+add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/rd2
+add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/we3
+add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/wd3
+add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ReadDataW
+add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/CSRReadValW
+add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ResultSrcW
+add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ResultW
+add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/A
+add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/B
+add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/ALUControl
+add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/result
+add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/FlagsE
 add wave -noupdate -group alu -divider internals
-add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/overflow
-add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/carry
-add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/zero
-add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/neg
-add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/lt
-add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/ltu
-add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1D
-add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs2D
-add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1E
-add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs2E
-add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/RdE
-add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/RdM
-add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/RdW
-add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/MemReadE
-add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/RegWriteM
-add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/RegWriteW
-add wave -noupdate -group Forward -color Thistle /testbench/dut/hart/ieu/fw/ForwardAE
-add wave -noupdate -group Forward -color Thistle /testbench/dut/hart/ieu/fw/ForwardBE
-add wave -noupdate -group Forward -color Thistle /testbench/dut/hart/ieu/fw/LoadStallD
-add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/WriteDataE
-add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/ALUResultE
-add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcAE
-add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcBE
-add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCNextF
-add wave -noupdate -group PCS /testbench/dut/hart/PCF
-add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCD
-add wave -noupdate -group PCS /testbench/dut/hart/PCE
-add wave -noupdate -group PCS /testbench/dut/hart/PCM
+add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/overflow
+add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/carry
+add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/zero
+add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/neg
+add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/lt
+add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/ltu
+add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs1D
+add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs2D
+add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs1E
+add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs2E
+add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdE
+add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdM
+add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdW
+add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/MemReadE
+add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RegWriteM
+add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RegWriteW
+add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/ForwardAE
+add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/ForwardBE
+add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/LoadStallD
+add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/WriteDataE
+add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/ALUResultE
+add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcAE
+add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcBE
+add wave -noupdate -group PCS /testbench/dut/core/ifu/PCNextF
+add wave -noupdate -group PCS /testbench/dut/core/PCF
+add wave -noupdate -group PCS /testbench/dut/core/ifu/PCD
+add wave -noupdate -group PCS /testbench/dut/core/PCE
+add wave -noupdate -group PCS /testbench/dut/core/PCM
 add wave -noupdate -group PCS /testbench/PCW
-add wave -noupdate -group muldiv /testbench/dut/hart/mdu/Funct3E
-add wave -noupdate -group muldiv /testbench/dut/hart/mdu/MulDivE
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-add wave -noupdate -group muldiv /testbench/dut/hart/mdu/StallM
-add wave -noupdate -group muldiv /testbench/dut/hart/mdu/StallW
-add wave -noupdate -group muldiv /testbench/dut/hart/mdu/FlushM
-add wave -noupdate -group muldiv /testbench/dut/hart/mdu/FlushW
-add wave -noupdate -group muldiv /testbench/dut/hart/mdu/MulDivResultW
-add wave -noupdate -group muldiv /testbench/dut/hart/mdu/DivBusyE
-add wave -noupdate -group icache -color Gold /testbench/dut/hart/ifu/icache/controller/CurrState
-add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/BasePAdrF
-add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/WayHit
-add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/VictimWay
-add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/ifu/icache/MemWay[0]/WriteEnable}
-add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/ifu/icache/MemWay[0]/SetValid}
-add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/hart/ifu/icache/MemWay[0]/CacheTagMem/StoredData}
-add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/ifu/icache/MemWay[0]/ValidBits}
-add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[0]/CacheDataMem/StoredData}
-add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
-add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[1]/CacheDataMem/StoredData}
-add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
-add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word2 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
-add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word2 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[2]/CacheDataMem/StoredData}
-add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
-add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[3]/CacheDataMem/StoredData}
-add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/controller/NextState
-add wave -noupdate -group icache /testbench/dut/hart/ifu/ITLBMissF
-add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/ITLBWriteF
-add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/ReadLineF
-add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/ReadLineF
-add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/BasePAdrF
-add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/hit
-add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spill
-add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/ICacheStallF
-add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
-add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
-add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntReset
-add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PreCntEn
-add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntEn
-add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/InstrPAdrF
-add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/InstrInF
-add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag
-add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/FetchCount
-add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrReadF
-add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrAckF
-add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable
-add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/ICacheMemWriteData
-add wave -noupdate -group AHB -color Gold /testbench/dut/hart/ebu/BusState
-add wave -noupdate -group AHB /testbench/dut/hart/ebu/NextBusState
-add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/AtomicMaskedM
-add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/InstrReadF
-add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/MemSizeM
-add wave -noupdate -group AHB /testbench/dut/hart/ebu/HCLK
-add wave -noupdate -group AHB /testbench/dut/hart/ebu/HRESETn
-add wave -noupdate -group AHB /testbench/dut/hart/ebu/HRDATA
-add wave -noupdate -group AHB /testbench/dut/hart/ebu/HREADY
-add wave -noupdate -group AHB /testbench/dut/hart/ebu/HRESP
-add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDR
-add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWDATA
-add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITE
-add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZE
-add wave -noupdate -group AHB /testbench/dut/hart/ebu/HBURST
-add wave -noupdate -group AHB /testbench/dut/hart/ebu/HPROT
-add wave -noupdate -group AHB /testbench/dut/hart/ebu/HTRANS
-add wave -noupdate -group AHB /testbench/dut/hart/ebu/HMASTLOCK
-add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDRD
-add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED
-add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED
-add wave -noupdate -group lsu -expand -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/SelPTW
-add wave -noupdate -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu.bus.dcache/dcachefsm/CurrState
-add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu.bus.dcache/WalkerPageFaultM
-add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu.bus.dcache/WriteDataM
-add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu.bus.dcache/SRAMBlockWriteEnableM
-add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu.bus.dcache/SRAMWordWriteEnableM
-add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu.bus.dcache/SRAMWayWriteEnable
-add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu.bus.dcache/SRAMWordEnable
-add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu.bus.dcache/SRAMBlockWayWriteEnableM
-add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu.bus.dcache/SelAdrM
-add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu.bus.dcache/ReadDataBlockM
-add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu.bus.dcache/DCacheMemWriteData
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu.bus.dcache/MemWay[0]/WriteEnable}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu.bus.dcache/MemWay[0]/SetValid}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu.bus.dcache/MemWay[0]/SetDirty}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu.bus.dcache/MemWay[0]/CacheTagMem/StoredData}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu.bus.dcache/MemWay[0]/DirtyBits}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu.bus.dcache/MemWay[0]/ValidBits}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu.bus.dcache/MemWay[0]/word[0]/CacheDataMem/StoredData}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu.bus.dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu.bus.dcache/MemWay[0]/word[1]/CacheDataMem/StoredData}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu.bus.dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu.bus.dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu.bus.dcache/MemWay[0]/word[2]/CacheDataMem/StoredData}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu.bus.dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu.bus.dcache/MemWay[0]/word[3]/CacheDataMem/StoredData}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu.bus.dcache/MemWay[1]/DirtyBits}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu.bus.dcache/MemWay[1]/SetDirty}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu.bus.dcache/MemWay[1]/WriteEnable}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu.bus.dcache/MemWay[1]/WriteWordEnable}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/hart/lsu.bus.dcache/MemWay[1]/CacheTagMem/StoredData}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu.bus.dcache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu.bus.dcache/MemWay[1]/word[0]/CacheDataMem/StoredData}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu.bus.dcache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu.bus.dcache/MemWay[1]/word[1]/CacheDataMem/StoredData}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu.bus.dcache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu.bus.dcache/MemWay[1]/word[2]/CacheDataMem/StoredData}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu.bus.dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu.bus.dcache/MemWay[1]/word[3]/CacheDataMem/StoredData}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu.bus.dcache/MemWay[2]/WriteEnable}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu.bus.dcache/MemWay[2]/SetValid}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu.bus.dcache/MemWay[2]/SetDirty}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/hart/lsu.bus.dcache/MemWay[2]/CacheTagMem/StoredData}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu.bus.dcache/MemWay[2]/DirtyBits}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu.bus.dcache/MemWay[2]/ValidBits}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu.bus.dcache/MemWay[2]/word[0]/CacheDataMem/StoredData}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu.bus.dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu.bus.dcache/MemWay[2]/word[1]/CacheDataMem/StoredData}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu.bus.dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu.bus.dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu.bus.dcache/MemWay[2]/word[2]/CacheDataMem/StoredData}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu.bus.dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu.bus.dcache/MemWay[2]/word[3]/CacheDataMem/StoredData}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu.bus.dcache/MemWay[3]/WriteEnable}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu.bus.dcache/MemWay[3]/SetValid}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu.bus.dcache/MemWay[3]/SetDirty}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/hart/lsu.bus.dcache/MemWay[3]/CacheTagMem/StoredData}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu.bus.dcache/MemWay[3]/DirtyBits}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu.bus.dcache/MemWay[3]/ValidBits}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu.bus.dcache/MemWay[3]/word[0]/CacheDataMem/StoredData}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu.bus.dcache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu.bus.dcache/MemWay[3]/word[1]/CacheDataMem/StoredData}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu.bus.dcache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu.bus.dcache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu.bus.dcache/MemWay[3]/word[2]/CacheDataMem/StoredData}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu.bus.dcache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu.bus.dcache/MemWay[3]/word[3]/CacheDataMem/StoredData}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/hart/lsu.bus.dcache/SetValid
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/hart/lsu.bus.dcache/ClearValid
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/hart/lsu.bus.dcache/SetDirty
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/hart/lsu.bus.dcache/ClearDirty
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/hart/lsu.bus.dcache/MemWay[0]/WayHit}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/hart/lsu.bus.dcache/MemWay[0]/Valid}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/hart/lsu.bus.dcache/MemWay[0]/Dirty}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/hart/lsu.bus.dcache/MemWay[0]/ReadTag}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu.bus.dcache/MemWay[1]/WayHit}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu.bus.dcache/MemWay[1]/Valid}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu.bus.dcache/MemWay[1]/Dirty}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu.bus.dcache/MemWay[1]/ReadTag}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu.bus.dcache/MemWay[2]/WayHit}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu.bus.dcache/MemWay[2]/Valid}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu.bus.dcache/MemWay[2]/Dirty}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu.bus.dcache/MemWay[2]/ReadTag}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu.bus.dcache/MemWay[3]/WayHit}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu.bus.dcache/MemWay[3]/Valid}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu.bus.dcache/MemWay[3]/Dirty}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu.bus.dcache/MemWay[3]/ReadTag}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu.bus.dcache/WayHit
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu.bus.dcache/ReadDataBlockWayMaskedM
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu.bus.dcache/ReadDataWordM
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu.bus.dcache/ReadDataWordMuxM
-add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu.bus.dcache/VictimTag
-add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu.bus.dcache/VictimWay
-add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu.bus.dcache/VictimDirtyWay
-add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu.bus.dcache/VictimDirty
-add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu.bus.dcache/MemRWM
-add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu.bus.dcache/MemAdrE
-add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu.bus.dcache/MemPAdrM
-add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu.bus.dcache/Funct3M
-add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu.bus.dcache/Funct7M
-add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu.bus.dcache/AtomicM
-add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu.bus.dcache/FlushDCacheM
-add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu.bus.dcache/CacheableM
-add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu.bus.dcache/WriteDataM
-add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu.bus.dcache/ReadDataM
-add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu.bus.dcache/DCacheStallM
-add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu.bus.dcache/FlushAdrFlag
-add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu.bus.dcache/WayHit
-add wave -noupdate -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu.bus.dcache/CacheHit
-add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu.bus.dcache/FetchCount
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu.bus.dcache/FetchCountFlag
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu.bus.dcache/AHBPAdr
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu.bus.dcache/AHBRead
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu.bus.dcache/AHBWrite
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu.bus.dcache/AHBAck
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu.bus.dcache/HRDATA
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu.bus.dcache/HWDATA
-add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode
-add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate
-add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation
-add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss
-add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/TLBHit
-add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress
-add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/TLBPageFault
-add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/LoadAccessFaultM
-add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/StoreAccessFaultM
-add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/TLBPAdr
-add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/PTE
-add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/TLBWrite
-add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/PhysicalAddress
-add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/SelRegions
-add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/Cacheable
-add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/Idempotent
-add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/AtomicAllowed
-add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/PMAAccessFault
-add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMAInstrAccessFaultF
-add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMALoadAccessFaultM
-add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMAStoreAccessFaultM
-add wave -noupdate -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPInstrAccessFaultF
-add wave -noupdate -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPLoadAccessFaultM
-add wave -noupdate -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPStoreAccessFaultM
-add wave -noupdate -group lsu -group ptwalker -color Gold /testbench/dut/hart/lsu/hptw/genblk1/WalkerState
-add wave -noupdate -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/PCF
-add wave -noupdate -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/genblk1/TranslationVAdr
-add wave -noupdate -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/TranslationPAdr
-add wave -noupdate -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/HPTWReadPTE
-add wave -noupdate -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/PTE
-add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/ITLBMissF
-add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/DTLBMissM
-add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/ITLBWriteF
-add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/DTLBWriteM
-add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerInstrPageFaultF
-add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerLoadPageFaultM
-add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerStorePageFaultM
-add wave -noupdate -group csr /testbench/dut/hart/priv/csr/MIP_REGW
-add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/TLBWrite
-add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF
-add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress
-add wave -noupdate /testbench/dut/hart/lsu.bus.dcache/VAdr
-add wave -noupdate /testbench/dut/hart/lsu.bus.dcache/MemPAdrM
+add wave -noupdate -group muldiv /testbench/dut/core/mdu/Funct3E
+add wave -noupdate -group muldiv /testbench/dut/core/mdu/MulDivE
+add wave -noupdate -group muldiv /testbench/dut/core/mdu/W64E
+add wave -noupdate -group muldiv /testbench/dut/core/mdu/StallM
+add wave -noupdate -group muldiv /testbench/dut/core/mdu/StallW
+add wave -noupdate -group muldiv /testbench/dut/core/mdu/FlushM
+add wave -noupdate -group muldiv /testbench/dut/core/mdu/FlushW
+add wave -noupdate -group muldiv /testbench/dut/core/mdu/MulDivResultW
+add wave -noupdate -group muldiv /testbench/dut/core/mdu/DivBusyE
+add wave -noupdate -group icache -color Gold /testbench/dut/core/ifu/icache/controller/CurrState
+add wave -noupdate -group icache /testbench/dut/core/ifu/icache/BasePAdrF
+add wave -noupdate -group icache /testbench/dut/core/ifu/icache/WayHit
+add wave -noupdate -group icache /testbench/dut/core/ifu/icache/VictimWay
+add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/core/ifu/icache/MemWay[0]/WriteEnable}
+add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/core/ifu/icache/MemWay[0]/SetValid}
+add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/core/ifu/icache/MemWay[0]/CacheTagMem/StoredData}
+add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/core/ifu/icache/MemWay[0]/ValidBits}
+add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/core/ifu/icache/MemWay[0]/word[0]/CacheDataMem/StoredData}
+add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/core/ifu/icache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
+add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/core/ifu/icache/MemWay[0]/word[1]/CacheDataMem/StoredData}
+add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/core/ifu/icache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
+add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word2 {/testbench/dut/core/ifu/icache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
+add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word2 {/testbench/dut/core/ifu/icache/MemWay[0]/word[2]/CacheDataMem/StoredData}
+add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/core/ifu/icache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
+add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/core/ifu/icache/MemWay[0]/word[3]/CacheDataMem/StoredData}
+add wave -noupdate -group icache /testbench/dut/core/ifu/icache/controller/NextState
+add wave -noupdate -group icache /testbench/dut/core/ifu/ITLBMissF
+add wave -noupdate -group icache /testbench/dut/core/ifu/icache/ITLBWriteF
+add wave -noupdate -group icache /testbench/dut/core/ifu/icache/ReadLineF
+add wave -noupdate -group icache /testbench/dut/core/ifu/icache/ReadLineF
+add wave -noupdate -group icache /testbench/dut/core/ifu/icache/BasePAdrF
+add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/icache/controller/hit
+add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/icache/controller/spill
+add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/icache/controller/ICacheStallF
+add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/icache/controller/spillSave
+add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/icache/controller/spillSave
+add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/icache/controller/CntReset
+add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/icache/controller/PreCntEn
+add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/icache/controller/CntEn
+add wave -noupdate -group icache -expand -group memory /testbench/dut/core/ifu/icache/InstrPAdrF
+add wave -noupdate -group icache -expand -group memory /testbench/dut/core/ifu/icache/InstrInF
+add wave -noupdate -group icache -expand -group memory /testbench/dut/core/ifu/icache/controller/FetchCountFlag
+add wave -noupdate -group icache -expand -group memory /testbench/dut/core/ifu/icache/FetchCount
+add wave -noupdate -group icache -expand -group memory /testbench/dut/core/ifu/icache/controller/InstrReadF
+add wave -noupdate -group icache -expand -group memory /testbench/dut/core/ifu/icache/controller/InstrAckF
+add wave -noupdate -group icache -expand -group memory /testbench/dut/core/ifu/icache/controller/ICacheMemWriteEnable
+add wave -noupdate -group icache -expand -group memory /testbench/dut/core/ifu/icache/ICacheMemWriteData
+add wave -noupdate -group AHB -color Gold /testbench/dut/core/ebu/BusState
+add wave -noupdate -group AHB /testbench/dut/core/ebu/NextBusState
+add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/core/ebu/AtomicMaskedM
+add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/core/ebu/InstrReadF
+add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/core/ebu/MemSizeM
+add wave -noupdate -group AHB /testbench/dut/core/ebu/HCLK
+add wave -noupdate -group AHB /testbench/dut/core/ebu/HRESETn
+add wave -noupdate -group AHB /testbench/dut/core/ebu/HRDATA
+add wave -noupdate -group AHB /testbench/dut/core/ebu/HREADY
+add wave -noupdate -group AHB /testbench/dut/core/ebu/HRESP
+add wave -noupdate -group AHB /testbench/dut/core/ebu/HADDR
+add wave -noupdate -group AHB /testbench/dut/core/ebu/HWDATA
+add wave -noupdate -group AHB /testbench/dut/core/ebu/HWRITE
+add wave -noupdate -group AHB /testbench/dut/core/ebu/HSIZE
+add wave -noupdate -group AHB /testbench/dut/core/ebu/HBURST
+add wave -noupdate -group AHB /testbench/dut/core/ebu/HPROT
+add wave -noupdate -group AHB /testbench/dut/core/ebu/HTRANS
+add wave -noupdate -group AHB /testbench/dut/core/ebu/HMASTLOCK
+add wave -noupdate -group AHB /testbench/dut/core/ebu/HADDRD
+add wave -noupdate -group AHB /testbench/dut/core/ebu/HSIZED
+add wave -noupdate -group AHB /testbench/dut/core/ebu/HWRITED
+add wave -noupdate -group lsu -expand -group {LSU ARB} /testbench/dut/core/lsu/arbiter/SelPTW
+add wave -noupdate -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu.bus.dcache/dcachefsm/CurrState
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/WalkerPageFaultM
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/WriteDataM
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/SRAMBlockWriteEnableM
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/SRAMWordWriteEnableM
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/SRAMWayWriteEnable
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/SRAMWordEnable
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/SRAMBlockWayWriteEnableM
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/SelAdrM
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/ReadDataBlockM
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/DCacheMemWriteData
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/MemWay[0]/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/MemWay[0]/SetValid}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/MemWay[0]/SetDirty}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu.bus.dcache/MemWay[0]/CacheTagMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/MemWay[0]/DirtyBits}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/MemWay[0]/ValidBits}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu.bus.dcache/MemWay[0]/word[0]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu.bus.dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu.bus.dcache/MemWay[0]/word[1]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu.bus.dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu.bus.dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu.bus.dcache/MemWay[0]/word[2]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu.bus.dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu.bus.dcache/MemWay[0]/word[3]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/MemWay[1]/DirtyBits}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/MemWay[1]/SetDirty}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/MemWay[1]/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/MemWay[1]/WriteWordEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/core/lsu.bus.dcache/MemWay[1]/CacheTagMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu.bus.dcache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu.bus.dcache/MemWay[1]/word[0]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu.bus.dcache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu.bus.dcache/MemWay[1]/word[1]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu.bus.dcache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu.bus.dcache/MemWay[1]/word[2]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu.bus.dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu.bus.dcache/MemWay[1]/word[3]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/MemWay[2]/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/MemWay[2]/SetValid}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/MemWay[2]/SetDirty}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/core/lsu.bus.dcache/MemWay[2]/CacheTagMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/MemWay[2]/DirtyBits}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/MemWay[2]/ValidBits}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu.bus.dcache/MemWay[2]/word[0]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu.bus.dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu.bus.dcache/MemWay[2]/word[1]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu.bus.dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu.bus.dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu.bus.dcache/MemWay[2]/word[2]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu.bus.dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu.bus.dcache/MemWay[2]/word[3]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/MemWay[3]/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/MemWay[3]/SetValid}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/MemWay[3]/SetDirty}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu.bus.dcache/MemWay[3]/CacheTagMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/MemWay[3]/DirtyBits}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/MemWay[3]/ValidBits}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu.bus.dcache/MemWay[3]/word[0]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu.bus.dcache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu.bus.dcache/MemWay[3]/word[1]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu.bus.dcache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu.bus.dcache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu.bus.dcache/MemWay[3]/word[2]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu.bus.dcache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu.bus.dcache/MemWay[3]/word[3]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/core/lsu.bus.dcache/SetValid
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/core/lsu.bus.dcache/ClearValid
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/core/lsu.bus.dcache/SetDirty
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/core/lsu.bus.dcache/ClearDirty
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu.bus.dcache/MemWay[0]/WayHit}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu.bus.dcache/MemWay[0]/Valid}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu.bus.dcache/MemWay[0]/Dirty}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu.bus.dcache/MemWay[0]/ReadTag}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/MemWay[1]/WayHit}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/MemWay[1]/Valid}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/MemWay[1]/Dirty}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/MemWay[1]/ReadTag}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/MemWay[2]/WayHit}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/MemWay[2]/Valid}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/MemWay[2]/Dirty}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/MemWay[2]/ReadTag}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/MemWay[3]/WayHit}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/MemWay[3]/Valid}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/MemWay[3]/Dirty}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/MemWay[3]/ReadTag}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu.bus.dcache/WayHit
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu.bus.dcache/ReadDataBlockWayMaskedM
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu.bus.dcache/ReadDataWordM
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu.bus.dcache/ReadDataWordMuxM
+add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu.bus.dcache/VictimTag
+add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu.bus.dcache/VictimWay
+add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu.bus.dcache/VictimDirtyWay
+add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu.bus.dcache/VictimDirty
+add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu.bus.dcache/MemRWM
+add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu.bus.dcache/MemAdrE
+add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu.bus.dcache/MemPAdrM
+add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu.bus.dcache/Funct3M
+add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu.bus.dcache/Funct7M
+add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu.bus.dcache/AtomicM
+add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu.bus.dcache/FlushDCacheM
+add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu.bus.dcache/CacheableM
+add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu.bus.dcache/WriteDataM
+add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu.bus.dcache/ReadDataM
+add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu.bus.dcache/DCacheStallM
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/FlushAdrFlag
+add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/core/lsu.bus.dcache/WayHit
+add wave -noupdate -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu.bus.dcache/CacheHit
+add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/core/lsu.bus.dcache/FetchCount
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu.bus.dcache/FetchCountFlag
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu.bus.dcache/AHBPAdr
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu.bus.dcache/AHBRead
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu.bus.dcache/AHBWrite
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu.bus.dcache/AHBAck
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu.bus.dcache/HRDATA
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu.bus.dcache/HWDATA
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/TLBMiss
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/TLBHit
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/PhysicalAddress
+add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/TLBPageFault
+add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/LoadAccessFaultM
+add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/StoreAccessFaultM
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/genblk1/tlb/TLBPAdr
+add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/genblk1/tlb/PTE
+add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/genblk1/tlb/TLBWrite
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/pmachecker/PhysicalAddress
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/pmachecker/SelRegions
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/Cacheable
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/Idempotent
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/AtomicAllowed
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/pmachecker/PMAAccessFault
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/PMAInstrAccessFaultF
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/PMALoadAccessFaultM
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/PMAStoreAccessFaultM
+add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/PMPInstrAccessFaultF
+add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/PMPLoadAccessFaultM
+add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/PMPStoreAccessFaultM
+add wave -noupdate -group lsu -group ptwalker -color Gold /testbench/dut/core/lsu/hptw/genblk1/WalkerState
+add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/PCF
+add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/genblk1/TranslationVAdr
+add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/TranslationPAdr
+add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/HPTWReadPTE
+add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/PTE
+add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/ITLBMissF
+add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/DTLBMissM
+add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/ITLBWriteF
+add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/DTLBWriteM
+add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/WalkerInstrPageFaultF
+add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/WalkerLoadPageFaultM
+add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/WalkerStorePageFaultM
+add wave -noupdate -group csr /testbench/dut/core/priv/csr/MIP_REGW
+add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/TLBWrite
+add wave -noupdate -group itlb /testbench/dut/core/ifu/ITLBMissF
+add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/PhysicalAddress
+add wave -noupdate /testbench/dut/core/lsu.bus.dcache/VAdr
+add wave -noupdate /testbench/dut/core/lsu.bus.dcache/MemPAdrM
 add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HCLK
 add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HSELPLIC
 add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HADDR
@@ -461,27 +461,27 @@ add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HSELUART
 add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HADDR
 add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWRITE
 add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWDATA
-add wave -noupdate -radix unsigned /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/CYCLE_REGW
-add wave -noupdate -radix unsigned /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/INSTRET_REGW
-add wave -noupdate -label LoadStall -radix unsigned {/testbench/dut/hart/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW[3]}
-add wave -noupdate -label {Branch Instr} -radix unsigned {/testbench/dut/hart/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW[5]}
-add wave -noupdate -label {BP Dir Wrong} -radix unsigned {/testbench/dut/hart/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW[4]}
-add wave -noupdate -label {Jump, Jal, Jalr} -radix unsigned {/testbench/dut/hart/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW[7]}
-add wave -noupdate -label {RAS Wrong} -radix unsigned {/testbench/dut/hart/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW[8]}
-add wave -noupdate -label {BTB Wrong} -radix unsigned {/testbench/dut/hart/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW[6]}
-add wave -noupdate -label {BP Class Non CFI Wrong} -radix unsigned {/testbench/dut/hart/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW[10]}
-add wave -noupdate -label DCacheAccess -radix unsigned {/testbench/dut/hart/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW[11]}
-add wave -noupdate -label DCacheMiss -radix unsigned {/testbench/dut/hart/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW[12]}
-add wave -noupdate -label Return -radix unsigned {/testbench/dut/hart/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW[9]}
-add wave -noupdate /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW
-add wave -noupdate /testbench/dut/hart/priv/csr/genblk1/counters/MCOUNTINHIBIT_REGW
-add wave -noupdate /testbench/dut/hart/priv/csr/genblk1/counters/InstrValidM
-add wave -noupdate /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/InstrValidNotFlushedM
-add wave -noupdate /testbench/dut/hart/priv/csr/genblk1/counters/BPPredDirWrongM
-add wave -noupdate /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/genblk1/genblk1/LoadStallM
-add wave -noupdate /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/genblk1/NextHPMCOUNTERM
-add wave -noupdate /testbench/dut/hart/priv/csr/genblk1/counters/DCacheMiss
-add wave -noupdate /testbench/dut/hart/priv/csr/genblk1/counters/DCacheAccess
+add wave -noupdate -radix unsigned /testbench/dut/core/priv/csr/genblk1/counters/genblk1/CYCLE_REGW
+add wave -noupdate -radix unsigned /testbench/dut/core/priv/csr/genblk1/counters/genblk1/INSTRET_REGW
+add wave -noupdate -label LoadStall -radix unsigned {/testbench/dut/core/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW[3]}
+add wave -noupdate -label {Branch Instr} -radix unsigned {/testbench/dut/core/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW[5]}
+add wave -noupdate -label {BP Dir Wrong} -radix unsigned {/testbench/dut/core/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW[4]}
+add wave -noupdate -label {Jump, Jal, Jalr} -radix unsigned {/testbench/dut/core/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW[7]}
+add wave -noupdate -label {RAS Wrong} -radix unsigned {/testbench/dut/core/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW[8]}
+add wave -noupdate -label {BTB Wrong} -radix unsigned {/testbench/dut/core/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW[6]}
+add wave -noupdate -label {BP Class Non CFI Wrong} -radix unsigned {/testbench/dut/core/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW[10]}
+add wave -noupdate -label DCacheAccess -radix unsigned {/testbench/dut/core/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW[11]}
+add wave -noupdate -label DCacheMiss -radix unsigned {/testbench/dut/core/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW[12]}
+add wave -noupdate -label Return -radix unsigned {/testbench/dut/core/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW[9]}
+add wave -noupdate /testbench/dut/core/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW
+add wave -noupdate /testbench/dut/core/priv/csr/genblk1/counters/MCOUNTINHIBIT_REGW
+add wave -noupdate /testbench/dut/core/priv/csr/genblk1/counters/InstrValidM
+add wave -noupdate /testbench/dut/core/priv/csr/genblk1/counters/genblk1/InstrValidNotFlushedM
+add wave -noupdate /testbench/dut/core/priv/csr/genblk1/counters/BPPredDirWrongM
+add wave -noupdate /testbench/dut/core/priv/csr/genblk1/counters/genblk1/genblk1/genblk1/LoadStallM
+add wave -noupdate /testbench/dut/core/priv/csr/genblk1/counters/genblk1/genblk1/NextHPMCOUNTERM
+add wave -noupdate /testbench/dut/core/priv/csr/genblk1/counters/DCacheMiss
+add wave -noupdate /testbench/dut/core/priv/csr/genblk1/counters/DCacheAccess
 TreeUpdate [SetDefaultTree]
 WaveRestoreCursors {{Cursor 6} {17923831 ns} 0}
 quietly wave cursor active 1

pipelined/regression/wave-dos/ahb-muldiv.do

@@ -7,79 +7,79 @@ add wave /testbench/reset
 add wave -divider
 
 # new
-#add wave /testbench/dut/hart/ebu/IReadF
-add wave /testbench/dut/hart/DataStall
-add wave /testbench/dut/hart/ICacheStallF
-add wave /testbench/dut/hart/StallF
-add wave /testbench/dut/hart/StallD
+#add wave /testbench/dut/core/ebu/IReadF
+add wave /testbench/dut/core/DataStall
+add wave /testbench/dut/core/ICacheStallF
+add wave /testbench/dut/core/StallF
+add wave /testbench/dut/core/StallD
 
-add wave /testbench/dut/hart/StallE
-add wave /testbench/dut/hart/StallM
-add wave /testbench/dut/hart/StallW
-add wave /testbench/dut/hart/FlushD
-add wave /testbench/dut/hart/FlushE
-add wave /testbench/dut/hart/FlushM
-add wave /testbench/dut/hart/FlushW
+add wave /testbench/dut/core/StallE
+add wave /testbench/dut/core/StallM
+add wave /testbench/dut/core/StallW
+add wave /testbench/dut/core/FlushD
+add wave /testbench/dut/core/FlushE
+add wave /testbench/dut/core/FlushM
+add wave /testbench/dut/core/FlushW
 
 add wave -noupdate -divider -height 32 "MulDiv"
-add wave -hex /testbench/dut/hart/mdu/*
+add wave -hex /testbench/dut/core/mdu/*
 
 add wave -noupdate -divider -height 32 "Integer Divider"
-add wave -hex /testbench/dut/hart/mdu/genblk1/div/fsm1/CURRENT_STATE
-add wave -hex /testbench/dut/hart/mdu/genblk1/div/fsm1/NEXT_STATE
-add wave -hex /testbench/dut/hart/mdu/genblk1/div/*
+add wave -hex /testbench/dut/core/mdu/genblk1/div/fsm1/CURRENT_STATE
+add wave -hex /testbench/dut/core/mdu/genblk1/div/fsm1/NEXT_STATE
+add wave -hex /testbench/dut/core/mdu/genblk1/div/*
 
 add wave -noupdate -divider -height 32 "RF"
-add wave -hex /testbench/dut/hart/ieu/dp/regf/*
-add wave -hex /testbench/dut/hart/ieu/dp/regf/rf
+add wave -hex /testbench/dut/core/ieu/dp/regf/*
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf
 
 add wave -divider
-add wave -hex /testbench/dut/hart/ifu/PCF
-add wave -hex /testbench/dut/hart/ifu/PCD
-add wave -hex /testbench/dut/hart/ifu/InstrD
+add wave -hex /testbench/dut/core/ifu/PCF
+add wave -hex /testbench/dut/core/ifu/PCD
+add wave -hex /testbench/dut/core/ifu/InstrD
 add wave /testbench/InstrDName
 add wave -divider
 
-add wave -hex /testbench/dut/hart/ifu/PCE
-add wave -hex /testbench/dut/hart/ifu/InstrE
+add wave -hex /testbench/dut/core/ifu/PCE
+add wave -hex /testbench/dut/core/ifu/InstrE
 add wave /testbench/InstrEName
-add wave -hex /testbench/dut/hart/ieu/dp/SrcAE
-add wave -hex /testbench/dut/hart/ieu/dp/SrcBE
-add wave -hex /testbench/dut/hart/ieu/dp/ALUResultE
-#add wave /testbench/dut/hart/ieu/dp/PCSrcE
+add wave -hex /testbench/dut/core/ieu/dp/SrcAE
+add wave -hex /testbench/dut/core/ieu/dp/SrcBE
+add wave -hex /testbench/dut/core/ieu/dp/ALUResultE
+#add wave /testbench/dut/core/ieu/dp/PCSrcE
 add wave -divider
 
-add wave -hex /testbench/dut/hart/ifu/PCM
-add wave -hex /testbench/dut/hart/ifu/InstrM
+add wave -hex /testbench/dut/core/ifu/PCM
+add wave -hex /testbench/dut/core/ifu/InstrM
 add wave /testbench/InstrMName
 add wave /testbench/dut/uncore/ram/memwrite
 add wave -hex /testbench/dut/uncore/HADDR
 add wave -hex /testbench/dut/uncore/HWDATA
 add wave -divider
 
-add wave -hex /testbench/dut/hart/ebu/MemReadM
-add wave -hex /testbench/dut/hart/ebu/InstrReadF
-add wave -hex /testbench/dut/hart/ebu/BusState
-add wave -hex /testbench/dut/hart/ebu/NextBusState
-add wave -hex /testbench/dut/hart/ebu/HADDR
-add wave -hex /testbench/dut/hart/ebu/HREADY
-add wave -hex /testbench/dut/hart/ebu/HTRANS
-add wave -hex /testbench/dut/hart/ebu/HRDATA
-add wave -hex /testbench/dut/hart/ebu/HWRITE
-add wave -hex /testbench/dut/hart/ebu/HWDATA
-add wave -hex /testbench/dut/hart/ebu/CaptureDataM
+add wave -hex /testbench/dut/core/ebu/MemReadM
+add wave -hex /testbench/dut/core/ebu/InstrReadF
+add wave -hex /testbench/dut/core/ebu/BusState
+add wave -hex /testbench/dut/core/ebu/NextBusState
+add wave -hex /testbench/dut/core/ebu/HADDR
+add wave -hex /testbench/dut/core/ebu/HREADY
+add wave -hex /testbench/dut/core/ebu/HTRANS
+add wave -hex /testbench/dut/core/ebu/HRDATA
+add wave -hex /testbench/dut/core/ebu/HWRITE
+add wave -hex /testbench/dut/core/ebu/HWDATA
+add wave -hex /testbench/dut/core/ebu/CaptureDataM
 add wave -divider
 
 add wave -hex /testbench/dut/uncore/ram/*
 add wave -divider
 
-add wave -hex /testbench/dut/hart/ifu/PCW
-add wave -hex /testbench/dut/hart/ifu/InstrW
+add wave -hex /testbench/dut/core/ifu/PCW
+add wave -hex /testbench/dut/core/ifu/InstrW
 add wave /testbench/InstrWName
-add wave /testbench/dut/hart/ieu/dp/RegWriteW
-add wave -hex /testbench/dut/hart/ebu/ReadDataW
-add wave -hex /testbench/dut/hart/ieu/dp/ResultW
-add wave -hex /testbench/dut/hart/ieu/dp/RdW
+add wave /testbench/dut/core/ieu/dp/RegWriteW
+add wave -hex /testbench/dut/core/ebu/ReadDataW
+add wave -hex /testbench/dut/core/ieu/dp/ResultW
+add wave -hex /testbench/dut/core/ieu/dp/RdW
 add wave -divider
 
 add wave -hex /testbench/dut/uncore/ram/*

pipelined/regression/wave-dos/ahb-waves.do

@@ -7,67 +7,67 @@ add wave /testbench/clk
 add wave /testbench/reset
 add wave -divider
 
-#add wave /testbench/dut/hart/ebu/IReadF
-add wave /testbench/dut/hart/DataStall
-add wave /testbench/dut/hart/ICacheStallF
-add wave /testbench/dut/hart/StallF
-add wave /testbench/dut/hart/StallD
-add wave /testbench/dut/hart/StallE
-add wave /testbench/dut/hart/StallM
-add wave /testbench/dut/hart/StallW
-add wave /testbench/dut/hart/FlushD
-add wave /testbench/dut/hart/FlushE
-add wave /testbench/dut/hart/FlushM
-add wave /testbench/dut/hart/FlushW
+#add wave /testbench/dut/core/ebu/IReadF
+add wave /testbench/dut/core/DataStall
+add wave /testbench/dut/core/ICacheStallF
+add wave /testbench/dut/core/StallF
+add wave /testbench/dut/core/StallD
+add wave /testbench/dut/core/StallE
+add wave /testbench/dut/core/StallM
+add wave /testbench/dut/core/StallW
+add wave /testbench/dut/core/FlushD
+add wave /testbench/dut/core/FlushE
+add wave /testbench/dut/core/FlushM
+add wave /testbench/dut/core/FlushW
 
 add wave -divider
-add wave -hex /testbench/dut/hart/ifu/PCF
-add wave -hex /testbench/dut/hart/ifu/PCD
-add wave -hex /testbench/dut/hart/ifu/InstrD
+add wave -hex /testbench/dut/core/ifu/PCF
+add wave -hex /testbench/dut/core/ifu/PCD
+add wave -hex /testbench/dut/core/ifu/InstrD
 add wave /testbench/InstrDName
-add wave -hex /testbench/dut/hart/ifu/ic/InstrRawD
+add wave -hex /testbench/dut/core/ifu/ic/InstrRawD
 add wave -divider
 
-add wave -hex /testbench/dut/hart/ifu/PCE
-add wave -hex /testbench/dut/hart/ifu/InstrE
+add wave -hex /testbench/dut/core/ifu/PCE
+add wave -hex /testbench/dut/core/ifu/InstrE
 add wave /testbench/InstrEName
-add wave -hex /testbench/dut/hart/ieu/dp/SrcAE
-add wave -hex /testbench/dut/hart/ieu/dp/SrcBE
-add wave -hex /testbench/dut/hart/ieu/dp/ALUResultE
-#add wave /testbench/dut/hart/ieu/dp/PCSrcE
+add wave -hex /testbench/dut/core/ieu/dp/SrcAE
+add wave -hex /testbench/dut/core/ieu/dp/SrcBE
+add wave -hex /testbench/dut/core/ieu/dp/ALUResultE
+#add wave /testbench/dut/core/ieu/dp/PCSrcE
 add wave -divider
 
-add wave -hex /testbench/dut/hart/ifu/PCM
-add wave -hex /testbench/dut/hart/ifu/InstrM
+add wave -hex /testbench/dut/core/ifu/PCM
+add wave -hex /testbench/dut/core/ifu/InstrM
 add wave /testbench/InstrMName
 add wave /testbench/dut/uncore/ram/memwrite
 add wave -hex /testbench/dut/uncore/HADDR
 add wave -hex /testbench/dut/uncore/HWDATA
 add wave -divider
 
-add wave -hex /testbench/dut/hart/ebu/MemReadM
-add wave -hex /testbench/dut/hart/ebu/InstrReadF
-add wave -hex /testbench/dut/hart/ebu/BusState
-add wave -hex /testbench/dut/hart/ebu/NextBusState
-add wave -hex /testbench/dut/hart/ebu/HADDR
-add wave -hex /testbench/dut/hart/ebu/HREADY
-add wave -hex /testbench/dut/hart/ebu/HTRANS
-add wave -hex /testbench/dut/hart/ebu/HRDATA
-add wave -hex /testbench/dut/hart/ebu/HWRITE
-add wave -hex /testbench/dut/hart/ebu/HWDATA
-add wave -hex /testbench/dut/hart/ebu/CaptureDataM
+add wave -hex /testbench/dut/core/ebu/MemReadM
+add wave -hex /testbench/dut/core/ebu/InstrReadF
+add wave -hex /testbench/dut/core/ebu/BusState
+add wave -hex /testbench/dut/core/ebu/NextBusState
+add wave -hex /testbench/dut/core/ebu/HADDR
+add wave -hex /testbench/dut/core/ebu/HREADY
+add wave -hex /testbench/dut/core/ebu/HTRANS
+add wave -hex /testbench/dut/core/ebu/HRDATA
+add wave -hex /testbench/dut/core/ebu/HWRITE
+add wave -hex /testbench/dut/core/ebu/HWDATA
+add wave -hex /testbench/dut/core/ebu/CaptureDataM
 add wave -divider
 
 add wave -hex /testbench/dut/uncore/ram/*
 add wave -divider
 
-add wave -hex /testbench/dut/hart/ifu/PCW
-add wave -hex /testbench/dut/hart/ifu/InstrW
+add wave -hex /testbench/dut/core/ifu/PCW
+add wave -hex /testbench/dut/core/ifu/InstrW
 add wave /testbench/InstrWName
-add wave /testbench/dut/hart/ieu/dp/RegWriteW
-add wave -hex /testbench/dut/hart/ebu/ReadDataW
-add wave -hex /testbench/dut/hart/ieu/dp/ResultW
-add wave -hex /testbench/dut/hart/ieu/dp/RdW
+add wave /testbench/dut/core/ieu/dp/RegWriteW
+add wave -hex /testbench/dut/core/ebu/ReadDataW
+add wave -hex /testbench/dut/core/ieu/dp/ResultW
+add wave -hex /testbench/dut/core/ieu/dp/RdW
 add wave -divider
 
 add wave -hex /testbench/dut/uncore/ram/*

pipelined/regression/wave-dos/cache-waves.do

@@ -2,75 +2,75 @@ add wave /testbench/clk
 add wave /testbench/reset
 add wave -divider
 
-#add wave /testbench/dut/hart/ebu/IReadF
-add wave /testbench/dut/hart/DataStall
-add wave /testbench/dut/hart/ICacheStallF
-add wave /testbench/dut/hart/StallF
-add wave /testbench/dut/hart/StallD
-add wave /testbench/dut/hart/StallE
-add wave /testbench/dut/hart/StallM
-add wave /testbench/dut/hart/StallW
-add wave /testbench/dut/hart/FlushD
-add wave /testbench/dut/hart/FlushE
-add wave /testbench/dut/hart/FlushM
-add wave /testbench/dut/hart/FlushW
+#add wave /testbench/dut/core/ebu/IReadF
+add wave /testbench/dut/core/DataStall
+add wave /testbench/dut/core/ICacheStallF
+add wave /testbench/dut/core/StallF
+add wave /testbench/dut/core/StallD
+add wave /testbench/dut/core/StallE
+add wave /testbench/dut/core/StallM
+add wave /testbench/dut/core/StallW
+add wave /testbench/dut/core/FlushD
+add wave /testbench/dut/core/FlushE
+add wave /testbench/dut/core/FlushM
+add wave /testbench/dut/core/FlushW
 
 add wave -divider
-add wave -hex /testbench/dut/hart/ifu/PCF
-add wave -hex /testbench/dut/hart/ifu/PCD
-add wave -hex /testbench/dut/hart/ifu/InstrD
+add wave -hex /testbench/dut/core/ifu/PCF
+add wave -hex /testbench/dut/core/ifu/PCD
+add wave -hex /testbench/dut/core/ifu/InstrD
 
 add wave /testbench/InstrDName
 add wave -divider
 
 
-add wave -hex /testbench/dut/hart/ifu/PCE
-add wave -hex /testbench/dut/hart/ifu/InstrE
+add wave -hex /testbench/dut/core/ifu/PCE
+add wave -hex /testbench/dut/core/ifu/InstrE
 add wave /testbench/InstrEName
-add wave -hex /testbench/dut/hart/ieu/dp/SrcAE
-add wave -hex /testbench/dut/hart/ieu/dp/SrcBE
-add wave -hex /testbench/dut/hart/ieu/dp/ALUResultE
-#add wave /testbench/dut/hart/ieu/dp/PCSrcE
+add wave -hex /testbench/dut/core/ieu/dp/SrcAE
+add wave -hex /testbench/dut/core/ieu/dp/SrcBE
+add wave -hex /testbench/dut/core/ieu/dp/ALUResultE
+#add wave /testbench/dut/core/ieu/dp/PCSrcE
 add wave -divider
 
-add wave -hex /testbench/dut/hart/ifu/PCM
-add wave -hex /testbench/dut/hart/ifu/InstrM
+add wave -hex /testbench/dut/core/ifu/PCM
+add wave -hex /testbench/dut/core/ifu/InstrM
 add wave /testbench/InstrMName
 add wave /testbench/dut/uncore/ram/memwrite
 add wave -hex /testbench/dut/uncore/HADDR
 add wave -hex /testbench/dut/uncore/HWDATA
 add wave -divider
 
-add wave -hex /testbench/dut/hart/ebu/MemReadM
-add wave -hex /testbench/dut/hart/ebu/InstrReadF
-add wave -hex /testbench/dut/hart/ebu/BusState
-add wave -hex /testbench/dut/hart/ebu/NextBusState
-add wave -hex /testbench/dut/hart/ebu/HADDR
-add wave -hex /testbench/dut/hart/ebu/HREADY
-add wave -hex /testbench/dut/hart/ebu/HTRANS
-add wave -hex /testbench/dut/hart/ebu/HRDATA
-add wave -hex /testbench/dut/hart/ebu/HWRITE
-add wave -hex /testbench/dut/hart/ebu/HWDATA
-add wave -hex /testbench/dut/hart/ebu/ReadDataM
+add wave -hex /testbench/dut/core/ebu/MemReadM
+add wave -hex /testbench/dut/core/ebu/InstrReadF
+add wave -hex /testbench/dut/core/ebu/BusState
+add wave -hex /testbench/dut/core/ebu/NextBusState
+add wave -hex /testbench/dut/core/ebu/HADDR
+add wave -hex /testbench/dut/core/ebu/HREADY
+add wave -hex /testbench/dut/core/ebu/HTRANS
+add wave -hex /testbench/dut/core/ebu/HRDATA
+add wave -hex /testbench/dut/core/ebu/HWRITE
+add wave -hex /testbench/dut/core/ebu/HWDATA
+add wave -hex /testbench/dut/core/ebu/ReadDataM
 add wave -divider
 
-add wave /testbench/dut/hart/ebu/CaptureDataM
-add wave /testbench/dut/hart/ebu/CapturedDataAvailable
-add wave /testbench/dut/hart/StallW
-add wave -hex /testbench/dut/hart/ebu/CapturedData
-add wave -hex /testbench/dut/hart/ebu/ReadDataWnext
-add wave -hex /testbench/dut/hart/ebu/ReadDataW
-add wave -hex /testbench/dut/hart/ifu/PCW
-add wave -hex /testbench/dut/hart/ifu/InstrW
+add wave /testbench/dut/core/ebu/CaptureDataM
+add wave /testbench/dut/core/ebu/CapturedDataAvailable
+add wave /testbench/dut/core/StallW
+add wave -hex /testbench/dut/core/ebu/CapturedData
+add wave -hex /testbench/dut/core/ebu/ReadDataWnext
+add wave -hex /testbench/dut/core/ebu/ReadDataW
+add wave -hex /testbench/dut/core/ifu/PCW
+add wave -hex /testbench/dut/core/ifu/InstrW
 add wave /testbench/InstrWName
-add wave /testbench/dut/hart/ieu/dp/RegWriteW
-add wave -hex /testbench/dut/hart/ebu/ReadDataW
-add wave -hex /testbench/dut/hart/ieu/dp/ResultW
-add wave -hex /testbench/dut/hart/ieu/dp/RdW
+add wave /testbench/dut/core/ieu/dp/RegWriteW
+add wave -hex /testbench/dut/core/ebu/ReadDataW
+add wave -hex /testbench/dut/core/ieu/dp/ResultW
+add wave -hex /testbench/dut/core/ieu/dp/RdW
 add wave -divider
 
-add wave -hex /testbench/dut/hart/dmem/*
-add wave -hex /testbench/dut/hart/dmem/genblk1/*
+add wave -hex /testbench/dut/core/dmem/*
+add wave -hex /testbench/dut/core/dmem/genblk1/*
 add wave -divider
 
 add wave -hex -r /testbench/*

pipelined/regression/wave-dos/default-waves.do

@@ -7,35 +7,35 @@ view wave
 add wave /testbench/clk
 add wave /testbench/reset
 add wave -divider
-#add wave /testbench/dut/hart/ebu/IReadF
-#add wave /testbench/dut/hart/DataStall
-add wave /testbench/dut/hart/ICacheStallF
-add wave /testbench/dut/hart/StallF
-add wave /testbench/dut/hart/StallD
-add wave /testbench/dut/hart/StallE
-add wave /testbench/dut/hart/StallM
-add wave /testbench/dut/hart/StallW
-add wave /testbench/dut/hart/FlushD
-add wave /testbench/dut/hart/FlushE
-add wave /testbench/dut/hart/FlushM
-add wave /testbench/dut/hart/FlushW
+#add wave /testbench/dut/core/ebu/IReadF
+#add wave /testbench/dut/core/DataStall
+add wave /testbench/dut/core/ICacheStallF
+add wave /testbench/dut/core/StallF
+add wave /testbench/dut/core/StallD
+add wave /testbench/dut/core/StallE
+add wave /testbench/dut/core/StallM
+add wave /testbench/dut/core/StallW
+add wave /testbench/dut/core/FlushD
+add wave /testbench/dut/core/FlushE
+add wave /testbench/dut/core/FlushM
+add wave /testbench/dut/core/FlushW
 
 add wave -divider
-add wave -hex /testbench/dut/hart/ifu/PCF
-add wave -hex /testbench/dut/hart/ifu/PCD
-add wave -hex /testbench/dut/hart/ifu/InstrD
+add wave -hex /testbench/dut/core/ifu/PCF
+add wave -hex /testbench/dut/core/ifu/PCD
+add wave -hex /testbench/dut/core/ifu/InstrD
 add wave /testbench/InstrDName
 add wave -divider
-add wave -hex /testbench/dut/hart/ifu/PCE
-add wave -hex /testbench/dut/hart/ifu/InstrE
+add wave -hex /testbench/dut/core/ifu/PCE
+add wave -hex /testbench/dut/core/ifu/InstrE
 add wave /testbench/InstrEName
-add wave -hex /testbench/dut/hart/ieu/dp/SrcAE
-add wave -hex /testbench/dut/hart/ieu/dp/SrcBE
-add wave -hex /testbench/dut/hart/ieu/dp/ALUResultE
-#add wave /testbench/dut/hart/ieu/dp/PCSrcE
+add wave -hex /testbench/dut/core/ieu/dp/SrcAE
+add wave -hex /testbench/dut/core/ieu/dp/SrcBE
+add wave -hex /testbench/dut/core/ieu/dp/ALUResultE
+#add wave /testbench/dut/core/ieu/dp/PCSrcE
 add wave -divider
-add wave -hex /testbench/dut/hart/ifu/PCM
-add wave -hex /testbench/dut/hart/ifu/InstrM
+add wave -hex /testbench/dut/core/ifu/PCM
+add wave -hex /testbench/dut/core/ifu/InstrM
 add wave /testbench/InstrMName
 add wave /testbench/dut/uncore/ram/memwrite
 add wave -hex /testbench/dut/uncore/HADDR
@@ -44,9 +44,9 @@ add wave -divider
 add wave -hex /testbench/PCW
 add wave -hex /testbench/InstrW
 add wave /testbench/InstrWName
-add wave /testbench/dut/hart/ieu/dp/RegWriteW
-add wave -hex /testbench/dut/hart/ieu/dp/ResultW
-add wave -hex /testbench/dut/hart/ieu/dp/RdW
+add wave /testbench/dut/core/ieu/dp/RegWriteW
+add wave -hex /testbench/dut/core/ieu/dp/ResultW
+add wave -hex /testbench/dut/core/ieu/dp/RdW
 add wave -divider
 
 add wave -hex -r /testbench/*

pipelined/regression/wave-dos/linux-waves.do

@@ -6,185 +6,185 @@ add wave -noupdate /testbench/reset
 add wave -noupdate -radix decimal /testbench/errorCount
 add wave -noupdate -radix decimal /testbench/InstrCountW
 add wave -noupdate -divider Stalls_and_Flushes
-add wave -noupdate /testbench/dut/hart/StallF
-add wave -noupdate /testbench/dut/hart/StallD
-add wave -noupdate /testbench/dut/hart/StallE
-add wave -noupdate /testbench/dut/hart/StallM
-add wave -noupdate /testbench/dut/hart/StallW
-add wave -noupdate /testbench/dut/hart/FlushD
-add wave -noupdate /testbench/dut/hart/FlushE
-add wave -noupdate /testbench/dut/hart/FlushM
-add wave -noupdate /testbench/dut/hart/FlushW
+add wave -noupdate /testbench/dut/core/StallF
+add wave -noupdate /testbench/dut/core/StallD
+add wave -noupdate /testbench/dut/core/StallE
+add wave -noupdate /testbench/dut/core/StallM
+add wave -noupdate /testbench/dut/core/StallW
+add wave -noupdate /testbench/dut/core/FlushD
+add wave -noupdate /testbench/dut/core/FlushE
+add wave -noupdate /testbench/dut/core/FlushM
+add wave -noupdate /testbench/dut/core/FlushW
 add wave -noupdate -divider F
-add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCF
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCF
 add wave -noupdate -divider D
-add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCD
 add wave -noupdate /testbench/InstrDName
-add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/InstrD
-add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/InstrValidD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/InstrValidD
 add wave -noupdate -divider E
-add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCE
 add wave -noupdate /testbench/InstrEName
-add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/InstrE
-add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/InstrValidE
-add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/SrcAE
-add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/SrcBE
-add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ALUResultE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/InstrValidE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/SrcAE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/SrcBE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ALUResultE
 add wave -noupdate -divider M
-add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCM
 add wave -noupdate /testbench/InstrMName
 add wave -noupdate /testbench/textM
-add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/InstrM
-add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/InstrValidM
-add wave -noupdate -radix hexadecimal /testbench/dut/hart/lsu.bus.dcache/MemPAdrM
-add wave -noupdate -radix hexadecimal /testbench/dut/hart/lsu.bus.dcache/MemRWM
-add wave -noupdate /testbench/dut/hart/lsu.bus.dcache/WriteDataM
-add wave -noupdate -radix hexadecimal /testbench/dut/hart/lsu.bus.dcache/ReadDataM
-add wave -noupdate -group Walker /testbench/dut/hart/lsu/hptw/genblk1/DTLBWalk
-add wave -noupdate -group Walker /testbench/dut/hart/lsu/hptw/genblk1/BasePageTablePPN
-add wave -noupdate -group Walker /testbench/dut/hart/lsu/hptw/genblk1/CurrentPPN
-add wave -noupdate -group Walker /testbench/dut/hart/lsu/hptw/genblk1/MemWrite
-add wave -noupdate -group Walker /testbench/dut/hart/lsu/hptw/genblk1/Executable
-add wave -noupdate -group Walker /testbench/dut/hart/lsu/hptw/genblk1/Writable
-add wave -noupdate -group Walker /testbench/dut/hart/lsu/hptw/genblk1/Readable
-add wave -noupdate -group Walker /testbench/dut/hart/lsu/hptw/genblk1/Valid
-add wave -noupdate -group Walker /testbench/dut/hart/lsu/hptw/genblk1/Misaligned
-add wave -noupdate -group Walker /testbench/dut/hart/lsu/hptw/genblk1/MegapageMisaligned
-add wave -noupdate -group Walker /testbench/dut/hart/lsu/hptw/genblk1/ValidPTE
-add wave -noupdate -group Walker /testbench/dut/hart/lsu/hptw/genblk1/LeafPTE
-add wave -noupdate -group Walker /testbench/dut/hart/lsu/hptw/genblk1/ValidLeafPTE
-add wave -noupdate -group Walker /testbench/dut/hart/lsu/hptw/genblk1/ValidNonLeafPTE
-add wave -noupdate -group Walker /testbench/dut/hart/lsu/hptw/genblk1/StartWalk
-add wave -noupdate -group Walker /testbench/dut/hart/lsu/hptw/genblk1/TLBMiss
-add wave -noupdate -group Walker /testbench/dut/hart/lsu/hptw/genblk1/PRegEn
-add wave -noupdate -group Walker /testbench/dut/hart/lsu/hptw/genblk1/NextPageType
-add wave -noupdate -group Walker /testbench/dut/hart/lsu/hptw/genblk1/SvMode
-add wave -noupdate -group Walker /testbench/dut/hart/lsu/hptw/genblk1/TranslationVAdr
-add wave -noupdate -group Walker /testbench/dut/hart/lsu/hptw/genblk1/WalkerState
-add wave -noupdate -group Walker /testbench/dut/hart/lsu/hptw/genblk1/NextWalkerState
-add wave -noupdate -group Walker /testbench/dut/hart/lsu/hptw/genblk1/InitialWalkerState
-add wave -noupdate -group LSU -r /testbench/dut/hart/lsu/*
-add wave -noupdate -group DCache -r /testbench/dut/hart/lsu.bus.dcache/*
-add wave -noupdate -group EBU /testbench/dut/hart/ebu/clk
-add wave -noupdate -group EBU /testbench/dut/hart/ebu/reset
-add wave -noupdate -group EBU /testbench/dut/hart/ebu/StallW
-add wave -noupdate -group EBU /testbench/dut/hart/ebu/UnsignedLoadM
-add wave -noupdate -group EBU /testbench/dut/hart/ebu/AtomicMaskedM
-add wave -noupdate -group EBU /testbench/dut/hart/ebu/Funct7M
-add wave -noupdate -group EBU /testbench/dut/hart/ebu/InstrPAdrF
-add wave -noupdate -group EBU /testbench/dut/hart/ebu/InstrReadF
-add wave -noupdate -group EBU /testbench/dut/hart/ebu/InstrRData
-add wave -noupdate -group EBU /testbench/dut/hart/ebu/InstrAckF
-add wave -noupdate -group EBU /testbench/dut/hart/ebu/DCtoAHBPAdrM
-add wave -noupdate -group EBU /testbench/dut/hart/ebu/DCtoAHBReadM
-add wave -noupdate -group EBU /testbench/dut/hart/ebu/DCtoAHBWriteM
-add wave -noupdate -group EBU /testbench/dut/hart/ebu/DCtoAHBWriteData
-add wave -noupdate -group EBU /testbench/dut/hart/ebu/DCfromAHBReadData
-add wave -noupdate -group EBU /testbench/dut/hart/ebu/MemSizeM
-add wave -noupdate -group EBU /testbench/dut/hart/ebu/DCfromAHBAck
-add wave -noupdate -group EBU /testbench/dut/hart/ebu/HRDATA
-add wave -noupdate -group EBU /testbench/dut/hart/ebu/HREADY
-add wave -noupdate -group EBU /testbench/dut/hart/ebu/HRESP
-add wave -noupdate -group EBU /testbench/dut/hart/ebu/HCLK
-add wave -noupdate -group EBU /testbench/dut/hart/ebu/HRESETn
-add wave -noupdate -group EBU /testbench/dut/hart/ebu/HADDR
-add wave -noupdate -group EBU /testbench/dut/hart/ebu/HWDATA
-add wave -noupdate -group EBU /testbench/dut/hart/ebu/HWRITE
-add wave -noupdate -group EBU /testbench/dut/hart/ebu/HSIZE
-add wave -noupdate -group EBU /testbench/dut/hart/ebu/HBURST
-add wave -noupdate -group EBU /testbench/dut/hart/ebu/HPROT
-add wave -noupdate -group EBU /testbench/dut/hart/ebu/HTRANS
-add wave -noupdate -group EBU /testbench/dut/hart/ebu/HMASTLOCK
-add wave -noupdate -group EBU /testbench/dut/hart/ebu/HADDRD
-add wave -noupdate -group EBU /testbench/dut/hart/ebu/HSIZED
-add wave -noupdate -group EBU /testbench/dut/hart/ebu/HWRITED
-add wave -noupdate -group EBU /testbench/dut/hart/ebu/GrantData
-add wave -noupdate -group EBU /testbench/dut/hart/ebu/AccessAddress
-add wave -noupdate -group EBU /testbench/dut/hart/ebu/ISize
-add wave -noupdate -group EBU /testbench/dut/hart/ebu/HRDATAMasked
-add wave -noupdate -group EBU /testbench/dut/hart/ebu/ReadDataM
-add wave -noupdate -group EBU /testbench/dut/hart/ebu/HRDATANext
-add wave -noupdate -group EBU /testbench/dut/hart/ebu/CapturedHRDATAMasked
-add wave -noupdate -group EBU /testbench/dut/hart/ebu/WriteData
-add wave -noupdate -group EBU /testbench/dut/hart/ebu/IReady
-add wave -noupdate -group EBU /testbench/dut/hart/ebu/DReady
-add wave -noupdate -group EBU /testbench/dut/hart/ebu/CaptureDataM
-add wave -noupdate -group EBU /testbench/dut/hart/ebu/CapturedDataAvailable
-add wave -noupdate -group EBU /testbench/dut/hart/ebu/BusState
-add wave -noupdate -group EBU /testbench/dut/hart/ebu/NextBusState
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/InstrValidM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/lsu.bus.dcache/MemPAdrM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/lsu.bus.dcache/MemRWM
+add wave -noupdate /testbench/dut/core/lsu.bus.dcache/WriteDataM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/lsu.bus.dcache/ReadDataM
+add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/DTLBWalk
+add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/BasePageTablePPN
+add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/CurrentPPN
+add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/MemWrite
+add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/Executable
+add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/Writable
+add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/Readable
+add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/Valid
+add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/Misaligned
+add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/MegapageMisaligned
+add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/ValidPTE
+add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/LeafPTE
+add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/ValidLeafPTE
+add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/ValidNonLeafPTE
+add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/StartWalk
+add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/TLBMiss
+add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/PRegEn
+add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/NextPageType
+add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/SvMode
+add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/TranslationVAdr
+add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/WalkerState
+add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/NextWalkerState
+add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/InitialWalkerState
+add wave -noupdate -group LSU -r /testbench/dut/core/lsu/*
+add wave -noupdate -group DCache -r /testbench/dut/core/lsu.bus.dcache/*
+add wave -noupdate -group EBU /testbench/dut/core/ebu/clk
+add wave -noupdate -group EBU /testbench/dut/core/ebu/reset
+add wave -noupdate -group EBU /testbench/dut/core/ebu/StallW
+add wave -noupdate -group EBU /testbench/dut/core/ebu/UnsignedLoadM
+add wave -noupdate -group EBU /testbench/dut/core/ebu/AtomicMaskedM
+add wave -noupdate -group EBU /testbench/dut/core/ebu/Funct7M
+add wave -noupdate -group EBU /testbench/dut/core/ebu/InstrPAdrF
+add wave -noupdate -group EBU /testbench/dut/core/ebu/InstrReadF
+add wave -noupdate -group EBU /testbench/dut/core/ebu/InstrRData
+add wave -noupdate -group EBU /testbench/dut/core/ebu/InstrAckF
+add wave -noupdate -group EBU /testbench/dut/core/ebu/DCtoAHBPAdrM
+add wave -noupdate -group EBU /testbench/dut/core/ebu/DCtoAHBReadM
+add wave -noupdate -group EBU /testbench/dut/core/ebu/DCtoAHBWriteM
+add wave -noupdate -group EBU /testbench/dut/core/ebu/DCtoAHBWriteData
+add wave -noupdate -group EBU /testbench/dut/core/ebu/DCfromAHBReadData
+add wave -noupdate -group EBU /testbench/dut/core/ebu/MemSizeM
+add wave -noupdate -group EBU /testbench/dut/core/ebu/DCfromAHBAck
+add wave -noupdate -group EBU /testbench/dut/core/ebu/HRDATA
+add wave -noupdate -group EBU /testbench/dut/core/ebu/HREADY
+add wave -noupdate -group EBU /testbench/dut/core/ebu/HRESP
+add wave -noupdate -group EBU /testbench/dut/core/ebu/HCLK
+add wave -noupdate -group EBU /testbench/dut/core/ebu/HRESETn
+add wave -noupdate -group EBU /testbench/dut/core/ebu/HADDR
+add wave -noupdate -group EBU /testbench/dut/core/ebu/HWDATA
+add wave -noupdate -group EBU /testbench/dut/core/ebu/HWRITE
+add wave -noupdate -group EBU /testbench/dut/core/ebu/HSIZE
+add wave -noupdate -group EBU /testbench/dut/core/ebu/HBURST
+add wave -noupdate -group EBU /testbench/dut/core/ebu/HPROT
+add wave -noupdate -group EBU /testbench/dut/core/ebu/HTRANS
+add wave -noupdate -group EBU /testbench/dut/core/ebu/HMASTLOCK
+add wave -noupdate -group EBU /testbench/dut/core/ebu/HADDRD
+add wave -noupdate -group EBU /testbench/dut/core/ebu/HSIZED
+add wave -noupdate -group EBU /testbench/dut/core/ebu/HWRITED
+add wave -noupdate -group EBU /testbench/dut/core/ebu/GrantData
+add wave -noupdate -group EBU /testbench/dut/core/ebu/AccessAddress
+add wave -noupdate -group EBU /testbench/dut/core/ebu/ISize
+add wave -noupdate -group EBU /testbench/dut/core/ebu/HRDATAMasked
+add wave -noupdate -group EBU /testbench/dut/core/ebu/ReadDataM
+add wave -noupdate -group EBU /testbench/dut/core/ebu/HRDATANext
+add wave -noupdate -group EBU /testbench/dut/core/ebu/CapturedHRDATAMasked
+add wave -noupdate -group EBU /testbench/dut/core/ebu/WriteData
+add wave -noupdate -group EBU /testbench/dut/core/ebu/IReady
+add wave -noupdate -group EBU /testbench/dut/core/ebu/DReady
+add wave -noupdate -group EBU /testbench/dut/core/ebu/CaptureDataM
+add wave -noupdate -group EBU /testbench/dut/core/ebu/CapturedDataAvailable
+add wave -noupdate -group EBU /testbench/dut/core/ebu/BusState
+add wave -noupdate -group EBU /testbench/dut/core/ebu/NextBusState
 add wave -noupdate -divider W
 add wave -noupdate -radix hexadecimal /testbench/PCW
-add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/InstrValidW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/InstrValidW
 add wave -noupdate /testbench/textM
-add wave -noupdate /testbench/dut/hart/ieu/dp/ReadDataW
-add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ResultW
-add wave -noupdate -group RF /testbench/dut/hart/ieu/dp/RegWriteW
-add wave -noupdate -group RF -radix unsigned /testbench/dut/hart/ieu/dp/RdW
-add wave -noupdate -group RF /testbench/dut/hart/ieu/dp/regf/wd3
-add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[2]}
-add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[3]}
-add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[4]}
-add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[5]}
-add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[6]}
-add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[7]}
-add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[8]}
-add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[9]}
-add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[10]}
-add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[11]}
-add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[12]}
-add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[13]}
-add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[14]}
-add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[15]}
-add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[16]}
-add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[17]}
-add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[18]}
-add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[19]}
-add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[20]}
-add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[21]}
-add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[22]}
-add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[23]}
-add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[24]}
-add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[25]}
-add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[26]}
-add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[27]}
-add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[28]}
-add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[29]}
-add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[30]}
-add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[31]}
-add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/MSTATUS_REGW
-add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/MCOUNTINHIBIT_REGW
-add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/MCOUNTEREN_REGW
-add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csri/MIDELEG_REGW
-add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csri/MIP_REGW
-add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csri/MIE_REGW
-add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MEPC_REGW
-add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MTVEC_REGW
-add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MCOUNTEREN_REGW
-add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MCOUNTINHIBIT_REGW
-add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MEDELEG_REGW
-add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MIDELEG_REGW
-add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MSCRATCH_REGW
-add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MCAUSE_REGW
-add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MTVAL_REGW
-add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/SSTATUS_REGW
-add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/SCOUNTEREN_REGW
-add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csri/SIP_REGW
-add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csri/SIE_REGW
-add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/SEPC_REGW
-add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/STVEC_REGW
-add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/SCOUNTEREN_REGW
-add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/SEDELEG_REGW
-add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/SIDELEG_REGW
-add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/SATP_REGW
-add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/USTATUS_REGW
-add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrn/UEPC_REGW
-add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrn/UTVEC_REGW
-add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrn/UIP_REGW
-add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrn/UIE_REGW
-add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/PMPCFG_ARRAY_REGW
-add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/PMPADDR_ARRAY_REGW
-add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MISA_REGW
-add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csru/FRM_REGW
+add wave -noupdate /testbench/dut/core/ieu/dp/ReadDataW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ResultW
+add wave -noupdate -group RF /testbench/dut/core/ieu/dp/RegWriteW
+add wave -noupdate -group RF -radix unsigned /testbench/dut/core/ieu/dp/RdW
+add wave -noupdate -group RF /testbench/dut/core/ieu/dp/regf/wd3
+add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[2]}
+add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[3]}
+add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[4]}
+add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[5]}
+add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[6]}
+add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[7]}
+add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[8]}
+add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[9]}
+add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[10]}
+add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[11]}
+add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[12]}
+add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[13]}
+add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[14]}
+add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[15]}
+add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[16]}
+add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[17]}
+add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[18]}
+add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[19]}
+add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[20]}
+add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[21]}
+add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[22]}
+add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[23]}
+add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[24]}
+add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[25]}
+add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[26]}
+add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[27]}
+add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[28]}
+add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[29]}
+add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[30]}
+add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[31]}
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/MSTATUS_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/MCOUNTINHIBIT_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/MCOUNTEREN_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/MIDELEG_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/MIP_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/MIE_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MEPC_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MTVEC_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCOUNTEREN_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCOUNTINHIBIT_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MEDELEG_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MIDELEG_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MSCRATCH_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCAUSE_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MTVAL_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/SSTATUS_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/SCOUNTEREN_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/SIP_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/SIE_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/SEPC_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/STVEC_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/SCOUNTEREN_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/SEDELEG_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/SIDELEG_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/SATP_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/USTATUS_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/UEPC_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/UTVEC_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/UIP_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/UIE_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/PMPCFG_ARRAY_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/PMPADDR_ARRAY_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MISA_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/FRM_REGW
 add wave -noupdate -divider <NULL>
 add wave -hex -r /testbench/*
 TreeUpdate [SetDefaultTree]

pipelined/regression/wave-dos/peripheral-waves.do

@@ -9,99 +9,99 @@ add wave /testbench/clk
 add wave /testbench/reset
 add wave -divider
 
-#add wave /testbench/dut/hart/DataStall
-add wave /testbench/dut/hart/StallF
-add wave /testbench/dut/hart/StallD
-add wave /testbench/dut/hart/StallE
-add wave /testbench/dut/hart/StallM
-add wave /testbench/dut/hart/StallW
-add wave /testbench/dut/hart/FlushD
-add wave /testbench/dut/hart/FlushE
-add wave /testbench/dut/hart/FlushM
-add wave /testbench/dut/hart/FlushW
+#add wave /testbench/dut/core/DataStall
+add wave /testbench/dut/core/StallF
+add wave /testbench/dut/core/StallD
+add wave /testbench/dut/core/StallE
+add wave /testbench/dut/core/StallM
+add wave /testbench/dut/core/StallW
+add wave /testbench/dut/core/FlushD
+add wave /testbench/dut/core/FlushE
+add wave /testbench/dut/core/FlushM
+add wave /testbench/dut/core/FlushW
 add wave -divider
 
-add wave -hex /testbench/dut/hart/ifu/PCF
-add wave -hex /testbench/dut/hart/ifu/PCD
-add wave -hex /testbench/dut/hart/ifu/InstrD
-add wave -hex /testbench/dut/hart/ieu/c/InstrValidD
+add wave -hex /testbench/dut/core/ifu/PCF
+add wave -hex /testbench/dut/core/ifu/PCD
+add wave -hex /testbench/dut/core/ifu/InstrD
+add wave -hex /testbench/dut/core/ieu/c/InstrValidD
 add wave /testbench/InstrDName
 add wave -divider
-add wave -hex /testbench/dut/hart/ifu/PCE
-add wave -hex /testbench/dut/hart/ifu/InstrE
-add wave -hex /testbench/dut/hart/ieu/c/InstrValidE
+add wave -hex /testbench/dut/core/ifu/PCE
+add wave -hex /testbench/dut/core/ifu/InstrE
+add wave -hex /testbench/dut/core/ieu/c/InstrValidE
 add wave /testbench/InstrEName
-add wave -hex /testbench/dut/hart/ieu/dp/SrcAE
-add wave -hex /testbench/dut/hart/ieu/dp/SrcBE
-add wave -hex /testbench/dut/hart/ieu/dp/ALUResultE
-#add wave /testbench/dut/hart/ieu/dp/PCSrcE
-add wave /testbench/dut/hart/mdu/genblk1/div/DivStartE
-add wave /testbench/dut/hart/mdu/DivBusyE
-add wave -hex /testbench/dut/hart/mdu/genblk1/div/RemM
-add wave -hex /testbench/dut/hart/mdu/genblk1/div/QuotM
+add wave -hex /testbench/dut/core/ieu/dp/SrcAE
+add wave -hex /testbench/dut/core/ieu/dp/SrcBE
+add wave -hex /testbench/dut/core/ieu/dp/ALUResultE
+#add wave /testbench/dut/core/ieu/dp/PCSrcE
+add wave /testbench/dut/core/mdu/genblk1/div/DivStartE
+add wave /testbench/dut/core/mdu/DivBusyE
+add wave -hex /testbench/dut/core/mdu/genblk1/div/RemM
+add wave -hex /testbench/dut/core/mdu/genblk1/div/QuotM
 
 add wave -divider
-add wave -hex /testbench/dut/hart/ifu/PCM
-add wave -hex /testbench/dut/hart/ifu/InstrM
-add wave -hex /testbench/dut/hart/ieu/c/InstrValidM
+add wave -hex /testbench/dut/core/ifu/PCM
+add wave -hex /testbench/dut/core/ifu/InstrM
+add wave -hex /testbench/dut/core/ieu/c/InstrValidM
 add wave /testbench/InstrMName
 add wave /testbench/dut/uncore/ram/memwrite
-add wave -hex /testbench/dut/hart/WriteDataM
-add wave -hex /testbench/dut/hart/lsu.bus.dcache/MemPAdrM
-add wave -hex /testbench/dut/hart/lsu.bus.dcache/WriteDataM
-add wave -hex /testbench/dut/hart/lsu.bus.dcache/ReadDataM
+add wave -hex /testbench/dut/core/WriteDataM
+add wave -hex /testbench/dut/core/lsu.bus.dcache/MemPAdrM
+add wave -hex /testbench/dut/core/lsu.bus.dcache/WriteDataM
+add wave -hex /testbench/dut/core/lsu.bus.dcache/ReadDataM
 add wave -divider
 add wave -hex /testbench/PCW
 #add wave -hex /testbench/InstrW
-#add wave -hex /testbench/dut/hart/ieu/c/InstrValidW
+#add wave -hex /testbench/dut/core/ieu/c/InstrValidW
 #add wave /testbench/InstrWName
-add wave -hex /testbench/dut/hart/ReadDataW
-add wave -hex /testbench/dut/hart/ieu/dp/ResultW
-add wave -hex /testbench/dut/hart/ieu/dp/RegWriteW
-add wave -hex /testbench/dut/hart/ieu/dp/WriteDataW
-add wave -hex /testbench/dut/hart/ieu/dp/RdW
+add wave -hex /testbench/dut/core/ReadDataW
+add wave -hex /testbench/dut/core/ieu/dp/ResultW
+add wave -hex /testbench/dut/core/ieu/dp/RegWriteW
+add wave -hex /testbench/dut/core/ieu/dp/WriteDataW
+add wave -hex /testbench/dut/core/ieu/dp/RdW
 add wave -divider
-add wave -hex /testbench/dut/hart/priv/csr/TrapM
-add wave -hex /testbench/dut/hart/priv/csr/UnalignedNextEPCM
-add wave -hex /testbench/dut/hart/priv/csr/genblk1/csrm/WriteMEPCM
-add wave -hex /testbench/dut/hart/priv/csr/genblk1/csrm/MEPC_REGW
+add wave -hex /testbench/dut/core/priv/csr/TrapM
+add wave -hex /testbench/dut/core/priv/csr/UnalignedNextEPCM
+add wave -hex /testbench/dut/core/priv/csr/genblk1/csrm/WriteMEPCM
+add wave -hex /testbench/dut/core/priv/csr/genblk1/csrm/MEPC_REGW
 
 add wave -divider RegFile
-add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[1]
-add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[2]
-add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[3]
-add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[4]
-add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[5]
-add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[6]
-add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[7]
-add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[8]
-add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[9]
-add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[10]
-add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[11]
-add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[12]
-add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[13]
-add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[14]
-add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[15]
-add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[16]
-add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[17]
-add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[18]
-add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[19]
-add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[20]
-add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[21]
-add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[22]
-add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[23]
-add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[24]
-add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[25]
-add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[26]
-add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[27]
-add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[28]
-add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[29]
-add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[30]
-add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[31]
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[1]
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[2]
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[3]
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[4]
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[5]
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[6]
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[7]
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[8]
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[9]
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[10]
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[11]
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[12]
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[13]
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[14]
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[15]
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[16]
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[17]
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[18]
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[19]
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[20]
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[21]
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[22]
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[23]
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[24]
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[25]
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[26]
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[27]
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[28]
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[29]
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[30]
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[31]
 
 # peripherals
 add wave -divider PLIC
-add wave -hex /testbench/dut/hart/priv/csr/TrapM
+add wave -hex /testbench/dut/core/priv/csr/TrapM
 add wave -hex /testbench/dut/uncore/plic/plic/*
 add wave -hex /testbench/dut/uncore/plic/plic/intPriority
 add wave -hex /testbench/dut/uncore/plic/plic/pendingArray
@@ -110,7 +110,7 @@ add wave -hex /testbench/dut/uncore/uart/uart/u/*
 add wave -divider GPIO
 add wave -hex /testbench/dut/uncore/gpio/gpio/*
 #add wave -divider
-#add wave -hex /testbench/dut/hart/ebu/*
+#add wave -hex /testbench/dut/core/ebu/*
 #add wave -divider
 #add wave -divider
 

pipelined/src/ebu/ahblite.sv

@@ -7,7 +7,7 @@
 // Purpose: AHB Lite External Bus Unit
 //          See ARM_HIH0033A_AMBA_AHB-Lite_SPEC 1.0
 //          Arbitrates requests from instruction and data streams
-//          Connects hart to peripherals and I/O pins on SOC
+//          Connects core to peripherals and I/O pins on SOC
 //          Bus width presently matches XLEN
 //          Anticipate replacing this with an AXI bus interface to communicate with FPGA DRAM/Flash controllers
 // 

pipelined/src/generic/flop/simpleram.sv

@@ -4,7 +4,7 @@
 // Written: David_Harris@hmc.edu 9 January 2021
 // Modified: 
 //
-// Purpose: On-chip SIMPLERAM, external to hart
+// Purpose: On-chip SIMPLERAM, external to core
 // 
 // A component of the Wally configurable RISC-V project.
 // 
@@ -31,50 +31,30 @@
 `include "wally-config.vh"
 
 module simpleram #(parameter BASE=0, RANGE = 65535) (
-  input  logic             HCLK, HRESETn, 
-  input  logic             HSELRam,
-  input  logic [31:0]      HADDR,
-  input  logic             HWRITE,
-  input  logic             HREADY,
-  input  logic [1:0]       HTRANS,
-  input  logic [`XLEN-1:0] HWDATA,
-  output logic [`XLEN-1:0] HREADRam,
-  output logic             HRESPRam, HREADYRam
+  input  logic             clk, 
+  input  logic [31:0]      a,
+  input  logic             we,
+  input  logic [`XLEN-1:0] wd,
+  output logic [`XLEN-1:0] rd
 );
 
-  localparam MemStartAddr = BASE>>(1+`XLEN/32);
-  localparam MemEndAddr = (RANGE+BASE)>>1+(`XLEN/32);
-  
   logic [`XLEN-1:0] RAM[BASE>>(1+`XLEN/32):(RANGE+BASE)>>1+(`XLEN/32)];
-  logic [31:0] HWADDR, A;
-  logic [`XLEN-1:0] HREADRam0;
-
-  logic        prevHREADYRam, risingHREADYRam;
-  logic        initTrans;
-  logic        memwrite;
-  logic [3:0]  busycount;
+  logic [31:0] ad;
 
+  flop #(32)   areg(clk, a, ad); // *** redesign external interface so this delay isn't needed
   
   /* verilator lint_off WIDTH */
   if (`XLEN == 64)  begin:ramrw
-    always_ff @(posedge HCLK) begin
-      if (HWRITE & |HTRANS) RAM[HADDR[31:3]] <= #1 HWDATA;
+    always_ff @(posedge clk) begin
+      rd <= RAM[a[31:3]];
+      if (we) RAM[ad[31:3]] <= #1 wd;
     end
   end else begin 
-    always_ff @(posedge HCLK) begin:ramrw
-      if (HWRITE & |HTRANS) RAM[HADDR[31:2]] <= #1 HWDATA;
+    always_ff @(posedge clk) begin:ramrw
+      rd <= RAM[a[31:2]];
+      if (we) RAM[ad[31:2]] <= #1 wd;
     end
   end
-
-  // read
-  if(`XLEN == 64) begin: ramr
-    assign HREADRam0 = RAM[HADDR[31:3]];
-  end else begin
-    assign HREADRam0 = RAM[HADDR[31:2]];
-  end
-
   /* verilator lint_on WIDTH */
-
-  assign HREADRam = HREADRam0;
 endmodule
 

pipelined/src/ifu/SRAM2P1R1W.sv

@@ -14,7 +14,7 @@
 // in modelsim's do file.
 // mem load -infile <relative path to the text file > -format <bin|hex> <hierarchy to the memory.>
 // example
-// mem load -infile twoBitPredictor.txt -format bin testbench/dut/hart/ifu/bpred/DirPredictor/memory/memory
+// mem load -infile twoBitPredictor.txt -format bin testbench/dut/core/ifu/bpred/DirPredictor/memory/memory
 //
 // A component of the Wally configurable RISC-V project.
 // 

pipelined/src/ifu/ifu.sv

@@ -96,7 +96,7 @@ module ifu (
   logic [`XLEN-1:0]            PCD;
 
   localparam [31:0]            nop = 32'h00000013; // instruction for NOP
-  //logic                        reset_q; // see comment below about PCNextF and icache.
+  logic                        reset_q; // see comment below about PCNextF and icache.
 
   logic                        BPPredDirWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE;
   logic [`XLEN-1:0] 		   PCBPWrongInvalidate;
@@ -107,7 +107,7 @@ module ifu (
   logic [`XLEN+1:0]            PCFExt;
 
   logic 					   CacheableF;
-  logic [11:0] 				   PCNextFMux;
+  logic [`XLEN-1:0]			   PCNextFMux;
   logic [`XLEN-1:0] 		   PCFMux;
   logic 					   SelNextSpill;
   logic 					   ICacheFetchLine;
@@ -128,7 +128,7 @@ module ifu (
 	// this exists only if there are compressed instructions.
 	assign PCFp2 = PCF + `XLEN'b10;
     
-	assign PCNextFMux = SelNextSpill ? PCFp2[11:0] : PCNextF[11:0];
+	assign PCNextFMux = SelNextSpill ? PCFp2 : PCNextF;
 	assign PCFMux = SelSpill ? PCFp2 : PCF;
     
 	assign Spill = &PCF[$clog2(SPILLTHRESHOLD)+1:1];
@@ -168,7 +168,7 @@ module ifu (
 
 	// end of spill support
   end else begin : NoSpillSupport // line: SpillSupport
-	assign PCNextFMux = PCNextF[11:0];
+	assign PCNextFMux = PCNextF;
 	assign PCFMux = PCF;
 	assign SelNextSpill = 0;
 	assign PostSpillInstrRawF = InstrRawF;
@@ -233,22 +233,20 @@ module ifu (
   if (`MEM_IROM) begin : irom
 	logic [`XLEN-1:0] FinalInstrRawF_FIXME;
 
+    // *** adjust interface so write address doesn't need delaying
+    // *** modify to be a ROM rather than RAM
     simpleram #(
         .BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram (
-        .HCLK(clk), .HRESETn(~reset), 
-        .HSELRam(1'b1), .HADDR(PCPF[31:0]),
-        .HWRITE(1'b0), .HREADY(1'b1),
-        .HTRANS(2'b10), .HWDATA(0), .HREADRam(FinalInstrRawF_FIXME),
-        .HRESPRam(), .HREADYRam());
-
-	assign FinalInstrRawF = FinalInstrRawF_FIXME[31:0];
+        .clk, 
+        .a(CPUBusy ? PCPF[31:0] : PCNextFMux[31:0]), // mux is also inside $, have to replay address if CPU is stalled.
+        .we(1'b0),
+        .wd(0), .rd(FinalInstrRawF_FIXME));
+	  assign FinalInstrRawF = FinalInstrRawF_FIXME[31:0];
     assign BusStall = 0;
     assign IFUBusRead = 0;
     assign ICacheBusAck = 0;
     assign SelUncachedAdr = 0;
     assign IFUBusAdr = 0;
-    
-    
   end else begin : bus
       genvar 			   index;
       for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer
@@ -291,7 +289,7 @@ module ifu (
 		   .RW(IFURWF), 
 		   .Atomic(2'b00),
 		   .FlushCache(1'b0),
-		   .NextAdr(PCNextFMux),
+		   .NextAdr(PCNextFMux[11:0]),
 		   .PAdr(PCPF),
 		   .CacheCommitted(),
 		   .InvalidateCacheM(InvalidateICacheM));
@@ -354,9 +352,9 @@ module ifu (
   mux2 #(`XLEN) pcmux3(.d0(PCNext2F),
          .d1(PrivilegedNextPCM),
          .s(PrivilegedChangePCM),
-         .y(UnalignedPCNextF));
+         //.y(UnalignedPCNextF));
+         .y(PCNext3F));
 
-         //.y(PCNext3F));
   // This mux is not strictly speaking required.  Because the icache takes in
   // PCNextF rather than PCPF, PCNextF should stay in reset while the cache
   // looks up the addresses.  Without this mux PCNextF will increment + 2/4.
@@ -367,14 +365,12 @@ module ifu (
   // cache line so the mux is not required.  I am leaving this comment and mux
   // a a reminder as to what is happening in case keep PCNextF at RESET_VECTOR
   // during reset becomes a requirement.
-  //mux2 #(`XLEN) pcmux4(.d0(PCNext3F),
-  //       .d1(`RESET_VECTOR),
-  //       .s(reset_q),
-  //       .y(UnalignedPCNextF)); 
-  //flop #(1) resetReg (.clk(clk),
-  //      .d(reset),
-  //      .q(reset_q));
+  mux2 #(`XLEN) pcmux4(.d0(PCNext3F),
+                       .d1(`RESET_VECTOR),
+                       .s(`MEM_IROM ? reset : reset_q),
+                       .y(UnalignedPCNextF));
 
+  flop #(1) resetReg (.clk(clk), .d(reset),.q(reset_q)); // delay reset
 
   flopenrc #(1) BPPredWrongMReg(.clk, .reset, .en(~StallM), .clear(FlushM),
 								.d(BPPredWrongE), .q(BPPredWrongM));

pipelined/src/lsu/lsu.sv

@@ -5,7 +5,7 @@
 // Modified: 
 //
 // Purpose: Load/Store Unit 
-//          Top level of the memory-stage hart logic
+//          Top level of the memory-stage core logic
 //          Contains data cache, DTLB, subword read/write datapath, interface to external bus
 // 
 // A component of the Wally configurable RISC-V project.
@@ -245,12 +245,12 @@ module lsu (
   logic 			   SelUncachedAdr;
 
   if (`MEM_DTIM) begin : dtim
+    // *** adjust interface so write address doesn't need delaying; switch to standard RAM?
     simpleram #(.BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram (
-        .HCLK(clk), .HRESETn(~reset), 
-        .HSELRam(1'b1), .HADDR(LSUPAdrM[31:0]),
-        .HWRITE(LSURWM[0]), .HREADY(1'b1),
-        .HTRANS(|LSURWM ? 2'b10 : 2'b00), .HWDATA(FinalWriteDataM), .HREADRam(ReadDataWordM),
-        .HRESPRam(), .HREADYRam());
+        .clk, 
+        .a(CPUBusy ? IEUAdrM[31:0] : IEUAdrE[31:0]),
+        .we(LSURWM[0]), 
+        .wd(FinalWriteDataM), .rd(ReadDataWordM));
 
     // since we have a local memory the bus connections are all disabled.
     // There are no peripherals supported.
@@ -259,7 +259,7 @@ module lsu (
     assign {DCacheStallM, DCacheCommittedM, DCacheWriteLine, DCacheFetchLine, DCacheBusAdr} = '0;
     assign ReadDataLineSetsM[0] = 0;
     assign DCacheMiss = 1'b0; assign DCacheAccess = 1'b0;
-end else begin : bus  // *** lsubusdp
+  end else begin : bus  // *** lsubusdp
     // Bus Side logic
     // register the fetch data from the next level of memory.
     // This register should be necessary for timing.  There is no register in the uncore or

pipelined/src/privileged/csr.sv

@@ -93,6 +93,9 @@ module csr #(parameter
   logic        IllegalCSRCAccessM, IllegalCSRMAccessM, IllegalCSRSAccessM, IllegalCSRUAccessM, IllegalCSRNAccessM, InsufficientCSRPrivilegeM;
   logic IllegalCSRMWriteReadonlyM;
   
+  logic InstrValidNotFlushedM;
+  assign InstrValidNotFlushedM = ~StallW & ~FlushW;
+
   // modify CSRs
   always_comb begin
     // Choose either rs1 or uimm[4:0] as source
@@ -119,7 +122,7 @@ module csr #(parameter
   assign CSRSWriteM = CSRWriteM & (|PrivilegeModeW);
   assign CSRUWriteM = CSRWriteM;  
 
-  csri  csri(.clk, .reset, .FlushW, .StallW, .CSRMWriteM, .CSRSWriteM,
+  csri  csri(.clk, .reset, .InstrValidNotFlushedM, .StallW, .CSRMWriteM, .CSRSWriteM,
              .CSRAdrM, .ExtIntM, .TimerIntM, .SwIntM,
              .MIDELEG_REGW, .MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW, .CSRWriteValM);
   csrsr csrsr(.clk, .reset, .StallW,
@@ -137,7 +140,7 @@ module csr #(parameter
               .CSRAdrM, .PrivilegeModeW, .CSRWriteValM,
               .MCOUNTINHIBIT_REGW, .MCOUNTEREN_REGW, .SCOUNTEREN_REGW,
               .MTIME_CLINT,  .CSRCReadValM, .IllegalCSRCAccessM);
-  csrm  csrm(.clk, .reset, .FlushW, .StallW,
+  csrm  csrm(.clk, .reset, .InstrValidNotFlushedM, .StallW,
               .CSRMWriteM, .MTrapM, .CSRAdrM,
               .NextEPCM, .NextCauseM, .NextMtvalM, .MSTATUS_REGW, 
               .CSRWriteValM, .CSRMReadValM, .MTVEC_REGW,
@@ -145,7 +148,7 @@ module csr #(parameter
               .MEDELEG_REGW, .MIDELEG_REGW,.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
               .MIP_REGW, .MIE_REGW, .WriteMSTATUSM,
               .IllegalCSRMAccessM, .IllegalCSRMWriteReadonlyM);
-  csrs  csrs(.clk, .reset,  .FlushW, .StallW,
+  csrs  csrs(.clk, .reset,  .InstrValidNotFlushedM, .StallW,
               .CSRSWriteM, .STrapM, .CSRAdrM,
               .NextEPCM, .NextCauseM, .NextMtvalM, .SSTATUS_REGW, 
               .STATUS_TVM, .CSRWriteValM, .PrivilegeModeW,
@@ -153,12 +156,12 @@ module csr #(parameter
               .SCOUNTEREN_REGW, .SEDELEG_REGW, .SIDELEG_REGW, 
               .SATP_REGW, .SIP_REGW, .SIE_REGW,
               .WriteSSTATUSM, .IllegalCSRSAccessM);
-  csrn  csrn(.clk, .reset, .FlushW, .StallW,
+  csrn  csrn(.clk, .reset, .InstrValidNotFlushedM, .StallW,
               .CSRNWriteM(CSRUWriteM), .UTrapM, .CSRAdrM,
               .NextEPCM, .NextCauseM, .NextMtvalM, .USTATUS_REGW, 
               .CSRWriteValM, .CSRNReadValM, .UEPC_REGW, .UTVEC_REGW, 
               .UIP_REGW, .UIE_REGW, .WriteUSTATUSM, .IllegalCSRNAccessM);
-  csru  csru(.clk, .reset, .FlushW, .StallW,
+  csru  csru(.clk, .reset, .InstrValidNotFlushedM, .StallW,
               .CSRUWriteM, .CSRAdrM, .CSRWriteValM, .CSRUReadValM,  
               .SetFflagsM, .FRM_REGW, .WriteFRMM, .WriteFFLAGSM,
               .IllegalCSRUAccessM);

pipelined/src/privileged/csri.sv

@@ -38,7 +38,7 @@ module csri #(parameter
   SIE = 12'h104,
   SIP = 12'h144) (
     input  logic             clk, reset, 
-    input  logic             FlushW, StallW,
+    input  logic             InstrValidNotFlushedM, StallW,
     input  logic             CSRMWriteM, CSRSWriteM,
     input  logic [11:0]      CSRAdrM,
     input  logic             ExtIntM, TimerIntM, SwIntM,
@@ -52,9 +52,6 @@ module csri #(parameter
   logic [11:0]     MIP_WRITE_MASK, SIP_WRITE_MASK;
   logic            WriteMIPM, WriteMIEM, WriteSIPM, WriteSIEM;
 
-  logic            InstrValidNotFlushedM;
-  assign InstrValidNotFlushedM = ~StallW & ~FlushW;
-
   // Determine which interrupts need to be set
   // assumes no N-mode user interrupts
 

pipelined/src/privileged/csrm.sv

@@ -70,7 +70,7 @@ module csrm #(parameter
    MIDELEG_MASK = {{(`XLEN-12){1'b0}}, 12'h222}
 ) (
     input logic 	     clk, reset, 
-    input logic 	     FlushW, StallW,
+    input logic 	     InstrValidNotFlushedM, StallW,
     input logic 	     CSRMWriteM, MTrapM,
     input logic [11:0] 	     CSRAdrM,
     input logic [`XLEN-1:0]  NextEPCM, NextCauseM, NextMtvalM, MSTATUS_REGW, 
@@ -95,9 +95,6 @@ module csrm #(parameter
   logic            WriteMSCRATCHM, WriteMEPCM, WriteMCAUSEM, WriteMTVALM;
   logic            WriteMCOUNTERENM, WriteMCOUNTINHIBITM;
 
-  logic            InstrValidNotFlushedM;
-  assign InstrValidNotFlushedM = ~StallW & ~FlushW;
-  
  // There are PMP_ENTRIES = 0, 16, or 64 PMPADDR registers, each of which has its own flop
   genvar i;
   if (`PMP_ENTRIES > 0) begin:pmp

pipelined/src/privileged/csrn.sv

@@ -42,7 +42,7 @@ module csrn #(parameter
   UTVAL = 12'h043,
   UIP = 12'h044) (
     input  logic             clk, reset, 
-    input  logic             FlushW, StallW,
+    input  logic             InstrValidNotFlushedM, StallW,
     input  logic             CSRNWriteM, UTrapM,
     input  logic [11:0]      CSRAdrM,
     input  logic [`XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, USTATUS_REGW, 
@@ -60,9 +60,6 @@ module csrn #(parameter
     logic WriteUCAUSEM, WriteUTVALM;
     logic [`XLEN-1:0] UEDELEG_REGW, UIDELEG_REGW;
     logic [`XLEN-1:0] USCRATCH_REGW, UCAUSE_REGW, UTVAL_REGW;
-    
-    logic             InstrValidNotFlushedM;
-    assign InstrValidNotFlushedM = ~StallW & ~FlushW;
 
     // Write enables
     assign WriteUSTATUSM = CSRNWriteM & (CSRAdrM == USTATUS) & InstrValidNotFlushedM;

pipelined/src/privileged/csrs.sv

@@ -52,7 +52,7 @@ module csrs #(parameter
 
   ) (
     input logic 	     clk, reset, 
-    input logic 	     FlushW, StallW,
+    input logic 	     InstrValidNotFlushedM, StallW,
     input logic 	     CSRSWriteM, STrapM,
     input logic [11:0] 	     CSRAdrM,
     input logic [`XLEN-1:0]  NextEPCM, NextCauseM, NextMtvalM, SSTATUS_REGW, 
@@ -81,9 +81,6 @@ module csrs #(parameter
 (* mark_debug = "true" *)    logic [`XLEN-1:0] SSCRATCH_REGW, STVAL_REGW;
     (* mark_debug = "true" *) logic [`XLEN-1:0] SCAUSE_REGW;      
     
-    logic             InstrValidNotFlushedM;
-    assign InstrValidNotFlushedM = ~StallW & ~FlushW;
-
     assign WriteSSTATUSM = CSRSWriteM & (CSRAdrM == SSTATUS)  & InstrValidNotFlushedM;
     assign WriteSTVECM = CSRSWriteM & (CSRAdrM == STVEC) & InstrValidNotFlushedM;
     assign WriteSSCRATCHM = CSRSWriteM & (CSRAdrM == SSCRATCH) & InstrValidNotFlushedM;

pipelined/src/privileged/csru.sv

@@ -37,7 +37,7 @@ module csru #(parameter
   FRM = 12'h002,
   FCSR = 12'h003) (
     input  logic             clk, reset, 
-    input  logic             FlushW, StallW,
+    input  logic             InstrValidNotFlushedM, StallW,
     input  logic             CSRUWriteM,
     input  logic [11:0]      CSRAdrM,
     input  logic [`XLEN-1:0] CSRWriteValM,
@@ -54,9 +54,6 @@ module csru #(parameter
     logic [2:0] NextFRMM;
     logic [4:0] NextFFLAGSM;
       
-    logic       InstrValidNotFlushedM;
-    assign InstrValidNotFlushedM = ~StallW & ~FlushW;
-
     // Write enables
     //assign WriteFCSRM = CSRUWriteM & (CSRAdrM == FCSR)  & InstrValidNotFlushedM;
     assign WriteFRMM = (CSRUWriteM & (CSRAdrM == FRM | CSRAdrM == FCSR))  & InstrValidNotFlushedM;

pipelined/src/uncore/ram.sv

@@ -4,7 +4,7 @@
 // Written: David_Harris@hmc.edu 9 January 2021
 // Modified: 
 //
-// Purpose: On-chip RAM, external to hart
+// Purpose: On-chip RAM, external to core
 // 
 // A component of the Wally configurable RISC-V project.
 // 

pipelined/src/uncore/uncore.sv

@@ -4,7 +4,7 @@
 // Written: David_Harris@hmc.edu 9 January 2021
 // Modified: Ben Bracker 6 Mar 2021 to better fit AMBA 3 AHB-Lite spec
 //
-// Purpose: System-on-Chip components outside the core (hart)
+// Purpose: System-on-Chip components outside the core
 //          Memories, peripherals, external bus control
 // 
 // A component of the Wally configurable RISC-V project.
@@ -97,7 +97,7 @@ module uncore (
     .HWDATAIN, .HWDATA);
 
 //  generate
-    // on-chip RAM outside hart
+    // on-chip RAM
     if (`RAM_SUPPORTED) begin : ram
       ram #(
         .BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram (

pipelined/src/wally/wallypipelinedcore.sv

@@ -1,5 +1,5 @@
 ///////////////////////////////////////////
-// wallypipelinedhart.sv
+// wallypipelinedcore.sv
 //
 // Written: David_Harris@hmc.edu 9 January 2021
 // Modified: 
@@ -31,7 +31,7 @@
 `include "wally-config.vh"
 /* verilator lint_on UNUSED */
 
-module wallypipelinedhart (
+module wallypipelinedcore (
    input logic 		    clk, reset,
    // Privileged
    input logic 		    TimerIntM, ExtIntM, SwIntM,

pipelined/src/wally/wallypipelinedsoc.sv

@@ -83,7 +83,7 @@ module wallypipelinedsoc (
   synchronizer resetsync(.clk, .d(reset_ext), .q(reset)); 
    
   // instantiate processor and memories
-  wallypipelinedhart hart(.clk, .reset,
+  wallypipelinedcore core(.clk, .reset,
     .TimerIntM, .ExtIntM, .SwIntM, 
     .MTIME_CLINT,
     .HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA,

pipelined/testbench/common/function_radix.sv

@@ -48,11 +48,11 @@ module FunctionName(reset, clk, ProgramAddrMapFile, ProgramLabelMapFile);
   logic 	    StallD, StallE, FlushD, FlushE;
   integer 	    ProgramAddrIndex;
 
-  assign PCF = testbench.dut.hart.PCF;
-  assign StallD = testbench.dut.hart.StallD;
-  assign StallE = testbench.dut.hart.StallE;  
-  assign FlushD = testbench.dut.hart.FlushD;
-  assign FlushE = testbench.dut.hart.FlushE;
+  assign PCF = testbench.dut.core.PCF;
+  assign StallD = testbench.dut.core.StallD;
+  assign StallE = testbench.dut.core.StallE;  
+  assign FlushD = testbench.dut.core.FlushD;
+  assign FlushE = testbench.dut.core.FlushE;
 
   // copy from ifu
   // when the F and D stages are flushed we need to ensure the PCE is held so that the function name does not

pipelined/testbench/testbench-coremark_bare.sv

@@ -83,23 +83,23 @@ module testbench();
                         .UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK); 
 
   logic [31:0] InstrW;
-  flopenr  #(32)   InstrWReg(clk, reset, ~dut.hart.ieu.dp.StallW,  dut.hart.ifu.InstrM, InstrW);
+  flopenr  #(32)   InstrWReg(clk, reset, ~dut.core.ieu.dp.StallW,  dut.core.ifu.InstrM, InstrW);
 
   // Track names of instructions
-    instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE,
-                dut.hart.ifu.FinalInstrRawF,
-                dut.hart.ifu.InstrD, dut.hart.ifu.InstrE,
-                dut.hart.ifu.InstrM,  InstrW,
+    instrTrackerTB it(clk, reset, dut.core.ieu.dp.FlushE,
+                dut.core.ifu.FinalInstrRawF,
+                dut.core.ifu.InstrD, dut.core.ifu.InstrE,
+                dut.core.ifu.InstrM,  InstrW,
                 InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
 /*
-  instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE,
-                dut.hart.ifu.icache.controller.FinalInstrRawF,
-                dut.hart.ifu.InstrD, dut.hart.ifu.InstrE,
-                dut.hart.ifu.InstrM, InstrW,
+  instrTrackerTB it(clk, reset, dut.core.ieu.dp.FlushE,
+                dut.core.ifu.icache.controller.FinalInstrRawF,
+                dut.core.ifu.InstrD, dut.core.ifu.InstrE,
+                dut.core.ifu.InstrM, InstrW,
                 InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
 */
   logic [`XLEN-1:0] PCW;
-  flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, dut.hart.ifu.PCM, PCW);
+  flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, dut.core.ifu.PCM, PCW);
   
   // initialize tests
   integer j;
@@ -123,7 +123,7 @@ module testbench();
     end
   always @(negedge clk)
     begin
-      if (dut.hart.priv.priv.ecallM) begin
+      if (dut.core.priv.priv.ecallM) begin
         #20;
         $display("Code ended with ebreakM");
         $stop;
@@ -131,10 +131,10 @@ module testbench();
     end
 
   initial begin
-//    $readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.memory);
-//    $readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.bpred.TargetPredictor.memory.memory);
-    $readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem);
-	  $readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.bpred.TargetPredictor.memory.mem);    
+//    $readmemb(`TWO_BIT_PRELOAD, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.memory);
+//    $readmemb(`BTB_PRELOAD, dut.core.ifu.bpred.bpred.TargetPredictor.memory.memory);
+    $readmemb(`TWO_BIT_PRELOAD, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem);
+	  $readmemb(`BTB_PRELOAD, dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem);    
 
   end
    

pipelined/testbench/testbench-fpga.sv

@@ -524,8 +524,8 @@ string tests32f[] = '{
 
   logic 	    DCacheFlushDone, DCacheFlushStart;
     
-  flopenr #(`XLEN) PCWReg(clk, reset, ~dut.wallypipelinedsoc.hart.ieu.dp.StallW, dut.wallypipelinedsoc.hart.ifu.PCM, PCW);
-  flopenr  #(32)   InstrWReg(clk, reset, ~dut.wallypipelinedsoc.hart.ieu.dp.StallW,  dut.wallypipelinedsoc.hart.ifu.InstrM, InstrW);
+  flopenr #(`XLEN) PCWReg(clk, reset, ~dut.wallypipelinedsoc.core.ieu.dp.StallW, dut.wallypipelinedsoc.core.ifu.PCM, PCW);
+  flopenr  #(32)   InstrWReg(clk, reset, ~dut.wallypipelinedsoc.core.ieu.dp.StallW,  dut.wallypipelinedsoc.core.ifu.InstrM, InstrW);
 
   // check assertions for a legal configuration
   riscvassertions riscvassertions();
@@ -611,10 +611,10 @@ string tests32f[] = '{
                         .UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK); 
 
   // Track names of instructions
-  instrTrackerTB it(clk, reset, dut.wallypipelinedsoc.hart.ieu.dp.FlushE,
-                dut.wallypipelinedsoc.hart.ifu.icache.FinalInstrRawF,
-                dut.wallypipelinedsoc.hart.ifu.InstrD, dut.wallypipelinedsoc.hart.ifu.InstrE,
-                dut.wallypipelinedsoc.hart.ifu.InstrM,  InstrW,
+  instrTrackerTB it(clk, reset, dut.wallypipelinedsoc.core.ieu.dp.FlushE,
+                dut.wallypipelinedsoc.core.ifu.icache.FinalInstrRawF,
+                dut.wallypipelinedsoc.core.ifu.InstrD, dut.wallypipelinedsoc.core.ifu.InstrE,
+                dut.wallypipelinedsoc.core.ifu.InstrM,  InstrW,
                 InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
 
   // initialize tests
@@ -666,11 +666,11 @@ string tests32f[] = '{
   always @(negedge clk)
     begin    
 /* -----\/----- EXCLUDED -----\/-----
-      if (dut.wallypipelinedsoc.hart.priv.EcallFaultM & 
-			    (dut.wallypipelinedsoc.hart.ieu.dp.regf.rf[3] == 1 | 
-			     (dut.wallypipelinedsoc.hart.ieu.dp.regf.we3 & 
-			      dut.wallypipelinedsoc.hart.ieu.dp.regf.a3 == 3 & 
-			      dut.wallypipelinedsoc.hart.ieu.dp.regf.wd3 == 1))) begin
+      if (dut.wallypipelinedsoc.core.priv.EcallFaultM & 
+			    (dut.wallypipelinedsoc.core.ieu.dp.regf.rf[3] == 1 | 
+			     (dut.wallypipelinedsoc.core.ieu.dp.regf.we3 & 
+			      dut.wallypipelinedsoc.core.ieu.dp.regf.a3 == 3 & 
+			      dut.wallypipelinedsoc.core.ieu.dp.regf.wd3 == 1))) begin
  -----/\----- EXCLUDED -----/\----- */
       if (DCacheFlushDone) begin
         //$display("Code ended with ecall with gp = 1");
@@ -756,11 +756,11 @@ string tests32f[] = '{
   end
  -----/\----- EXCLUDED -----/\----- */
 
-  assign DCacheFlushStart = dut.wallypipelinedsoc.hart.priv.EcallFaultM & 
-			    (dut.wallypipelinedsoc.hart.ieu.dp.regf.rf[3] == 1 | 
-			     (dut.wallypipelinedsoc.hart.ieu.dp.regf.we3 & 
-			      dut.wallypipelinedsoc.hart.ieu.dp.regf.a3 == 3 & 
-			      dut.wallypipelinedsoc.hart.ieu.dp.regf.wd3 == 1));
+  assign DCacheFlushStart = dut.wallypipelinedsoc.core.priv.EcallFaultM & 
+			    (dut.wallypipelinedsoc.core.ieu.dp.regf.rf[3] == 1 | 
+			     (dut.wallypipelinedsoc.core.ieu.dp.regf.we3 & 
+			      dut.wallypipelinedsoc.core.ieu.dp.regf.a3 == 3 & 
+			      dut.wallypipelinedsoc.core.ieu.dp.regf.wd3 == 1));
   
   DCacheFlushFSM DCacheFlushFSM(.clk(clk),
 				.reset(reset),
@@ -771,8 +771,8 @@ string tests32f[] = '{
   // initialize the branch predictor
   if (`BPRED_ENABLED == 1)
     initial begin
-      $readmemb(`TWO_BIT_PRELOAD, dut.wallypipelinedsoc.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem);
-      $readmemb(`BTB_PRELOAD, dut.wallypipelinedsoc.hart.ifu.bpred.bpred.TargetPredictor.memory.mem);
+      $readmemb(`TWO_BIT_PRELOAD, dut.wallypipelinedsoc.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem);
+      $readmemb(`BTB_PRELOAD, dut.wallypipelinedsoc.core.ifu.bpred.bpred.TargetPredictor.memory.mem);
     end
 endmodule
 
@@ -809,10 +809,10 @@ module DCacheFlushFSM
    input logic start,
    output logic done);
 
-  localparam integer numlines = testbench.dut.wallypipelinedsoc.hart.lsu.bus.dcache.NUMLINES;
-  localparam integer numways = testbench.dut.wallypipelinedsoc.hart.lsu.bus.dcache.NUMWAYS;
-  localparam integer linebytelen = testbench.dut.wallypipelinedsoc.hart.lsu.bus.dcache.LINEBYTELEN;
-  localparam integer numwords = testbench.dut.wallypipelinedsoc.hart.lsu.bus.dcache.LINELEN/`XLEN;  
+  localparam integer numlines = testbench.dut.wallypipelinedsoc.core.lsu.bus.dcache.NUMLINES;
+  localparam integer numways = testbench.dut.wallypipelinedsoc.core.lsu.bus.dcache.NUMWAYS;
+  localparam integer linebytelen = testbench.dut.wallypipelinedsoc.core.lsu.bus.dcache.LINEBYTELEN;
+  localparam integer numwords = testbench.dut.wallypipelinedsoc.core.lsu.bus.dcache.LINELEN/`XLEN;  
   localparam integer lognumlines = $clog2(numlines);
   localparam integer loglinebytelen = $clog2(linebytelen);
   localparam integer lognumways = $clog2(numways);
@@ -836,10 +836,10 @@ module DCacheFlushFSM
         copyShadow #(.tagstart(tagstart), .loglinebytelen(loglinebytelen))
         copyShadow(.clk,
             .start,
-            .tag(testbench.dut.wallypipelinedsoc.hart.lsu.bus.dcache.MemWay[way].CacheTagMem.StoredData[index]),
-            .valid(testbench.dut.wallypipelinedsoc.hart.lsu.bus.dcache.MemWay[way].ValidBits[index]),
-            .dirty(testbench.dut.wallypipelinedsoc.hart.lsu.bus.dcache.MemWay[way].DirtyBits[index]),
-            .data(testbench.dut.wallypipelinedsoc.hart.lsu.bus.dcache.MemWay[way].word[cacheWord].CacheDataMem.StoredData[index]),
+            .tag(testbench.dut.wallypipelinedsoc.core.lsu.bus.dcache.MemWay[way].CacheTagMem.StoredData[index]),
+            .valid(testbench.dut.wallypipelinedsoc.core.lsu.bus.dcache.MemWay[way].ValidBits[index]),
+            .dirty(testbench.dut.wallypipelinedsoc.core.lsu.bus.dcache.MemWay[way].DirtyBits[index]),
+            .data(testbench.dut.wallypipelinedsoc.core.lsu.bus.dcache.MemWay[way].word[cacheWord].CacheDataMem.StoredData[index]),
             .index(index),
             .cacheWord(cacheWord),
             .CacheData(CacheData[way][index][cacheWord]),

pipelined/testbench/testbench-linux.sv

@@ -94,14 +94,14 @@ module testbench;
   logic             InstrValidW;
   logic [`XLEN-1:0] IEUAdrW, WriteDataW;
   logic             TrapW;
-  `define FLUSHW dut.hart.FlushW
-  `define STALLW dut.hart.StallW
-  flopenrc #(`XLEN)         PCWReg(clk, reset, `FLUSHW, ~`STALLW, dut.hart.ifu.PCM, PCW);
-  flopenr #(32)          InstrWReg(clk, reset, ~`STALLW, `FLUSHW ? nop : dut.hart.ifu.InstrM, InstrW);
-  flopenrc #(1)        controlregW(clk, reset, `FLUSHW, ~`STALLW, dut.hart.ieu.c.InstrValidM, InstrValidW);
-  flopenrc #(`XLEN)     IEUAdrWReg(clk, reset, `FLUSHW, ~`STALLW, dut.hart.IEUAdrM, IEUAdrW);
-  flopenrc #(`XLEN)  WriteDataWReg(clk, reset, `FLUSHW, ~`STALLW, dut.hart.WriteDataM, WriteDataW);  
-  flopenr #(1)            TrapWReg(clk, reset, ~`STALLW, dut.hart.hzu.TrapM, TrapW);
+  `define FLUSHW dut.core.FlushW
+  `define STALLW dut.core.StallW
+  flopenrc #(`XLEN)         PCWReg(clk, reset, `FLUSHW, ~`STALLW, dut.core.ifu.PCM, PCW);
+  flopenr #(32)          InstrWReg(clk, reset, ~`STALLW, `FLUSHW ? nop : dut.core.ifu.InstrM, InstrW);
+  flopenrc #(1)        controlregW(clk, reset, `FLUSHW, ~`STALLW, dut.core.ieu.c.InstrValidM, InstrValidW);
+  flopenrc #(`XLEN)     IEUAdrWReg(clk, reset, `FLUSHW, ~`STALLW, dut.core.IEUAdrM, IEUAdrW);
+  flopenrc #(`XLEN)  WriteDataWReg(clk, reset, `FLUSHW, ~`STALLW, dut.core.WriteDataM, WriteDataW);  
+  flopenr #(1)            TrapWReg(clk, reset, ~`STALLW, dut.core.hzu.TrapM, TrapW);
 
   ///////////////////////////////////////////////////////////////////////////////
   //////////////////////// Signals & Macro DECLARATIONS /////////////////////////
@@ -171,9 +171,9 @@ module testbench;
   integer           CheckMIPFutureE;
   integer           CheckMIPFutureM;
   // Useful Aliases
-  `define RF          dut.hart.ieu.dp.regf.rf
-  `define PC          dut.hart.ifu.pcreg.q
-  `define CSR_BASE    dut.hart.priv.priv.csr
+  `define RF          dut.core.ieu.dp.regf.rf
+  `define PC          dut.core.ifu.pcreg.q
+  `define CSR_BASE    dut.core.priv.priv.csr
   `define HPMCOUNTER  `CSR_BASE.counters.counters.HPMCOUNTER_REGW
   `define PMP_BASE    `CSR_BASE.csrm.pmp
   `define PMPCFG      genblk2.PMPCFGreg.q
@@ -209,8 +209,8 @@ module testbench;
   `define STATUS_MIE  `CSR_BASE.csrsr.STATUS_MIE
   `define STATUS_SIE  `CSR_BASE.csrsr.STATUS_SIE
   `define STATUS_UIE  `CSR_BASE.csrsr.STATUS_UIE
-  `define PRIV        dut.hart.priv.priv.privmodereg.q
-  `define INSTRET     dut.hart.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2]
+  `define PRIV        dut.core.priv.priv.privmodereg.q
+  `define INSTRET     dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2]
   // Common Macros
   `define checkCSR(CSR) \
     begin \
@@ -302,12 +302,12 @@ module testbench;
   integer ramFile;
   integer readResult;
   initial begin
-    force dut.hart.priv.priv.SwIntM = 0;
-    force dut.hart.priv.priv.TimerIntM = 0;
-    force dut.hart.priv.priv.ExtIntM = 0;    
+    force dut.core.priv.priv.SwIntM = 0;
+    force dut.core.priv.priv.TimerIntM = 0;
+    force dut.core.priv.priv.ExtIntM = 0;    
     $readmemh({`LINUX_TEST_VECTORS,"bootmem.txt"}, dut.uncore.bootrom.bootrom.RAM, 'h1000 >> 3);
-    $readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem);
-    $readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.bpred.TargetPredictor.memory.mem);
+    $readmemb(`TWO_BIT_PRELOAD, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem);
+    $readmemb(`BTB_PRELOAD, dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem);
     ProgramAddrMapFile = {`LINUX_TEST_VECTORS,"vmlinux.objdump.addr"};
     ProgramLabelMapFile = {`LINUX_TEST_VECTORS,"vmlinux.objdump.lab"};
     if (CHECKPOINT==0) begin // normal
@@ -359,7 +359,7 @@ module testbench;
   // on the next falling edge the expected state is compared to the wally state.
 
   // step 0: read the expected state
-  assign checkInstrM = dut.hart.ieu.InstrValidM & ~dut.hart.priv.priv.trap.InstrPageFaultM & ~dut.hart.priv.priv.trap.InterruptM & ~dut.hart.StallM;
+  assign checkInstrM = dut.core.ieu.InstrValidM & ~dut.core.priv.priv.trap.InstrPageFaultM & ~dut.core.priv.priv.trap.InterruptM & ~dut.core.StallM;
   `define SCAN_NEW_INSTR_FROM_TRACE(STAGE) \
     // always check PC, instruction bits \
     if (checkInstrM) begin \
@@ -438,11 +438,11 @@ module testbench;
       end \
       if(`"STAGE`"=="M") begin \
         // override on special conditions \
-        if (dut.hart.lsu.LSUPAdrM == 'h10000005) \
+        if (dut.core.lsu.LSUPAdrM == 'h10000005) \
           //$display("%tns, %d instrs: Overwrite UART's LSR in memory stage.", $time, InstrCountW-1); \
-          force dut.hart.ieu.dp.ReadDataM = ExpectedMemReadDataM; \
+          force dut.core.ieu.dp.ReadDataM = ExpectedMemReadDataM; \
         else \
-          release dut.hart.ieu.dp.ReadDataM; \
+          release dut.core.ieu.dp.ReadDataM; \
         if(textM.substr(0,5) == "rdtime") begin \
           //$display("%tns, %d instrs: Overwrite MTIME_CLINT on read of MTIME in memory stage.", $time, InstrCountW-1); \
           force dut.uncore.clint.clint.MTIME = ExpectedRegValueM; \
@@ -467,13 +467,13 @@ module testbench;
       // $display("%tns: ExpectedPCM %x",$time,ExpectedPCM);
       // $display("%tns: ExpectedPCE %x",$time,ExpectedPCE);
       // $display("%tns: ExpectedPCW %x",$time,ExpectedPCW);
-      if((ExpectedPCE != MepcExpected) & ((MepcExpected - ExpectedPCE) * (MepcExpected - ExpectedPCE) <= 200) || ~dut.hart.ieu.c.InstrValidM) begin
+      if((ExpectedPCE != MepcExpected) & ((MepcExpected - ExpectedPCE) * (MepcExpected - ExpectedPCE) <= 200) || ~dut.core.ieu.c.InstrValidM) begin
         RequestDelayedMIP <= 1;
         $display("%tns: Requesting Delayed MIP. Current MEPC value is %x",$time,MepcExpected);
       end else begin // update MIP immediately
         $display("%tns: Updating MIP to %x",$time,NextMIPexpected);
         MIPexpected = NextMIPexpected;
-        force dut.hart.priv.priv.csr.csri.MIP_REGW = MIPexpected;
+        force dut.core.priv.priv.csr.csri.MIP_REGW = MIPexpected;
       end
       // $display("%tn: ExpectedCSRArrayM = %p",$time,ExpectedCSRArrayM);
       // $display("%tn: ExpectedCSRArrayValueM = %p",$time,ExpectedCSRArrayValueM);
@@ -485,11 +485,11 @@ module testbench;
       // $display("%tn: ExpectedCSRArrayValueM[NumCSRM] %x",$time,ExpectedCSRArrayValueM[NumCSRM]);
     end
     if(RequestDelayedMIP & checkInstrM) begin
-      $display("%tns: Executing Delayed MIP. Current MEPC value is %x",$time,dut.hart.priv.priv.csr.csrm.MEPC_REGW);
+      $display("%tns: Executing Delayed MIP. Current MEPC value is %x",$time,dut.core.priv.priv.csr.csrm.MEPC_REGW);
       $display("%tns: Updating MIP to %x",$time,NextMIPexpected);
       MIPexpected = NextMIPexpected;
-      force dut.hart.priv.priv.csr.csri.MIP_REGW = MIPexpected;
-      $display("%tns: Finished Executing Delayed MIP. Current MEPC value is %x",$time,dut.hart.priv.priv.csr.csrm.MEPC_REGW);
+      force dut.core.priv.priv.csr.csri.MIP_REGW = MIPexpected;
+      $display("%tns: Finished Executing Delayed MIP. Current MEPC value is %x",$time,dut.core.priv.priv.csr.csrm.MEPC_REGW);
       RequestDelayedMIP = 0;
     end
   end
@@ -508,8 +508,8 @@ module testbench;
       ExpectedMemWriteDataW <= '0;
       ExpectedMemReadDataW <= '0;
       NumCSRW <= '0;
-    end else if(~dut.hart.StallW) begin
-      if(dut.hart.FlushW) begin
+    end else if(~dut.core.StallW) begin
+      if(dut.core.FlushW) begin
         ExpectedPCW <= '0;
         ExpectedInstrW <= '0;
         textW <= "";
@@ -521,7 +521,7 @@ module testbench;
         ExpectedMemWriteDataW <= '0;
         ExpectedMemReadDataW <= '0;
         NumCSRW <= '0;
-      end else if (dut.hart.ieu.c.InstrValidM) begin 
+      end else if (dut.core.ieu.c.InstrValidM) begin 
         ExpectedPCW <= ExpectedPCM;
         ExpectedInstrW <= ExpectedInstrM;
         textW <= textM;
@@ -540,21 +540,21 @@ module testbench;
       end
       #1;
       // override on special conditions
-      if(~dut.hart.StallW) begin
+      if(~dut.core.StallW) begin
         if(textW.substr(0,5) == "rdtime") begin
           //$display("%tns, %d instrs: Releasing force of MTIME_CLINT.", $time, InstrCountW);
           release dut.uncore.clint.clint.MTIME;
         end 
         //if (ExpectedIEUAdrM == 'h10000005) begin
           //$display("%tns, %d instrs: releasing force of ReadDataM.", $time, InstrCountW);
-          //release dut.hart.ieu.dp.ReadDataM;
+          //release dut.core.ieu.dp.ReadDataM;
         //end
       end
     end
   end
   
   // step2: make all checks in the write back stage.
-  assign checkInstrW =              InstrValidW & ~dut.hart.StallW; // trapW will already be invalid in there was an InstrPageFault in the previous instruction.
+  assign checkInstrW =              InstrValidW & ~dut.core.StallW; // trapW will already be invalid in there was an InstrPageFault in the previous instruction.
   always @(negedge clk) begin
     // always check PC, instruction bits
     if (checkInstrW) begin
@@ -570,23 +570,23 @@ module testbench;
         `checkEQ("PCW",PCW,ExpectedPCW)
         //`checkEQ("InstrW",InstrW,ExpectedInstrW) <-- not viable because of
         // compressed to uncompressed conversion
-        `checkEQ("Instr Count",dut.hart.priv.priv.csr.counters.counters.INSTRET_REGW,InstrCountW)
+        `checkEQ("Instr Count",dut.core.priv.priv.csr.counters.counters.INSTRET_REGW,InstrCountW)
         #2; // delay 2 ns.
         if(`DEBUG_TRACE >= 5) begin
-          $display("%tns, %d instrs: Reg Write Address %02d ? expected value: %02d", $time, InstrCountW, dut.hart.ieu.dp.regf.a3, ExpectedRegAdrW);
-          $display("%tns, %d instrs: RF[%02d] %016x ? expected value: %016x", $time, InstrCountW, ExpectedRegAdrW, dut.hart.ieu.dp.regf.rf[ExpectedRegAdrW], ExpectedRegValueW);
+          $display("%tns, %d instrs: Reg Write Address %02d ? expected value: %02d", $time, InstrCountW, dut.core.ieu.dp.regf.a3, ExpectedRegAdrW);
+          $display("%tns, %d instrs: RF[%02d] %016x ? expected value: %016x", $time, InstrCountW, ExpectedRegAdrW, dut.core.ieu.dp.regf.rf[ExpectedRegAdrW], ExpectedRegValueW);
         end
         if (RegWriteW == "GPR") begin
-          `checkEQ("Reg Write Address",dut.hart.ieu.dp.regf.a3,ExpectedRegAdrW)
+          `checkEQ("Reg Write Address",dut.core.ieu.dp.regf.a3,ExpectedRegAdrW)
           $sformat(name,"RF[%02d]",ExpectedRegAdrW);
-          `checkEQ(name, dut.hart.ieu.dp.regf.rf[ExpectedRegAdrW], ExpectedRegValueW)
+          `checkEQ(name, dut.core.ieu.dp.regf.rf[ExpectedRegAdrW], ExpectedRegValueW)
         end
         if (MemOpW.substr(0,2) == "Mem") begin
           if(`DEBUG_TRACE >= 4) $display("\tIEUAdrW: %016x ? expected: %016x", IEUAdrW, ExpectedIEUAdrW);
           `checkEQ("IEUAdrW",IEUAdrW,ExpectedIEUAdrW)
           if(MemOpW == "MemR" || MemOpW == "MemRW") begin
-            if(`DEBUG_TRACE >= 4) $display("\tReadDataW: %016x ? expected: %016x", dut.hart.ieu.dp.ReadDataW, ExpectedMemReadDataW);
-            `checkEQ("ReadDataW",dut.hart.ieu.dp.ReadDataW,ExpectedMemReadDataW)
+            if(`DEBUG_TRACE >= 4) $display("\tReadDataW: %016x ? expected: %016x", dut.core.ieu.dp.ReadDataW, ExpectedMemReadDataW);
+            `checkEQ("ReadDataW",dut.core.ieu.dp.ReadDataW,ExpectedMemReadDataW)
           end else if(MemOpW == "MemW" || MemOpW == "MemRW") begin
             if(`DEBUG_TRACE >= 4) $display("\tWriteDataW: %016x ? expected: %016x", WriteDataW, ExpectedMemWriteDataW);
             `checkEQ("WriteDataW",ExpectedMemWriteDataW,ExpectedMemWriteDataW)
@@ -595,19 +595,19 @@ module testbench;
         // check csr
         for(NumCSRPostWIndex = 0; NumCSRPostWIndex < NumCSRW; NumCSRPostWIndex++) begin
           case(ExpectedCSRArrayW[NumCSRPostWIndex])
-            "mhartid": `checkCSR(dut.hart.priv.priv.csr.csrm.MHARTID_REGW)
-            "mstatus": `checkCSR(dut.hart.priv.priv.csr.csrm.MSTATUS_REGW)
-            "mtvec":   `checkCSR(dut.hart.priv.priv.csr.csrm.MTVEC_REGW)
-            "mip":     `checkCSR(dut.hart.priv.priv.csr.csrm.MIP_REGW)
-            "mie":     `checkCSR(dut.hart.priv.priv.csr.csrm.MIE_REGW)
-            "mideleg": `checkCSR(dut.hart.priv.priv.csr.csrm.MIDELEG_REGW)
-            "medeleg": `checkCSR(dut.hart.priv.priv.csr.csrm.MEDELEG_REGW)
-            "mepc":    `checkCSR(dut.hart.priv.priv.csr.csrm.MEPC_REGW)
-            "mtval":   `checkCSR(dut.hart.priv.priv.csr.csrm.MTVAL_REGW)
-            "sepc":    `checkCSR(dut.hart.priv.priv.csr.csrs.SEPC_REGW)
-            "scause":  `checkCSR(dut.hart.priv.priv.csr.csrs.csrs.SCAUSE_REGW)
-            "stvec":   `checkCSR(dut.hart.priv.priv.csr.csrs.STVEC_REGW)
-            "stval":   `checkCSR(dut.hart.priv.priv.csr.csrs.csrs.STVAL_REGW)
+            "mhartid": `checkCSR(dut.core.priv.priv.csr.csrm.MHARTID_REGW)
+            "mstatus": `checkCSR(dut.core.priv.priv.csr.csrm.MSTATUS_REGW)
+            "mtvec":   `checkCSR(dut.core.priv.priv.csr.csrm.MTVEC_REGW)
+            "mip":     `checkCSR(dut.core.priv.priv.csr.csrm.MIP_REGW)
+            "mie":     `checkCSR(dut.core.priv.priv.csr.csrm.MIE_REGW)
+            "mideleg": `checkCSR(dut.core.priv.priv.csr.csrm.MIDELEG_REGW)
+            "medeleg": `checkCSR(dut.core.priv.priv.csr.csrm.MEDELEG_REGW)
+            "mepc":    `checkCSR(dut.core.priv.priv.csr.csrm.MEPC_REGW)
+            "mtval":   `checkCSR(dut.core.priv.priv.csr.csrm.MTVAL_REGW)
+            "sepc":    `checkCSR(dut.core.priv.priv.csr.csrs.SEPC_REGW)
+            "scause":  `checkCSR(dut.core.priv.priv.csr.csrs.csrs.SCAUSE_REGW)
+            "stvec":   `checkCSR(dut.core.priv.priv.csr.csrs.STVEC_REGW)
+            "stval":   `checkCSR(dut.core.priv.priv.csr.csrs.csrs.STVAL_REGW)
           endcase
         end
         if (fault == 1) begin
@@ -635,10 +635,10 @@ module testbench;
   // Instr Opcode Tracking
   //   For waveview convenience
   string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
-  instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE,
-                dut.hart.ifu.FinalInstrRawF,
-                dut.hart.ifu.InstrD, dut.hart.ifu.InstrE,
-                dut.hart.ifu.InstrM,  InstrW,
+  instrTrackerTB it(clk, reset, dut.core.ieu.dp.FlushE,
+                dut.core.ifu.FinalInstrRawF,
+                dut.core.ifu.InstrD, dut.core.ifu.InstrE,
+                dut.core.ifu.InstrM,  InstrW,
                 InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
 
   // ------------------
@@ -661,7 +661,7 @@ module testbench;
     begin
       int i;
       // Grab the SATP register from privileged unit
-      SATP = dut.hart.priv.priv.csr.SATP_REGW;
+      SATP = dut.core.priv.priv.csr.SATP_REGW;
       // Split the virtual address into page number segments and offset
       VPN[2] = adrIn[38:30];
       VPN[1] = adrIn[29:21];
@@ -671,7 +671,7 @@ module testbench;
       SvMode = SATP[63];
       // Only perform translation if translation is on and the processor is not
       // in machine mode
-      if (SvMode & (dut.hart.priv.priv.PrivilegeModeW != `M_MODE)) begin
+      if (SvMode & (dut.core.priv.priv.PrivilegeModeW != `M_MODE)) begin
         BaseAdr = SATP[43:0] << 12;
         for (i = 2; i >= 0; i--) begin
           PAdr = BaseAdr + (VPN[i] << 3);

pipelined/testbench/testbench-tim.sv

@@ -71,8 +71,8 @@ logic [3:0] dummy;
 
   logic 	    DCacheFlushDone, DCacheFlushStart;
     
-  flopenr #(`XLEN) PCWReg(clk, reset, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.PCM, PCW);
-  flopenr  #(32)   InstrWReg(clk, reset, ~dut.hart.ieu.dp.StallW,  dut.hart.ifu.InstrM, InstrW);
+  flopenr #(`XLEN) PCWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.PCM, PCW);
+  flopenr  #(32)   InstrWReg(clk, reset, ~dut.core.ieu.dp.StallW,  dut.core.ifu.InstrM, InstrW);
 
   // check assertions for a legal configuration
   riscvassertions riscvassertions();
@@ -160,10 +160,10 @@ logic [3:0] dummy;
                         .UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK); 
 
   // Track names of instructions
-  instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE,
-                dut.hart.ifu.FinalInstrRawF,
-                dut.hart.ifu.InstrD, dut.hart.ifu.InstrE,
-                dut.hart.ifu.InstrM,  InstrW,
+  instrTrackerTB it(clk, reset, dut.core.ieu.dp.FlushE,
+                dut.core.ifu.FinalInstrRawF,
+                dut.core.ifu.InstrD, dut.core.ifu.InstrE,
+                dut.core.ifu.InstrM,  InstrW,
                 InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
 
   // initialize tests
@@ -196,15 +196,15 @@ logic [3:0] dummy;
       else pathname = tvpaths[1]; */
       memfilename = {pathname, tests[test], ".elf.memfile"};
       //$readmemh(memfilename, dut.uncore.ram.ram.RAM);
-      $readmemh(memfilename, dut.hart.lsu.dtim.ram.RAM);      
-//      if(`MEM_DTIM == 1) $readmemh(memfilename, dut.hart.lsu.dtim.ram.RAM);
+      $readmemh(memfilename, dut.core.lsu.dtim.ram.RAM);      
+//      if(`MEM_DTIM == 1) $readmemh(memfilename, dut.core.lsu.dtim.ram.RAM);
 //`ifdef `MEM_IROM
 //          $display("here!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!");
-//      $readmemh(memfilename, dut.hart.ifu.irom.ram.RAM);
+//      $readmemh(memfilename, dut.core.ifu.irom.ram.RAM);
 //`endif
 //      if(`MEM_IROM == 1) begin
 //        $display("here!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!");
-        $readmemh(memfilename, dut.hart.ifu.irom.ram.RAM);
+        $readmemh(memfilename, dut.core.ifu.irom.ram.RAM);
 //      end
       ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"};
       ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};
@@ -258,7 +258,7 @@ logic [3:0] dummy;
         while (signature[i] !== 'bx) begin
           //$display("signature[%h] = %h", i, signature[i]);
 		  // *** have to figure out how to exclude shadowram when not using a dcache.
-          if (signature[i] !== dut.hart.lsu.dtim.ram.RAM[testadr+i] &
+          if (signature[i] !== dut.core.lsu.dtim.ram.RAM[testadr+i] &
 	      (signature[i] !== DCacheFlushFSM.ShadowRAM[testadr+i])) begin
             if (signature[i+4] !== 'bx | signature[i] !== 32'hFFFFFFFF) begin
               // report errors unless they are garbage at the end of the sim
@@ -266,7 +266,7 @@ logic [3:0] dummy;
               errors = errors+1;
               $display("  Error on test %s result %d: adr = %h sim (D$) %h sim (TIM) = %h, signature = %h", 
                     //tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], dut.uncore.ram.ram.RAM[testadr+i], signature[i]);
-                       tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], dut.hart.lsu.dtim.ram.RAM[testadr+i], signature[i]);
+                       tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], dut.core.lsu.dtim.ram.RAM[testadr+i], signature[i]);
               $stop;//***debug
             end
           end
@@ -290,16 +290,16 @@ logic [3:0] dummy;
             //pathname = tvpaths[tests[0]];
             memfilename = {pathname, tests[test], ".elf.memfile"};
             //$readmemh(memfilename, dut.uncore.ram.ram.RAM);
-            $readmemh(memfilename, dut.hart.lsu.dtim.ram.RAM);
-            //if(`MEM_DTIM == 1) $readmemh(memfilename, dut.hart.lsu.dtim.ram.RAM);
+            $readmemh(memfilename, dut.core.lsu.dtim.ram.RAM);
+            //if(`MEM_DTIM == 1) $readmemh(memfilename, dut.core.lsu.dtim.ram.RAM);
 /* -----\/----- EXCLUDED -----\/-----
 `ifdef `MEM_IROM
           $display("here!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!");
-            $readmemh(memfilename, dut.hart.ifu.irom.ram.RAM);
+            $readmemh(memfilename, dut.core.ifu.irom.ram.RAM);
 `endif
  -----/\----- EXCLUDED -----/\----- */
-          $readmemh(memfilename, dut.hart.ifu.irom.ram.RAM);
-          //if(`MEM_IROM == 1) $readmemh(memfilename, dut.hart.ifu.irom.ram.RAM);      
+          $readmemh(memfilename, dut.core.ifu.irom.ram.RAM);
+          //if(`MEM_IROM == 1) $readmemh(memfilename, dut.core.ifu.irom.ram.RAM);      
             ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"};
             ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};
             $display("Read memfile %s", memfilename);
@@ -322,14 +322,14 @@ logic [3:0] dummy;
   // or sd gp, -56(t0) 
   // or on a jump to self infinite loop (6f) for RISC-V Arch tests
   logic ecf; // remove this once we don't rely on old Imperas tests with Ecalls
-  if (`ZICSR_SUPPORTED) assign ecf = dut.hart.priv.priv.EcallFaultM;
+  if (`ZICSR_SUPPORTED) assign ecf = dut.core.priv.priv.EcallFaultM;
   else                  assign ecf = 0;
   assign DCacheFlushStart = ecf & 
-			    (dut.hart.ieu.dp.regf.rf[3] == 1 | 
-			     (dut.hart.ieu.dp.regf.we3 & 
-			      dut.hart.ieu.dp.regf.a3 == 3 & 
-			      dut.hart.ieu.dp.regf.wd3 == 1)) |
-          (dut.hart.ifu.InstrM == 32'h6f | dut.hart.ifu.InstrM == 32'hfc32a423 | dut.hart.ifu.InstrM == 32'hfc32a823) & dut.hart.ieu.c.InstrValidM;
+			    (dut.core.ieu.dp.regf.rf[3] == 1 | 
+			     (dut.core.ieu.dp.regf.we3 & 
+			      dut.core.ieu.dp.regf.a3 == 3 & 
+			      dut.core.ieu.dp.regf.wd3 == 1)) |
+          (dut.core.ifu.InstrM == 32'h6f | dut.core.ifu.InstrM == 32'hfc32a423 | dut.core.ifu.InstrM == 32'hfc32a823) & dut.core.ieu.c.InstrValidM;
 
   DCacheFlushFSM DCacheFlushFSM(.clk(clk),
     			.reset(reset),
@@ -339,8 +339,8 @@ logic [3:0] dummy;
   // initialize the branch predictor
   if (`BPRED_ENABLED == 1) 
     initial begin
-      $readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem);
-      $readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.bpred.TargetPredictor.memory.mem);    
+      $readmemb(`TWO_BIT_PRELOAD, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem);
+      $readmemb(`BTB_PRELOAD, dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem);    
     end 
 endmodule
 
@@ -385,10 +385,10 @@ module DCacheFlushFSM
   logic [`XLEN-1:0] ShadowRAM[`RAM_BASE>>(1+`XLEN/32):(`RAM_RANGE+`RAM_BASE)>>1+(`XLEN/32)];
   
 	if(`MEM_DCACHE) begin
-	  localparam integer numlines = testbench.dut.hart.lsu.bus.dcache.dcache.NUMLINES;
-	  localparam integer numways = testbench.dut.hart.lsu.bus.dcache.dcache.NUMWAYS;
-	  localparam integer linebytelen = testbench.dut.hart.lsu.bus.dcache.dcache.LINEBYTELEN;
-	  localparam integer numwords = testbench.dut.hart.lsu.bus.dcache.dcache.LINELEN/`XLEN;  
+	  localparam integer numlines = testbench.dut.core.lsu.bus.dcache.dcache.NUMLINES;
+	  localparam integer numways = testbench.dut.core.lsu.bus.dcache.dcache.NUMWAYS;
+	  localparam integer linebytelen = testbench.dut.core.lsu.bus.dcache.dcache.LINEBYTELEN;
+	  localparam integer numwords = testbench.dut.core.lsu.bus.dcache.dcache.LINELEN/`XLEN;  
 	  localparam integer lognumlines = $clog2(numlines);
 	  localparam integer loglinebytelen = $clog2(linebytelen);
 	  localparam integer lognumways = $clog2(numways);
@@ -409,10 +409,10 @@ module DCacheFlushFSM
 						 .loglinebytelen(loglinebytelen))
 			copyShadow(.clk,
 					   .start,
-					   .tag(testbench.dut.hart.lsu.bus.dcache.dcache.MemWay[way].CacheTagMem.StoredData[index]),
-					   .valid(testbench.dut.hart.lsu.bus.dcache.dcache.MemWay[way].ValidBits[index]),
-					   .dirty(testbench.dut.hart.lsu.bus.dcache.dcache.MemWay[way].DirtyBits[index]),
-					   .data(testbench.dut.hart.lsu.bus.dcache.dcache.MemWay[way].word[cacheWord].CacheDataMem.StoredData[index]),
+					   .tag(testbench.dut.core.lsu.bus.dcache.dcache.MemWay[way].CacheTagMem.StoredData[index]),
+					   .valid(testbench.dut.core.lsu.bus.dcache.dcache.MemWay[way].ValidBits[index]),
+					   .dirty(testbench.dut.core.lsu.bus.dcache.dcache.MemWay[way].DirtyBits[index]),
+					   .data(testbench.dut.core.lsu.bus.dcache.dcache.MemWay[way].word[cacheWord].CacheDataMem.StoredData[index]),
 					   .index(index),
 					   .cacheWord(cacheWord),
 					   .CacheData(CacheData[way][index][cacheWord]),

pipelined/testbench/testbench.sv

@@ -71,8 +71,8 @@ logic [3:0] dummy;
 
   logic 	    DCacheFlushDone, DCacheFlushStart;
     
-  flopenr #(`XLEN) PCWReg(clk, reset, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.PCM, PCW);
-  flopenr  #(32)   InstrWReg(clk, reset, ~dut.hart.ieu.dp.StallW,  dut.hart.ifu.InstrM, InstrW);
+  flopenr #(`XLEN) PCWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.PCM, PCW);
+  flopenr  #(32)   InstrWReg(clk, reset, ~dut.core.ieu.dp.StallW,  dut.core.ifu.InstrM, InstrW);
 
   // check assertions for a legal configuration
   riscvassertions riscvassertions();
@@ -160,10 +160,10 @@ logic [3:0] dummy;
                         .UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK); 
 
   // Track names of instructions
-  instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE,
-                dut.hart.ifu.FinalInstrRawF,
-                dut.hart.ifu.InstrD, dut.hart.ifu.InstrE,
-                dut.hart.ifu.InstrM,  InstrW,
+  instrTrackerTB it(clk, reset, dut.core.ieu.dp.FlushE,
+                dut.core.ifu.FinalInstrRawF,
+                dut.core.ifu.InstrD, dut.core.ifu.InstrE,
+                dut.core.ifu.InstrM,  InstrW,
                 InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
 
   // initialize tests
@@ -196,7 +196,7 @@ logic [3:0] dummy;
       else pathname = tvpaths[1]; */
       memfilename = {pathname, tests[test], ".elf.memfile"};
       $readmemh(memfilename, dut.uncore.ram.ram.RAM);
-      //if(`MEM_DTIM == 1) $readmemh(memfilename, dut.hart.lsu.dtim.ram.RAM);
+      //if(`MEM_DTIM == 1) $readmemh(memfilename, dut.core.lsu.dtim.ram.RAM);
       ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"};
       ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};
       $display("Read memfile %s", memfilename);
@@ -250,7 +250,7 @@ logic [3:0] dummy;
           //$display("signature[%h] = %h", i, signature[i]);
 		  // *** have to figure out how to exclude shadowram when not using a dcache.
           if (signature[i] !== dut.uncore.ram.ram.RAM[testadr+i] &
-          //if (signature[i] !== dut.hart.lsu.dtim.ram.RAM[testadr+i] &
+          //if (signature[i] !== dut.core.lsu.dtim.ram.RAM[testadr+i] &
 	      (signature[i] !== DCacheFlushFSM.ShadowRAM[testadr+i])) begin
             if (signature[i+4] !== 'bx | signature[i] !== 32'hFFFFFFFF) begin
               // report errors unless they are garbage at the end of the sim
@@ -258,7 +258,7 @@ logic [3:0] dummy;
               errors = errors+1;
               $display("  Error on test %s result %d: adr = %h sim (D$) %h sim (TIM) = %h, signature = %h", 
                     tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], dut.uncore.ram.ram.RAM[testadr+i], signature[i]);
-                    //   tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], dut.hart.lsu.dtim.ram.RAM[testadr+i], signature[i]);
+                    //   tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], dut.core.lsu.dtim.ram.RAM[testadr+i], signature[i]);
               $stop;//***debug
             end
           end
@@ -282,7 +282,7 @@ logic [3:0] dummy;
             //pathname = tvpaths[tests[0]];
             memfilename = {pathname, tests[test], ".elf.memfile"};
             $readmemh(memfilename, dut.uncore.ram.ram.RAM);
-            //if(`MEM_DTIM == 1) $readmemh(memfilename, dut.hart.lsu.dtim.ram.RAM);
+            //if(`MEM_DTIM == 1) $readmemh(memfilename, dut.core.lsu.dtim.ram.RAM);
             ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"};
             ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};
             $display("Read memfile %s", memfilename);
@@ -305,14 +305,14 @@ logic [3:0] dummy;
   // or sd gp, -56(t0) 
   // or on a jump to self infinite loop (6f) for RISC-V Arch tests
   logic ecf; // remove this once we don't rely on old Imperas tests with Ecalls
-  if (`ZICSR_SUPPORTED) assign ecf = dut.hart.priv.priv.EcallFaultM;
+  if (`ZICSR_SUPPORTED) assign ecf = dut.core.priv.priv.EcallFaultM;
   else                  assign ecf = 0;
   assign DCacheFlushStart = ecf & 
-			    (dut.hart.ieu.dp.regf.rf[3] == 1 | 
-			     (dut.hart.ieu.dp.regf.we3 & 
-			      dut.hart.ieu.dp.regf.a3 == 3 & 
-			      dut.hart.ieu.dp.regf.wd3 == 1)) |
-          (dut.hart.ifu.InstrM == 32'h6f | dut.hart.ifu.InstrM == 32'hfc32a423 | dut.hart.ifu.InstrM == 32'hfc32a823) & dut.hart.ieu.c.InstrValidM;
+			    (dut.core.ieu.dp.regf.rf[3] == 1 | 
+			     (dut.core.ieu.dp.regf.we3 & 
+			      dut.core.ieu.dp.regf.a3 == 3 & 
+			      dut.core.ieu.dp.regf.wd3 == 1)) |
+          (dut.core.ifu.InstrM == 32'h6f | dut.core.ifu.InstrM == 32'hfc32a423 | dut.core.ifu.InstrM == 32'hfc32a823) & dut.core.ieu.c.InstrValidM;
 
   DCacheFlushFSM DCacheFlushFSM(.clk(clk),
     			.reset(reset),
@@ -322,8 +322,8 @@ logic [3:0] dummy;
   // initialize the branch predictor
   if (`BPRED_ENABLED == 1) 
     initial begin
-      $readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem);
-      $readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.bpred.TargetPredictor.memory.mem);    
+      $readmemb(`TWO_BIT_PRELOAD, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem);
+      $readmemb(`BTB_PRELOAD, dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem);    
     end 
 endmodule
 
@@ -370,10 +370,10 @@ module DCacheFlushFSM
   logic [`XLEN-1:0] ShadowRAM[`RAM_BASE>>(1+`XLEN/32):(`RAM_RANGE+`RAM_BASE)>>1+(`XLEN/32)];
   
 	if(`MEM_DCACHE) begin
-	  localparam integer numlines = testbench.dut.hart.lsu.bus.dcache.dcache.NUMLINES;
-	  localparam integer numways = testbench.dut.hart.lsu.bus.dcache.dcache.NUMWAYS;
-	  localparam integer linebytelen = testbench.dut.hart.lsu.bus.dcache.dcache.LINEBYTELEN;
-	  localparam integer numwords = testbench.dut.hart.lsu.bus.dcache.dcache.LINELEN/`XLEN;  
+	  localparam integer numlines = testbench.dut.core.lsu.bus.dcache.dcache.NUMLINES;
+	  localparam integer numways = testbench.dut.core.lsu.bus.dcache.dcache.NUMWAYS;
+	  localparam integer linebytelen = testbench.dut.core.lsu.bus.dcache.dcache.LINEBYTELEN;
+	  localparam integer numwords = testbench.dut.core.lsu.bus.dcache.dcache.LINELEN/`XLEN;  
 	  localparam integer lognumlines = $clog2(numlines);
 	  localparam integer loglinebytelen = $clog2(linebytelen);
 	  localparam integer lognumways = $clog2(numways);
@@ -394,10 +394,10 @@ module DCacheFlushFSM
 						 .loglinebytelen(loglinebytelen))
 			copyShadow(.clk,
 					   .start,
-					   .tag(testbench.dut.hart.lsu.bus.dcache.dcache.MemWay[way].CacheTagMem.StoredData[index]),
-					   .valid(testbench.dut.hart.lsu.bus.dcache.dcache.MemWay[way].ValidBits[index]),
-					   .dirty(testbench.dut.hart.lsu.bus.dcache.dcache.MemWay[way].DirtyBits[index]),
-					   .data(testbench.dut.hart.lsu.bus.dcache.dcache.MemWay[way].word[cacheWord].CacheDataMem.StoredData[index]),
+					   .tag(testbench.dut.core.lsu.bus.dcache.dcache.MemWay[way].CacheTagMem.StoredData[index]),
+					   .valid(testbench.dut.core.lsu.bus.dcache.dcache.MemWay[way].ValidBits[index]),
+					   .dirty(testbench.dut.core.lsu.bus.dcache.dcache.MemWay[way].DirtyBits[index]),
+					   .data(testbench.dut.core.lsu.bus.dcache.dcache.MemWay[way].word[cacheWord].CacheDataMem.StoredData[index]),
 					   .index(index),
 					   .cacheWord(cacheWord),
 					   .CacheData(CacheData[way][index][cacheWord]),

setup.sh

@@ -4,7 +4,7 @@
 # David_Harris@hmc.edu and kekim@hmc.edu 1 December 2021
 # Set up tools for riscv-wally
 
-echo "Executing wally-setup.sh"
+echo "Executing Wally setup.sh"
 
 # Path to RISC-V Tools
 export RISCV=/opt/riscv   # change this if you installed the tools in a different location

tests/linux-testgen/qemu-patches/README

@@ -0,0 +1,2 @@
+replace /qemu/target/riscv/cpu.c with the provided cpu.c
+replace /qemu/hw/riscv/virt.c with the provided virt.c

tests/linux-testgen/qemu-patches/cpu.c

@@ -0,0 +1,722 @@
+/*
+ * QEMU RISC-V CPU
+ *
+ * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
+ * Copyright (c) 2017-2018 SiFive, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/qemu-print.h"
+#include "qemu/ctype.h"
+#include "qemu/log.h"
+#include "cpu.h"
+#include "internals.h"
+#include "exec/exec-all.h"
+#include "qapi/error.h"
+#include "qemu/error-report.h"
+#include "hw/qdev-properties.h"
+#include "migration/vmstate.h"
+#include "fpu/softfloat-helpers.h"
+
+/* RISC-V CPU definitions */
+
+static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG";
+
+const char * const riscv_int_regnames[] = {
+  "x0/zero", "x1/ra",  "x2/sp",  "x3/gp",  "x4/tp",  "x5/t0",   "x6/t1",
+  "x7/t2",   "x8/s0",  "x9/s1",  "x10/a0", "x11/a1", "x12/a2",  "x13/a3",
+  "x14/a4",  "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3",  "x20/s4",
+  "x21/s5",  "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11",
+  "x28/t3",  "x29/t4", "x30/t5", "x31/t6"
+};
+
+const char * const riscv_fpr_regnames[] = {
+  "f0/ft0",   "f1/ft1",  "f2/ft2",   "f3/ft3",   "f4/ft4",  "f5/ft5",
+  "f6/ft6",   "f7/ft7",  "f8/fs0",   "f9/fs1",   "f10/fa0", "f11/fa1",
+  "f12/fa2",  "f13/fa3", "f14/fa4",  "f15/fa5",  "f16/fa6", "f17/fa7",
+  "f18/fs2",  "f19/fs3", "f20/fs4",  "f21/fs5",  "f22/fs6", "f23/fs7",
+  "f24/fs8",  "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9",
+  "f30/ft10", "f31/ft11"
+};
+
+const char * const riscv_excp_names[] = {
+    "misaligned_fetch",
+    "fault_fetch",
+    "illegal_instruction",
+    "breakpoint",
+    "misaligned_load",
+    "fault_load",
+    "misaligned_store",
+    "fault_store",
+    "user_ecall",
+    "supervisor_ecall",
+    "hypervisor_ecall",
+    "machine_ecall",
+    "exec_page_fault",
+    "load_page_fault",
+    "reserved",
+    "store_page_fault",
+    "reserved",
+    "reserved",
+    "reserved",
+    "reserved",
+    "guest_exec_page_fault",
+    "guest_load_page_fault",
+    "reserved",
+    "guest_store_page_fault",
+};
+
+const char * const riscv_intr_names[] = {
+    "u_software",
+    "s_software",
+    "vs_software",
+    "m_software",
+    "u_timer",
+    "s_timer",
+    "vs_timer",
+    "m_timer",
+    "u_external",
+    "vs_external",
+    "h_external",
+    "m_external",
+    "reserved",
+    "reserved",
+    "reserved",
+    "reserved"
+};
+
+const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
+{
+    if (async) {
+        return (cause < ARRAY_SIZE(riscv_intr_names)) ?
+               riscv_intr_names[cause] : "(unknown)";
+    } else {
+        return (cause < ARRAY_SIZE(riscv_excp_names)) ?
+               riscv_excp_names[cause] : "(unknown)";
+    }
+}
+
+bool riscv_cpu_is_32bit(CPURISCVState *env)
+{
+    if (env->misa & RV64) {
+        return false;
+    }
+
+    return true;
+}
+
+static void set_misa(CPURISCVState *env, target_ulong misa)
+{
+    env->misa_mask = env->misa = misa;
+}
+
+static void set_priv_version(CPURISCVState *env, int priv_ver)
+{
+    env->priv_ver = priv_ver;
+}
+
+static void set_vext_version(CPURISCVState *env, int vext_ver)
+{
+    env->vext_ver = vext_ver;
+}
+
+static void set_feature(CPURISCVState *env, int feature)
+{
+    env->features |= (1ULL << feature);
+}
+
+static void set_resetvec(CPURISCVState *env, int resetvec)
+{
+#ifndef CONFIG_USER_ONLY
+    env->resetvec = resetvec;
+#endif
+}
+
+static void riscv_any_cpu_init(Object *obj)
+{
+    CPURISCVState *env = &RISCV_CPU(obj)->env;
+    set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
+    set_priv_version(env, PRIV_VERSION_1_11_0);
+}
+
+#if defined(TARGET_RISCV64)
+static void rv64_base_cpu_init(Object *obj)
+{
+    CPURISCVState *env = &RISCV_CPU(obj)->env;
+    /* We set this in the realise function */
+    set_misa(env, RV64);
+}
+
+static void rv64_sifive_u_cpu_init(Object *obj)
+{
+    CPURISCVState *env = &RISCV_CPU(obj)->env;
+    set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
+    set_priv_version(env, PRIV_VERSION_1_10_0);
+}
+
+static void rv64_sifive_e_cpu_init(Object *obj)
+{
+    CPURISCVState *env = &RISCV_CPU(obj)->env;
+    set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU);
+    set_priv_version(env, PRIV_VERSION_1_10_0);
+    qdev_prop_set_bit(DEVICE(obj), "mmu", false);
+}
+#else
+static void rv32_base_cpu_init(Object *obj)
+{
+    CPURISCVState *env = &RISCV_CPU(obj)->env;
+    /* We set this in the realise function */
+    set_misa(env, RV32);
+}
+
+static void rv32_sifive_u_cpu_init(Object *obj)
+{
+    CPURISCVState *env = &RISCV_CPU(obj)->env;
+    set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
+    set_priv_version(env, PRIV_VERSION_1_10_0);
+}
+
+static void rv32_sifive_e_cpu_init(Object *obj)
+{
+    CPURISCVState *env = &RISCV_CPU(obj)->env;
+    set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU);
+    set_priv_version(env, PRIV_VERSION_1_10_0);
+    qdev_prop_set_bit(DEVICE(obj), "mmu", false);
+}
+
+static void rv32_ibex_cpu_init(Object *obj)
+{
+    CPURISCVState *env = &RISCV_CPU(obj)->env;
+    set_misa(env, RV32 | RVI | RVM | RVC | RVU);
+    set_priv_version(env, PRIV_VERSION_1_10_0);
+    qdev_prop_set_bit(DEVICE(obj), "mmu", false);
+}
+
+static void rv32_imafcu_nommu_cpu_init(Object *obj)
+{
+    CPURISCVState *env = &RISCV_CPU(obj)->env;
+    set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVC | RVU);
+    set_priv_version(env, PRIV_VERSION_1_10_0);
+    set_resetvec(env, DEFAULT_RSTVEC);
+    qdev_prop_set_bit(DEVICE(obj), "mmu", false);
+}
+#endif
+
+static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
+{
+    ObjectClass *oc;
+    char *typename;
+    char **cpuname;
+
+    cpuname = g_strsplit(cpu_model, ",", 1);
+    typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]);
+    oc = object_class_by_name(typename);
+    g_strfreev(cpuname);
+    g_free(typename);
+    if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) ||
+        object_class_is_abstract(oc)) {
+        return NULL;
+    }
+    return oc;
+}
+
+static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
+{
+    RISCVCPU *cpu = RISCV_CPU(cs);
+    CPURISCVState *env = &cpu->env;
+    int i;
+
+#if !defined(CONFIG_USER_ONLY)
+    if (riscv_has_ext(env, RVH)) {
+        qemu_fprintf(f, " %s %d\n", "V      =  ", riscv_cpu_virt_enabled(env));
+    }
+#endif
+    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc      ", env->pc);
+#ifndef CONFIG_USER_ONLY
+
+    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcounteren ", env->mcounteren);
+    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "misa ", env->misa);
+    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mscratch ", env->mscratch);
+    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "satp ", env->satp);
+    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "scounteren ", env->scounteren);
+    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sscratch ", env->sscratch);
+    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stvec ", env->stvec);
+    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);
+    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", (target_ulong)env->mstatus);
+    if (riscv_cpu_is_32bit(env)) {
+        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ",
+                     (target_ulong)(env->mstatus >> 32));
+    }
+    if (riscv_has_ext(env, RVH)) {
+        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus);
+        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ",
+                     (target_ulong)env->vsstatus);
+    }
+    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip     ", env->mip);
+    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie     ", env->mie);
+    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg);
+    if (riscv_has_ext(env, RVH)) {
+        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hideleg ", env->hideleg);
+    }
+    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg);
+    if (riscv_has_ext(env, RVH)) {
+        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hedeleg ", env->hedeleg);
+    }
+    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtvec   ", env->mtvec);
+    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stvec   ", env->stvec);
+    if (riscv_has_ext(env, RVH)) {
+        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vstvec  ", env->vstvec);
+    }
+    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mepc    ", env->mepc);
+    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sepc    ", env->sepc);
+    if (riscv_has_ext(env, RVH)) {
+        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsepc   ", env->vsepc);
+    }
+    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcause  ", env->mcause);
+    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "scause  ", env->scause);
+    if (riscv_has_ext(env, RVH)) {
+        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vscause ", env->vscause);
+    }
+    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval ", env->mtval);
+    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->sbadaddr);
+    if (riscv_has_ext(env, RVH)) {
+        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval);
+        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2);
+    }
+#endif
+
+    for (i = 0; i < 32; i++) {
+        qemu_fprintf(f, " %s " TARGET_FMT_lx,
+                     riscv_int_regnames[i], env->gpr[i]);
+        if ((i & 3) == 3) {
+            qemu_fprintf(f, "\n");
+        }
+    }
+    if (flags & CPU_DUMP_FPU) {
+        for (i = 0; i < 32; i++) {
+            qemu_fprintf(f, " %s %016" PRIx64,
+                         riscv_fpr_regnames[i], env->fpr[i]);
+            if ((i & 3) == 3) {
+                qemu_fprintf(f, "\n");
+            }
+        }
+    }
+}
+
+static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
+{
+    RISCVCPU *cpu = RISCV_CPU(cs);
+    CPURISCVState *env = &cpu->env;
+    env->pc = value;
+}
+
+static void riscv_cpu_synchronize_from_tb(CPUState *cs,
+                                          const TranslationBlock *tb)
+{
+    RISCVCPU *cpu = RISCV_CPU(cs);
+    CPURISCVState *env = &cpu->env;
+    env->pc = tb->pc;
+}
+
+static bool riscv_cpu_has_work(CPUState *cs)
+{
+#ifndef CONFIG_USER_ONLY
+    RISCVCPU *cpu = RISCV_CPU(cs);
+    CPURISCVState *env = &cpu->env;
+    /*
+     * Definition of the WFI instruction requires it to ignore the privilege
+     * mode and delegation registers, but respect individual enables
+     */
+    return (env->mip & env->mie) != 0;
+#else
+    return true;
+#endif
+}
+
+void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb,
+                          target_ulong *data)
+{
+    env->pc = data[0];
+}
+
+static void riscv_cpu_reset(DeviceState *dev)
+{
+    CPUState *cs = CPU(dev);
+    RISCVCPU *cpu = RISCV_CPU(cs);
+    RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
+    CPURISCVState *env = &cpu->env;
+
+    mcc->parent_reset(dev);
+#ifndef CONFIG_USER_ONLY
+    env->priv = PRV_M;
+    env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
+    env->mcause = 0;
+    env->pc = env->resetvec;
+    env->two_stage_lookup = false;
+#endif
+    cs->exception_index = EXCP_NONE;
+    env->load_res = -1;
+    set_default_nan_mode(1, &env->fp_status);
+}
+
+static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
+{
+    RISCVCPU *cpu = RISCV_CPU(s);
+    if (riscv_cpu_is_32bit(&cpu->env)) {
+        info->print_insn = print_insn_riscv32;
+    } else {
+        info->print_insn = print_insn_riscv64;
+    }
+}
+
+static void riscv_cpu_realize(DeviceState *dev, Error **errp)
+{
+    CPUState *cs = CPU(dev);
+    RISCVCPU *cpu = RISCV_CPU(dev);
+    CPURISCVState *env = &cpu->env;
+    RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
+    int priv_version = PRIV_VERSION_1_11_0;
+    int vext_version = VEXT_VERSION_0_07_1;
+    target_ulong target_misa = env->misa;
+    Error *local_err = NULL;
+
+    cpu_exec_realizefn(cs, &local_err);
+    if (local_err != NULL) {
+        error_propagate(errp, local_err);
+        return;
+    }
+
+    if (cpu->cfg.priv_spec) {
+        if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
+            priv_version = PRIV_VERSION_1_11_0;
+        } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
+            priv_version = PRIV_VERSION_1_10_0;
+        } else {
+            error_setg(errp,
+                       "Unsupported privilege spec version '%s'",
+                       cpu->cfg.priv_spec);
+            return;
+        }
+    }
+
+    set_priv_version(env, priv_version);
+    set_vext_version(env, vext_version);
+
+    if (cpu->cfg.mmu) {
+        set_feature(env, RISCV_FEATURE_MMU);
+    }
+
+    if (cpu->cfg.pmp) {
+        set_feature(env, RISCV_FEATURE_PMP);
+    }
+
+    set_resetvec(env, cpu->cfg.resetvec);
+
+    /* If only XLEN is set for misa, then set misa from properties */
+    if (env->misa == RV32 || env->misa == RV64) {
+        /* Do some ISA extension error checking */
+        if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
+            error_setg(errp,
+                       "I and E extensions are incompatible");
+                       return;
+       }
+
+        if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) {
+            error_setg(errp,
+                       "Either I or E extension must be set");
+                       return;
+       }
+
+       if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m &
+                               cpu->cfg.ext_a & cpu->cfg.ext_f &
+                               cpu->cfg.ext_d)) {
+            warn_report("Setting G will also set IMAFD");
+            cpu->cfg.ext_i = true;
+            cpu->cfg.ext_m = true;
+            cpu->cfg.ext_a = true;
+            cpu->cfg.ext_f = true;
+            cpu->cfg.ext_d = true;
+        }
+
+        /* Set the ISA extensions, checks should have happened above */
+        if (cpu->cfg.ext_i) {
+            target_misa |= RVI;
+        }
+        if (cpu->cfg.ext_e) {
+            target_misa |= RVE;
+        }
+        if (cpu->cfg.ext_m) {
+            target_misa |= RVM;
+        }
+        if (cpu->cfg.ext_a) {
+            target_misa |= RVA;
+        }
+        if (cpu->cfg.ext_f) {
+            target_misa |= RVF;
+        }
+        if (cpu->cfg.ext_d) {
+            target_misa |= RVD;
+        }
+        if (cpu->cfg.ext_c) {
+            target_misa |= RVC;
+        }
+        if (cpu->cfg.ext_s) {
+            target_misa |= RVS;
+        }
+        if (cpu->cfg.ext_u) {
+            target_misa |= RVU;
+        }
+        if (cpu->cfg.ext_h) {
+            target_misa |= RVH;
+        }
+        if (cpu->cfg.ext_v) {
+            target_misa |= RVV;
+            if (!is_power_of_2(cpu->cfg.vlen)) {
+                error_setg(errp,
+                        "Vector extension VLEN must be power of 2");
+                return;
+            }
+            if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) {
+                error_setg(errp,
+                        "Vector extension implementation only supports VLEN "
+                        "in the range [128, %d]", RV_VLEN_MAX);
+                return;
+            }
+            if (!is_power_of_2(cpu->cfg.elen)) {
+                error_setg(errp,
+                        "Vector extension ELEN must be power of 2");
+                return;
+            }
+            if (cpu->cfg.elen > 64 || cpu->cfg.vlen < 8) {
+                error_setg(errp,
+                        "Vector extension implementation only supports ELEN "
+                        "in the range [8, 64]");
+                return;
+            }
+            if (cpu->cfg.vext_spec) {
+                if (!g_strcmp0(cpu->cfg.vext_spec, "v0.7.1")) {
+                    vext_version = VEXT_VERSION_0_07_1;
+                } else {
+                    error_setg(errp,
+                           "Unsupported vector spec version '%s'",
+                           cpu->cfg.vext_spec);
+                    return;
+                }
+            } else {
+                qemu_log("vector version is not specified, "
+                        "use the default value v0.7.1\n");
+            }
+            set_vext_version(env, vext_version);
+        }
+
+        set_misa(env, target_misa);
+    }
+
+    riscv_cpu_register_gdb_regs_for_features(cs);
+
+    qemu_init_vcpu(cs);
+    cpu_reset(cs);
+
+    mcc->parent_realize(dev, errp);
+}
+
+static void riscv_cpu_init(Object *obj)
+{
+    RISCVCPU *cpu = RISCV_CPU(obj);
+
+    cpu_set_cpustate_pointers(cpu);
+}
+
+static Property riscv_cpu_properties[] = {
+    DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
+    DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
+    DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, true),
+    DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true),
+    DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true),
+    DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true),
+    DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true),
+    DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true),
+    DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
+    DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
+    /* This is experimental so mark with 'x-' */
+    DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
+    DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
+    DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
+    DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
+    DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
+    DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
+    DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
+    DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
+    DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
+    DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
+    DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
+    DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+static gchar *riscv_gdb_arch_name(CPUState *cs)
+{
+    RISCVCPU *cpu = RISCV_CPU(cs);
+    CPURISCVState *env = &cpu->env;
+
+    if (riscv_cpu_is_32bit(env)) {
+        return g_strdup("riscv:rv32");
+    } else {
+        return g_strdup("riscv:rv64");
+    }
+}
+
+static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
+{
+    RISCVCPU *cpu = RISCV_CPU(cs);
+
+    if (strcmp(xmlname, "riscv-csr.xml") == 0) {
+        return cpu->dyn_csr_xml;
+    }
+
+    return NULL;
+}
+
+#include "hw/core/tcg-cpu-ops.h"
+
+static struct TCGCPUOps riscv_tcg_ops = {
+    .initialize = riscv_translate_init,
+    .synchronize_from_tb = riscv_cpu_synchronize_from_tb,
+    .cpu_exec_interrupt = riscv_cpu_exec_interrupt,
+    .tlb_fill = riscv_cpu_tlb_fill,
+
+#ifndef CONFIG_USER_ONLY
+    .do_interrupt = riscv_cpu_do_interrupt,
+    .do_transaction_failed = riscv_cpu_do_transaction_failed,
+    .do_unaligned_access = riscv_cpu_do_unaligned_access,
+#endif /* !CONFIG_USER_ONLY */
+};
+
+static void riscv_cpu_class_init(ObjectClass *c, void *data)
+{
+    RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
+    CPUClass *cc = CPU_CLASS(c);
+    DeviceClass *dc = DEVICE_CLASS(c);
+
+    device_class_set_parent_realize(dc, riscv_cpu_realize,
+                                    &mcc->parent_realize);
+
+    device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset);
+
+    cc->class_by_name = riscv_cpu_class_by_name;
+    cc->has_work = riscv_cpu_has_work;
+    cc->dump_state = riscv_cpu_dump_state;
+    cc->set_pc = riscv_cpu_set_pc;
+    cc->gdb_read_register = riscv_cpu_gdb_read_register;
+    cc->gdb_write_register = riscv_cpu_gdb_write_register;
+    cc->gdb_num_core_regs = 33;
+#if defined(TARGET_RISCV32)
+    cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
+#elif defined(TARGET_RISCV64)
+    cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
+#endif
+    cc->gdb_stop_before_watchpoint = true;
+    cc->disas_set_info = riscv_cpu_disas_set_info;
+#ifndef CONFIG_USER_ONLY
+    cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
+    /* For now, mark unmigratable: */
+    cc->vmsd = &vmstate_riscv_cpu;
+    cc->write_elf64_note = riscv_cpu_write_elf64_note;
+    cc->write_elf32_note = riscv_cpu_write_elf32_note;
+#endif
+    cc->gdb_arch_name = riscv_gdb_arch_name;
+    cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;
+    cc->tcg_ops = &riscv_tcg_ops;
+
+    device_class_set_props(dc, riscv_cpu_properties);
+}
+
+char *riscv_isa_string(RISCVCPU *cpu)
+{
+    int i;
+    const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) + 1;
+    char *isa_str = g_new(char, maxlen);
+    char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS);
+    for (i = 0; i < sizeof(riscv_exts); i++) {
+        if (cpu->env.misa & RV(riscv_exts[i])) {
+            *p++ = qemu_tolower(riscv_exts[i]);
+        }
+    }
+    *p = '\0';
+    return isa_str;
+}
+
+static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b)
+{
+    ObjectClass *class_a = (ObjectClass *)a;
+    ObjectClass *class_b = (ObjectClass *)b;
+    const char *name_a, *name_b;
+
+    name_a = object_class_get_name(class_a);
+    name_b = object_class_get_name(class_b);
+    return strcmp(name_a, name_b);
+}
+
+static void riscv_cpu_list_entry(gpointer data, gpointer user_data)
+{
+    const char *typename = object_class_get_name(OBJECT_CLASS(data));
+    int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX);
+
+    qemu_printf("%.*s\n", len, typename);
+}
+
+void riscv_cpu_list(void)
+{
+    GSList *list;
+
+    list = object_class_get_list(TYPE_RISCV_CPU, false);
+    list = g_slist_sort(list, riscv_cpu_list_compare);
+    g_slist_foreach(list, riscv_cpu_list_entry, NULL);
+    g_slist_free(list);
+}
+
+#define DEFINE_CPU(type_name, initfn)      \
+    {                                      \
+        .name = type_name,                 \
+        .parent = TYPE_RISCV_CPU,          \
+        .instance_init = initfn            \
+    }
+
+static const TypeInfo riscv_cpu_type_infos[] = {
+    {
+        .name = TYPE_RISCV_CPU,
+        .parent = TYPE_CPU,
+        .instance_size = sizeof(RISCVCPU),
+        .instance_align = __alignof__(RISCVCPU),
+        .instance_init = riscv_cpu_init,
+        .abstract = true,
+        .class_size = sizeof(RISCVCPUClass),
+        .class_init = riscv_cpu_class_init,
+    },
+    DEFINE_CPU(TYPE_RISCV_CPU_ANY,              riscv_any_cpu_init),
+#if defined(TARGET_RISCV32)
+    DEFINE_CPU(TYPE_RISCV_CPU_BASE32,           rv32_base_cpu_init),
+    DEFINE_CPU(TYPE_RISCV_CPU_IBEX,             rv32_ibex_cpu_init),
+    DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31,       rv32_sifive_e_cpu_init),
+    DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34,       rv32_imafcu_nommu_cpu_init),
+    DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34,       rv32_sifive_u_cpu_init),
+#elif defined(TARGET_RISCV64)
+    DEFINE_CPU(TYPE_RISCV_CPU_BASE64,           rv64_base_cpu_init),
+    DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51,       rv64_sifive_e_cpu_init),
+    DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54,       rv64_sifive_u_cpu_init),
+#endif
+};
+
+DEFINE_TYPES(riscv_cpu_type_infos)

tests/linux-testgen/qemu-patches/virt.c

@@ -0,0 +1,451 @@
+/*
+ * QEMU RISC-V VirtIO Board
+ *
+ * Copyright (c) 2017 SiFive, Inc.
+ *
+ * RISC-V machine with 16550a UART and VirtIO MMIO
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/units.h"
+#include "qemu/log.h"
+#include "qemu/error-report.h"
+#include "qapi/error.h"
+#include "hw/boards.h"
+#include "hw/loader.h"
+#include "hw/sysbus.h"
+#include "hw/qdev-properties.h"
+#include "hw/char/serial.h"
+#include "target/riscv/cpu.h"
+#include "hw/riscv/riscv_hart.h"
+#include "hw/riscv/virt.h"
+#include "hw/riscv/boot.h"
+#include "hw/riscv/numa.h"
+#include "hw/intc/sifive_clint.h"
+#include "hw/intc/sifive_plic.h"
+#include "hw/misc/sifive_test.h"
+#include "chardev/char.h"
+#include "sysemu/arch_init.h"
+#include "sysemu/device_tree.h"
+#include "sysemu/sysemu.h"
+#include "hw/pci/pci.h"
+#include "hw/pci-host/gpex.h"
+#include "hw/display/ramfb.h"
+
+static const MemMapEntry virt_memmap[] = {
+    [VIRT_MROM] =        {     0x1000,        0xf000 },
+    [VIRT_CLINT] =       {  0x2000000,       0x10000 },
+    [VIRT_PLIC] =        {  0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
+    [VIRT_UART0] =       { 0x10000000,         0x100 },
+    [VIRT_DRAM] =        { 0x80000000,           0x0 },
+};
+
+/* PCIe high mmio is fixed for RV32 */
+#define VIRT32_HIGH_PCIE_MMIO_BASE  0x300000000ULL
+#define VIRT32_HIGH_PCIE_MMIO_SIZE  (4 * GiB)
+
+/* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */
+#define VIRT64_HIGH_PCIE_MMIO_SIZE  (16 * GiB)
+
+#define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
+
+static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
+                       uint64_t mem_size, const char *cmdline, bool is_32_bit)
+{
+    void *fdt;
+    //int i, cpu, socket;
+    int cpu, socket;
+    MachineState *mc = MACHINE(s);
+    uint64_t addr, size;
+    uint32_t *clint_cells, *plic_cells;
+    unsigned long clint_addr, plic_addr;
+    uint32_t plic_phandle[MAX_NODES];
+    uint32_t cpu_phandle, intc_phandle;
+    uint32_t phandle = 1, plic_mmio_phandle = 1;
+    char *mem_name, *cpu_name, *core_name, *intc_name;
+    char *name, *clint_name, *plic_name, *clust_name;
+
+    if (mc->dtb) {
+        fdt = mc->fdt = load_device_tree(mc->dtb, &s->fdt_size);
+        if (!fdt) {
+            error_report("load_device_tree() failed");
+            exit(1);
+        }
+        goto update_bootargs;
+    } else {
+        fdt = mc->fdt = create_device_tree(&s->fdt_size);
+        if (!fdt) {
+            error_report("create_device_tree() failed");
+            exit(1);
+        }
+    }
+
+    qemu_fdt_setprop_string(fdt, "/", "model", "riscv-virtio,qemu");
+    qemu_fdt_setprop_string(fdt, "/", "compatible", "riscv-virtio");
+    qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
+    qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
+
+    qemu_fdt_add_subnode(fdt, "/soc");
+    qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
+    qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
+    qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
+    qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
+
+    qemu_fdt_add_subnode(fdt, "/cpus");
+    qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
+                          SIFIVE_CLINT_TIMEBASE_FREQ);
+    qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
+    qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
+    qemu_fdt_add_subnode(fdt, "/cpus/cpu-map");
+
+    for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) {
+        clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket);
+        qemu_fdt_add_subnode(fdt, clust_name);
+
+        plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
+        clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
+
+        for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) {
+            cpu_phandle = phandle++;
+
+            cpu_name = g_strdup_printf("/cpus/cpu@%d",
+                s->soc[socket].hartid_base + cpu);
+            qemu_fdt_add_subnode(fdt, cpu_name);
+            if (is_32_bit) {
+                qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32");
+            } else {
+                qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48");
+            }
+            name = riscv_isa_string(&s->soc[socket].harts[cpu]);
+            qemu_fdt_setprop_string(fdt, cpu_name, "riscv,isa", name);
+            g_free(name);
+            qemu_fdt_setprop_string(fdt, cpu_name, "compatible", "riscv");
+            qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay");
+            qemu_fdt_setprop_cell(fdt, cpu_name, "reg",
+                s->soc[socket].hartid_base + cpu);
+            qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu");
+            riscv_socket_fdt_write_id(mc, fdt, cpu_name, socket);
+            qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle);
+
+            intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name);
+            qemu_fdt_add_subnode(fdt, intc_name);
+            intc_phandle = phandle++;
+            qemu_fdt_setprop_cell(fdt, intc_name, "phandle", intc_phandle);
+            qemu_fdt_setprop_string(fdt, intc_name, "compatible",
+                "riscv,cpu-intc");
+            qemu_fdt_setprop(fdt, intc_name, "interrupt-controller", NULL, 0);
+            qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1);
+
+            clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
+            clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
+            clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
+            clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
+
+            plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
+            plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
+            plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
+            plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
+
+            core_name = g_strdup_printf("%s/core%d", clust_name, cpu);
+            qemu_fdt_add_subnode(fdt, core_name);
+            qemu_fdt_setprop_cell(fdt, core_name, "cpu", cpu_phandle);
+
+            g_free(core_name);
+            g_free(intc_name);
+            g_free(cpu_name);
+        }
+
+        addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(mc, socket);
+        size = riscv_socket_mem_size(mc, socket);
+        mem_name = g_strdup_printf("/memory@%lx", (long)addr);
+        qemu_fdt_add_subnode(fdt, mem_name);
+        qemu_fdt_setprop_cells(fdt, mem_name, "reg",
+            addr >> 32, addr, size >> 32, size);
+        qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory");
+        riscv_socket_fdt_write_id(mc, fdt, mem_name, socket);
+        g_free(mem_name);
+
+        clint_addr = memmap[VIRT_CLINT].base +
+            (memmap[VIRT_CLINT].size * socket);
+        clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr);
+        qemu_fdt_add_subnode(fdt, clint_name);
+        qemu_fdt_setprop_string(fdt, clint_name, "compatible", "riscv,clint0");
+        qemu_fdt_setprop_cells(fdt, clint_name, "reg",
+            0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size);
+        qemu_fdt_setprop(fdt, clint_name, "interrupts-extended",
+            clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
+        riscv_socket_fdt_write_id(mc, fdt, clint_name, socket);
+        g_free(clint_name);
+
+        plic_phandle[socket] = phandle++;
+        plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket);
+        plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr);
+        qemu_fdt_add_subnode(fdt, plic_name);
+        qemu_fdt_setprop_cell(fdt, plic_name,
+            "#address-cells", FDT_PLIC_ADDR_CELLS);
+        qemu_fdt_setprop_cell(fdt, plic_name,
+            "#interrupt-cells", FDT_PLIC_INT_CELLS);
+        qemu_fdt_setprop_string(fdt, plic_name, "compatible", "riscv,plic0");
+        qemu_fdt_setprop(fdt, plic_name, "interrupt-controller", NULL, 0);
+        qemu_fdt_setprop(fdt, plic_name, "interrupts-extended",
+            plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
+        qemu_fdt_setprop_cells(fdt, plic_name, "reg",
+            0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size);
+        qemu_fdt_setprop_cell(fdt, plic_name, "riscv,ndev", VIRTIO_NDEV);
+        riscv_socket_fdt_write_id(mc, fdt, plic_name, socket);
+        qemu_fdt_setprop_cell(fdt, plic_name, "phandle", plic_phandle[socket]);
+        g_free(plic_name);
+
+        g_free(clint_cells);
+        g_free(plic_cells);
+        g_free(clust_name);
+    }
+
+    for (socket = 0; socket < riscv_socket_count(mc); socket++) {
+        if (socket == 0) {
+            plic_mmio_phandle = plic_phandle[socket];
+        }
+    }
+
+    riscv_socket_fdt_write_distance_matrix(mc, fdt);
+
+    name = g_strdup_printf("/soc/uart@%lx", (long)memmap[VIRT_UART0].base);
+    qemu_fdt_add_subnode(fdt, name);
+    qemu_fdt_setprop_string(fdt, name, "compatible", "ns16550a");
+    qemu_fdt_setprop_cells(fdt, name, "reg",
+        0x0, memmap[VIRT_UART0].base,
+        0x0, memmap[VIRT_UART0].size);
+    qemu_fdt_setprop_cell(fdt, name, "clock-frequency", 3686400);
+    qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", plic_mmio_phandle);
+    qemu_fdt_setprop_cell(fdt, name, "interrupts", UART0_IRQ);
+
+    qemu_fdt_add_subnode(fdt, "/chosen");
+    qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", name);
+    g_free(name);
+
+update_bootargs:
+    if (cmdline) {
+        qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
+    }
+}
+
+static void virt_machine_init(MachineState *machine)
+{
+    const MemMapEntry *memmap = virt_memmap;
+    RISCVVirtState *s = RISCV_VIRT_MACHINE(machine);
+    MemoryRegion *system_memory = get_system_memory();
+    MemoryRegion *main_mem = g_new(MemoryRegion, 1);
+    MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
+    char *plic_hart_config, *soc_name;
+    size_t plic_hart_config_len;
+    target_ulong start_addr = memmap[VIRT_DRAM].base;
+    target_ulong firmware_end_addr, kernel_start_addr;
+    uint32_t fdt_load_addr;
+    uint64_t kernel_entry;
+    DeviceState *mmio_plic;
+    int i, j, base_hartid, hart_count;
+
+    /* Check socket count limit */
+    if (VIRT_SOCKETS_MAX < riscv_socket_count(machine)) {
+        error_report("number of sockets/nodes should be less than %d",
+            VIRT_SOCKETS_MAX);
+        exit(1);
+    }
+
+    /* Initialize sockets */
+    mmio_plic = NULL;
+    for (i = 0; i < riscv_socket_count(machine); i++) {
+        if (!riscv_socket_check_hartids(machine, i)) {
+            error_report("discontinuous hartids in socket%d", i);
+            exit(1);
+        }
+
+        base_hartid = riscv_socket_first_hartid(machine, i);
+        if (base_hartid < 0) {
+            error_report("can't find hartid base for socket%d", i);
+            exit(1);
+        }
+
+        hart_count = riscv_socket_hart_count(machine, i);
+        if (hart_count < 0) {
+            error_report("can't find hart count for socket%d", i);
+            exit(1);
+        }
+
+        soc_name = g_strdup_printf("soc%d", i);
+        object_initialize_child(OBJECT(machine), soc_name, &s->soc[i],
+                                TYPE_RISCV_HART_ARRAY);
+        g_free(soc_name);
+        object_property_set_str(OBJECT(&s->soc[i]), "cpu-type",
+                                machine->cpu_type, &error_abort);
+        object_property_set_int(OBJECT(&s->soc[i]), "hartid-base",
+                                base_hartid, &error_abort);
+        object_property_set_int(OBJECT(&s->soc[i]), "num-harts",
+                                hart_count, &error_abort);
+        sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort);
+
+        /* Per-socket CLINT */
+        sifive_clint_create(
+            memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size,
+            memmap[VIRT_CLINT].size, base_hartid, hart_count,
+            SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
+            SIFIVE_CLINT_TIMEBASE_FREQ, true);
+
+        /* Per-socket PLIC hart topology configuration string */
+        plic_hart_config_len =
+            (strlen(VIRT_PLIC_HART_CONFIG) + 1) * hart_count;
+        plic_hart_config = g_malloc0(plic_hart_config_len);
+        for (j = 0; j < hart_count; j++) {
+            if (j != 0) {
+                strncat(plic_hart_config, ",", plic_hart_config_len);
+            }
+            strncat(plic_hart_config, VIRT_PLIC_HART_CONFIG,
+                plic_hart_config_len);
+            plic_hart_config_len -= (strlen(VIRT_PLIC_HART_CONFIG) + 1);
+        }
+
+        /* Per-socket PLIC */
+        s->plic[i] = sifive_plic_create(
+            memmap[VIRT_PLIC].base + i * memmap[VIRT_PLIC].size,
+            plic_hart_config, base_hartid,
+            VIRT_PLIC_NUM_SOURCES,
+            VIRT_PLIC_NUM_PRIORITIES,
+            VIRT_PLIC_PRIORITY_BASE,
+            VIRT_PLIC_PENDING_BASE,
+            VIRT_PLIC_ENABLE_BASE,
+            VIRT_PLIC_ENABLE_STRIDE,
+            VIRT_PLIC_CONTEXT_BASE,
+            VIRT_PLIC_CONTEXT_STRIDE,
+            memmap[VIRT_PLIC].size);
+        g_free(plic_hart_config);
+
+        /* Try to use different PLIC instance based device type */
+        if (i == 0) {
+            mmio_plic = s->plic[i];
+        }
+    }
+
+    if (riscv_is_32bit(&s->soc[0])) {
+#if HOST_LONG_BITS == 64
+        /* limit RAM size in a 32-bit system */
+        if (machine->ram_size > 10 * GiB) {
+            machine->ram_size = 10 * GiB;
+            error_report("Limiting RAM size to 10 GiB");
+        }
+#endif
+    }
+
+    /* register system main memory (actual RAM) */
+    memory_region_init_ram(main_mem, NULL, "riscv_virt_board.ram",
+                           machine->ram_size, &error_fatal);
+    memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base,
+        main_mem);
+
+    /* create device tree */
+    create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
+               riscv_is_32bit(&s->soc[0]));
+
+    /* boot rom */
+    memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom",
+                           memmap[VIRT_MROM].size, &error_fatal);
+    memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base,
+                                mask_rom);
+
+    if (riscv_is_32bit(&s->soc[0])) {
+        firmware_end_addr = riscv_find_and_load_firmware(machine,
+                                    "opensbi-riscv32-generic-fw_dynamic.bin",
+                                    start_addr, NULL);
+    } else {
+        firmware_end_addr = riscv_find_and_load_firmware(machine,
+                                    "opensbi-riscv64-generic-fw_dynamic.bin",
+                                    start_addr, NULL);
+    }
+
+    if (machine->kernel_filename) {
+        kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
+                                                         firmware_end_addr);
+
+        kernel_entry = riscv_load_kernel(machine->kernel_filename,
+                                         kernel_start_addr, NULL);
+
+        if (machine->initrd_filename) {
+            hwaddr start;
+            hwaddr end = riscv_load_initrd(machine->initrd_filename,
+                                           machine->ram_size, kernel_entry,
+                                           &start);
+            qemu_fdt_setprop_cell(machine->fdt, "/chosen",
+                                  "linux,initrd-start", start);
+            qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end",
+                                  end);
+        }
+    } else {
+       /*
+        * If dynamic firmware is used, it doesn't know where is the next mode
+        * if kernel argument is not set.
+        */
+        kernel_entry = 0;
+    }
+
+    /* Compute the fdt load address in dram */
+    fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
+                                   machine->ram_size, machine->fdt);
+    /* load the reset vector */
+    riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr,
+                              virt_memmap[VIRT_MROM].base,
+                              virt_memmap[VIRT_MROM].size, kernel_entry,
+                              fdt_load_addr, machine->fdt);
+
+   serial_mm_init(system_memory, memmap[VIRT_UART0].base,
+        0, qdev_get_gpio_in(DEVICE(mmio_plic), UART0_IRQ), 399193,
+        serial_hd(0), DEVICE_LITTLE_ENDIAN);
+
+}
+
+static void virt_machine_instance_init(Object *obj)
+{
+}
+
+static void virt_machine_class_init(ObjectClass *oc, void *data)
+{
+    MachineClass *mc = MACHINE_CLASS(oc);
+
+    mc->desc = "RISC-V VirtIO board";
+    mc->init = virt_machine_init;
+    mc->max_cpus = VIRT_CPUS_MAX;
+    mc->default_cpu_type = TYPE_RISCV_CPU_BASE;
+    mc->pci_allow_0_address = true;
+    mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids;
+    mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
+    mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
+    mc->numa_mem_supported = true;
+
+    machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
+}
+
+static const TypeInfo virt_machine_typeinfo = {
+    .name       = MACHINE_TYPE_NAME("virt"),
+    .parent     = TYPE_MACHINE,
+    .class_init = virt_machine_class_init,
+    .instance_init = virt_machine_instance_init,
+    .instance_size = sizeof(RISCVVirtState),
+};
+
+static void virt_machine_init_register_types(void)
+{
+    type_register_static(&virt_machine_typeinfo);
+}
+
+type_init(virt_machine_init_register_types)
+