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simpleram simplification

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This commit is contained in:
David Harris 2022-01-25 18:26:31 +00:00
parent e3136c9a1e
commit a86a9f5c2a
3 changed files with 16 additions and 30 deletions
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32
pipelined/src/generic/flop/simpleram.sv
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@ -32,48 +32,36 @@
module simpleram #(parameter BASE=0, RANGE = 65535) (
input logic clk,
input logic HSELRam,
input logic [31:0] Adr,
input logic HWRITE,
input logic HREADY,
input logic [1:0] HTRANS,
input logic [`XLEN-1:0] HWDATA,
output logic [`XLEN-1:0] HREADRam,
output logic HRESPRam, HREADYRam
input logic [31:0] a,
input logic we,
input logic [`XLEN-1:0] wd,
output logic [`XLEN-1:0] rd
);
localparam MemStartAddr = BASE>>(1+`XLEN/32);
localparam MemEndAddr = (RANGE+BASE)>>1+(`XLEN/32);
logic [`XLEN-1:0] RAM[BASE>>(1+`XLEN/32):(RANGE+BASE)>>1+(`XLEN/32)];
logic [31:0] AD;
logic [`XLEN-1:0] HREADRam0;
logic [31:0] ad;
logic prevHREADYRam, risingHREADYRam;
logic initTrans;
logic memwrite;
logic [3:0] busycount;
assign initTrans = HREADY & HSELRam & (HTRANS != 2'b00);
flop #(32) Adrreg(clk, Adr, AD);
flop #(32) areg(clk, a, ad);
/* verilator lint_off WIDTH */
if (`XLEN == 64) begin:ramrw
always_ff @(posedge clk) begin
if (HWRITE & |HTRANS) RAM[AD[31:3]] <= #1 HWDATA;
if (we) RAM[ad[31:3]] <= #1 wd;
end
end else begin
always_ff @(posedge clk) begin:ramrw
if (HWRITE & |HTRANS) RAM[AD[31:2]] <= #1 HWDATA;
if (we) RAM[ad[31:2]] <= #1 wd;
end
end
// read
if(`XLEN == 64) begin: ramr
assign HREADRam = RAM[AD[31:3]];
assign rd = RAM[ad[31:3]];
end else begin
assign HREADRam = RAM[AD[31:2]];
assign rd = RAM[ad[31:2]];
end
/* verilator lint_on WIDTH */

7
pipelined/src/ifu/ifu.sv
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@ -236,10 +236,9 @@ module ifu (
simpleram #(
.BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram (
.clk,
.HSELRam(1'b1), .Adr(CPUBusy ? PCPF[31:0] : PCNextFMux[31:0]), // mux is also inside $, have to replay address if CPU is stalled.
.HWRITE(1'b0), .HREADY(1'b1),
.HTRANS(2'b10), .HWDATA(0), .HREADRam(FinalInstrRawF_FIXME),
.HRESPRam(), .HREADYRam());
.a(CPUBusy ? PCPF[31:0] : PCNextFMux[31:0]), // mux is also inside $, have to replay address if CPU is stalled.
.we(1'b0),
.wd(0), .rd(FinalInstrRawF_FIXME));
assign FinalInstrRawF = FinalInstrRawF_FIXME[31:0];
assign BusStall = 0;
assign IFUBusRead = 0;

7
pipelined/src/lsu/lsu.sv
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@ -247,10 +247,9 @@ module lsu (
if (`MEM_DTIM) begin : dtim
simpleram #(.BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram (
.clk,
.HSELRam(1'b1), .Adr(CPUBusy ? IEUAdrM[31:0] : IEUAdrE[31:0]),
.HWRITE(LSURWM[0]), .HREADY(1'b1),
.HTRANS(|LSURWM ? 2'b10 : 2'b00), .HWDATA(FinalWriteDataM), .HREADRam(ReadDataWordM),
.HRESPRam(), .HREADYRam());
.a(CPUBusy ? IEUAdrM[31:0] : IEUAdrE[31:0]),
.we(LSURWM[0]),
.wd(FinalWriteDataM), .rd(ReadDataWordM));
// since we have a local memory the bus connections are all disabled.
// There are no peripherals supported.