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simpleram simplification

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This commit is contained in:
David Harris 2022-01-25 19:40:07 +00:00
parent a86a9f5c2a
commit 9da1ed4ed9
1 changed files with 3 additions and 12 deletions
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15
pipelined/src/generic/flop/simpleram.sv
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@ -38,32 +38,23 @@ module simpleram #(parameter BASE=0, RANGE = 65535) (
output logic [`XLEN-1:0] rd
);
localparam MemStartAddr = BASE>>(1+`XLEN/32);
localparam MemEndAddr = (RANGE+BASE)>>1+(`XLEN/32);
logic [`XLEN-1:0] RAM[BASE>>(1+`XLEN/32):(RANGE+BASE)>>1+(`XLEN/32)];
logic [31:0] ad;
flop #(32) areg(clk, a, ad);
flop #(32) areg(clk, a, ad); // *** redesign external interface so this delay isn't needed
/* verilator lint_off WIDTH */
if (`XLEN == 64) begin:ramrw
always_ff @(posedge clk) begin
rd <= RAM[a[31:3]];
if (we) RAM[ad[31:3]] <= #1 wd;
end
end else begin
always_ff @(posedge clk) begin:ramrw
rd <= RAM[a[31:2]];
if (we) RAM[ad[31:2]] <= #1 wd;
end
end
// read
if(`XLEN == 64) begin: ramr
assign rd = RAM[ad[31:3]];
end else begin
assign rd = RAM[ad[31:2]];
end
/* verilator lint_on WIDTH */
endmodule