cvw/pipelined/src
2022-02-14 12:40:51 -06:00
..
cache Cache mods to be consistant with diagrams. 2022-02-14 12:40:51 -06:00
ebu Cleaned up synthesis warnings 2022-02-11 01:15:16 +00:00
fpu Replaced || and && with | and & 2022-01-31 01:07:35 +00:00
generic RAM simplification 2022-02-08 20:15:23 +00:00
hazard Renamed LSUStall to LSUStallM 2022-01-15 00:24:16 +00:00
ieu Synthesis script cleanup, eliminated privileged instructiosn from controller when ZICSR_SUPPORTED = 0 2022-02-12 05:50:34 +00:00
ifu Changed names of signals in cache. 2022-02-13 15:06:18 -06:00
lsu Changed names of signals in cache. 2022-02-13 15:06:18 -06:00
mmu Cleaned up synthesis warnings 2022-02-11 01:15:16 +00:00
muldiv Better solution to the integer divider interrupt interaction. 2022-01-12 14:22:18 -06:00
privileged More config file cleanup; 32ic tests broken 2022-02-03 01:08:34 +00:00
uncore Cleaned up synthesis warnings 2022-02-11 01:15:16 +00:00
wally Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault. 2022-01-27 17:11:27 -06:00
sdc piplined directory cleanup 2022-01-07 12:43:50 +00:00