1357 Commits

Author	SHA1	Message	Date
David Harris	e4724b8d0e	Crypto formatting cleanup	2024-03-10 20:45:27 -07:00
David Harris	34058ddbf0	Crypto formatting cleanup	2024-03-10 20:36:29 -07:00
David Harris	39ca7093bf	Merged AES changes	2024-03-10 19:17:01 -07:00
Rose Thompson	3cf6a19729	Merge branch 'main' into main	2024-03-10 10:48:21 -05:00
James E. Stine	047291ef49	add header for bmuctrl.sv	2024-03-09 22:09:31 -06:00
James E. Stine	54fec7c31f	fix bitmanipalu.sv typo on missing semicolon	2024-03-09 22:07:40 -06:00
James E. Stine	1573c890d0	Update bitmanipalu.sv for K extension	2024-03-09 22:01:20 -06:00
James E. Stine	ac3aa823e7	fix underscore in bmu directory	2024-03-09 20:19:46 -06:00
James E. Stine	1aa1608a18	fix space in kmu	2024-03-09 19:41:29 -06:00
James E. Stine	ad12def935	fix underscore in instantiation	2024-03-09 19:38:10 -06:00
James E. Stine	bd5741b4f1	fix space at beginning of file in bmu	2024-03-09 19:10:43 -06:00
James E. Stine	55e019c9dd	update removal of underscores from kmu	2024-03-09 19:00:31 -06:00
James E. Stine	3b16238a37	update removal of underscores from sha_instructions	2024-03-09 18:51:01 -06:00
James E. Stine	08c7ddd61d	update removal of underscores from aes_instructions	2024-03-09 13:28:47 -06:00
James E. Stine	8821386fe5	update removal of underscores from aes_common	2024-03-09 13:06:36 -06:00
Rose Thompson	29db2cd931	Basic hardware tracer works! ... Next step is to package the buses into packets to ethernet transmission.	2024-03-08 12:38:27 -06:00
Rose Thompson	140e64772e	Merge branch 'main' into rvvi	2024-03-08 10:16:31 -06:00
David Harris	eb87a4a5c3	UM comments in fdivsqrtotfc	2024-03-06 15:53:14 -08:00
David Harris	2c6588d4ae	Timinig optimization for radix 4 division, added missing derived config	2024-03-06 15:05:04 -08:00
David Harris	c7c12cc3a8	Fixed Lint issue on cacheLRU	2024-03-06 14:00:57 -08:00
Rose Thompson	54c1d28c8b	Fixed missing case in the align AccesByteOffset Mux.	2024-03-06 15:43:55 -06:00
Rose Thompson	0d8c251fa4	Merge branch 'main' of https://github.com/openhwgroup/cvw	2024-03-06 15:35:34 -06:00
Rose Thompson	2f94be5e79	Revert "Optimized the align logic for loads." ... This reverts commit 1fd678b433.	2024-03-06 15:19:17 -06:00
Rose Thompson	57aab52dc2	Revert "Partially working optimized subwordwrite for misaligned." ... This reverts commit dac8fc16af.	2024-03-06 15:17:57 -06:00
Rose Thompson	9668fdd868	Revert "Closer to getting subword write misaligned working." ... This reverts commit 6a9c2d8dc4.	2024-03-06 15:16:43 -06:00
Rose Thompson	dce7de59a3	Revert "Non-ideal fix. Added new output from pma which indicates if the write shift should occur." ... This reverts commit 3714b2bf4a.	2024-03-06 15:16:37 -06:00
Rose Thompson	a48c16c0ef	Revert "Swapped to the more compact subwordreadmisaligned.sv." ... This reverts commit 1ece6f8eae.	2024-03-06 15:16:32 -06:00
Rose Thompson	f752b5dd37	Revert "Beginning subword cleanup." ... This reverts commit 7e1ea1e6d9.	2024-03-06 15:16:24 -06:00
Rose Thompson	a8024eee26	Revert "Updated subword misaligned." ... This reverts commit 69d31d50e2.	2024-03-06 15:16:16 -06:00
Rose Thompson	298028b119	Revert "Cleanup." ... This reverts commit 45c30267a5.	2024-03-06 15:16:03 -06:00
Rose Thompson	739e73ef81	Revert "Siginficant cleanup of subwordwritemisaligned." ... This reverts commit fbc18abaa0.	2024-03-06 15:15:58 -06:00
Rose Thompson	e7ec2bedd4	Revert "Simplifications of subword code." ... This reverts commit a402883115.	2024-03-06 15:15:51 -06:00
Rose Thompson	b64b883129	Revert "Removed duplicate endianswap." ... This reverts commit caac48b7f2.	2024-03-06 15:15:43 -06:00
Rose Thompson	5447159cfd	Revert "Cleanup." ... This reverts commit e84b7cc147.	2024-03-06 15:15:26 -06:00
Rose Thompson	3fa5faa6cf	Revert "Added sdc to pma allow shift." ... This reverts commit a2d5618d88.	2024-03-06 13:29:08 -06:00
Rose Thompson	2ea0134329	Revert "Trying an experiment. Use the less compact subwordreaddouble in the fpga synthesize rather than subwordreadmisaligned." ... This reverts commit cba3209e7f.	2024-03-06 13:28:59 -06:00
Rose Thompson	068ffda5fb	Revert "Revert "Trying an experiment. Use the less compact subwordreaddouble in the fpga synthesize rather than subwordreadmisaligned."" ... This reverts commit 8136b45ca7.	2024-03-06 13:28:47 -06:00
David Harris	e0eb91f795	Changed always @(posedge clk) to always_ff @(posedge clk) where it was omitted in several places	2024-03-06 11:02:04 -08:00
David Harris	b386331cc8	Changed '0 to 0 where possible per Chapter 4 style guidelines	2024-03-06 05:48:17 -08:00
David Harris	dd33479056	Switched to ?: for gating per section 4.2.4.3	2024-03-06 04:59:58 -08:00
David Harris	86956026dc	Further simplified subwordread muxing	2024-03-06 04:24:31 -08:00
Kevin Kim	9d73e5bd0d	lsu supports quad enabled subwordreads	2024-03-05 17:07:39 -08:00
KelvinTr	00b61390d9	Optimized Inverse Mixcolumn	2024-03-05 14:56:24 -06:00
Rose Thompson	c093f53c9c	Merge branch 'main' of https://github.com/openhwgroup/cvw ... Cleaned up the cacheLRU.	2024-03-05 11:08:40 -06:00
Rose Thompson	e8e0538f6c	Changed to non-blocking in cacheLRU and removed clearing LRU bits on flush.	2024-03-05 10:33:47 -06:00
James E. Stine	5b445946b1	style file slight mods for sha_instructions	2024-03-05 09:14:22 -06:00
James E. Stine	6894ee4588	Separate gm2.sv to be separate module	2024-03-05 09:10:41 -06:00
James E. Stine	5aab40a35f	Missed some style module declarations	2024-03-05 09:06:48 -06:00
James E. Stine	5e247b9bf3	fix some spacing in aes_common	2024-03-05 09:02:22 -06:00
James E. Stine	7bbc6413fb	fix spacing in sha_instructions for style	2024-03-05 08:59:45 -06:00
James E. Stine	0d7ea36883	fix module name to lc in aes_instructions	2024-03-05 08:56:24 -06:00
James E. Stine	e6ffde61bd	fix module name to lc	2024-03-05 08:54:50 -06:00
David Harris	1a0097f6e7	Further fdivsqrt simplification after starting Sqrt at iteration 0	2024-03-04 16:40:49 -08:00
David Harris	9c04df8f69	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2024-03-04 16:04:24 -08:00
Rose Thompson	457d3481e7	How did this error get past for so long.	2024-03-04 17:58:41 -06:00
Rose Thompson	0222e8f42a	Don't want to clear the lru bits on invalidation (clearvalid).	2024-03-04 17:52:41 -06:00
Kevin Kim	10ab07975f	uslc comments	2024-03-04 14:31:21 -08:00
Kevin Kim	9b87a00698	sqrt mux lint fixes	2024-03-04 14:31:07 -08:00
Kevin Kim	587fdbdf8e	removed j1,j0 from iteration and put inside divider stage	2024-03-04 14:30:05 -08:00
KelvinTr	c163069484	Optimized mixcolumn	2024-03-04 15:23:11 -06:00
Kevin Kim	7dec9cdf21	optimization in uslc	2024-03-04 10:46:16 -08:00
Kevin Kim	9c95cba865	remove sqrt cycle muxing	2024-03-03 18:51:10 -08:00
Kevin Kim	0ff59ff157	remove redundant mux	2024-03-03 13:00:20 -08:00
Kevin Kim	c32173f163	changed U/C initialization to account for integer bit generation on divider stage for sqrt. Quick and dirty j1 logic fix	2024-03-03 10:30:18 -08:00
Kevin Kim	6c24afaf98	changed cycle count to account for integer bit generation for sqrt	2024-03-03 10:29:32 -08:00
Kevin Kim	c45d67f8ba	fdivsqrt changes	2024-03-02 20:29:03 -08:00
Kevin Kim	77ccc7b319	removed square root pre-process muxes	2024-03-02 15:55:34 -08:00
Rose Thompson	a22de45631	Removed unused storedelay from align.	2024-03-02 16:20:31 -06:00
Rose Thompson	8136b45ca7	Revert "Trying an experiment. Use the less compact subwordreaddouble in the fpga synthesize rather than subwordreadmisaligned." ... This reverts commit cba3209e7f.	2024-03-02 11:55:43 -06:00
Rose Thompson	cba3209e7f	Trying an experiment. Use the less compact subwordreaddouble in the fpga synthesize rather than subwordreadmisaligned.	2024-03-02 11:38:33 -06:00
Rose Thompson	4c3d927474	Renamed CacheHit to Hit.	2024-03-01 11:00:24 -06:00
Rose Thompson	e72880fd89	Changed cachefsm state STATE_HIT to STATE_ACCESS.	2024-03-01 09:59:54 -06:00
Rose Thompson	85691f0e8b	Simplified and clarified names in cacheLRU.	2024-02-29 17:18:01 -06:00
KelvinTr	c110d0bb03	Optimized Zbkx	2024-02-29 14:51:02 -06:00
KelvinTr	9f53c54f57	Optimized Zbkx	2024-02-29 14:50:15 -06:00
KelvinTr	e40ae126d3	Combined ZBC and ZBKC into one unit	2024-02-29 14:17:33 -06:00
KelvinTr	88d93b31b5	Combined byteop and revop logic	2024-02-29 12:51:42 -06:00
Rose Thompson	90ad5e7dab	Updated the cache for book clarity.	2024-02-28 17:07:32 -06:00
KelvinTr	01c45ab9d7	Fixed K extension changes	2024-02-28 17:05:08 -06:00
David Harris	90e89ced1d	Fixes for synthesis. HPTW change will break x detection	2024-02-26 04:20:08 -08:00
James E. Stine	eb1780a66d	control for bitmanip	2024-02-24 22:38:21 -06:00
James E. Stine	ce975a6336	Add ieu main module for k extension	2024-02-24 22:37:04 -06:00
James E. Stine	71cefdbbb2	main cvw module	2024-02-24 22:35:56 -06:00
James E. Stine	cd2a9b8712	Add mux7 for K ext	2024-02-24 22:26:21 -06:00
James E. Stine	50cbe54d7b	Add datapath.sv	2024-02-24 22:22:19 -06:00
James E. Stine	e06bafe972	Add alu + controller	2024-02-24 22:21:39 -06:00
Rose Thompson	ab750e150f	Fixed lint errors for alignment.	2024-02-23 14:00:19 -06:00
Rose Thompson	a2d5618d88	Added sdc to pma allow shift.	2024-02-23 13:46:04 -06:00
Rose Thompson	e84b7cc147	Cleanup.	2024-02-23 13:00:21 -06:00
Rose Thompson	ae36f1e5a5	Merge branch 'main' of github.com:ross144/cvw	2024-02-23 09:43:03 -06:00
Rose Thompson	caac48b7f2	Removed duplicate endianswap.	2024-02-23 09:42:39 -06:00
Rose Thompson	a402883115	Simplifications of subword code.	2024-02-23 09:41:59 -06:00
Rose Thompson	fbc18abaa0	Siginficant cleanup of subwordwritemisaligned.	2024-02-22 14:17:15 -06:00
Rose Thompson	45c30267a5	Cleanup.	2024-02-22 14:08:04 -06:00
Rose Thompson	69d31d50e2	Updated subword misaligned.	2024-02-22 13:29:39 -06:00
James E. Stine	cdd2aa6379	tweak of names	2024-02-22 12:27:40 -06:00
James E. Stine	c8468e99c0	slight tweak of names	2024-02-22 12:27:09 -06:00
James E. Stine	550f50debb	Modify ALU to handle Zkne/K extension	2024-02-22 11:55:00 -06:00
Rose Thompson	7e1ea1e6d9	Beginning subword cleanup.	2024-02-22 09:37:16 -06:00
Rose Thompson	1ece6f8eae	Swapped to the more compact subwordreadmisaligned.sv.	2024-02-22 09:34:16 -06:00
Rose Thompson	3714b2bf4a	Non-ideal fix. Added new output from pma which indicates if the write shift should occur. ... The more ideal solution would be to have the pma indicate if the shift should occur and the maximum amount..	2024-02-22 09:14:43 -06:00
James E. Stine	7cb170c19b	update on aes_instructions	2024-02-21 17:12:50 -06:00
James E. Stine	7097b17785	update aes_instructions	2024-02-21 17:11:34 -06:00
James E. Stine	ac9068d22c	update aes_common with style on separate sv	2024-02-21 17:05:58 -06:00
James E. Stine	3d65ea7aba	separate aes_shiftword per style file	2024-02-20 22:57:59 -06:00
James E. Stine	f700b7da5a	separate galois function SV per the style file	2024-02-20 22:55:34 -06:00
Rose Thompson	6a9c2d8dc4	Closer to getting subword write misaligned working.	2024-02-20 20:23:42 -06:00
James E. Stine	32be22565a	add kmu instruction	2024-02-20 20:18:50 -06:00
James E. Stine	38348f9784	Add SHA instructions	2024-02-20 20:01:12 -06:00
James E. Stine	2cf1d43ec5	add aes instructions	2024-02-20 19:39:26 -06:00
James E. Stine	93d9bb4bc4	minor changes + date change on copyright	2024-02-20 19:13:11 -06:00
James E. Stine	488583aed9	minor tweak	2024-02-20 18:42:34 -06:00
James E. Stine	0cc0cdeae2	initial seed of AES engine	2024-02-20 18:31:17 -06:00
David Harris	c77afcb7e6	Removed floprc with synchronous reset and synchornous clear	2024-02-19 22:28:55 -08:00
Rose Thompson	dac8fc16af	Partially working optimized subwordwrite for misaligned.	2024-02-19 12:26:29 -06:00
David Harris	9ba35991e3	Finished FPU coverage	2024-02-15 20:01:28 -08:00
David Harris	36259b4e16	Removed unused term affecting cvt coverage	2024-02-15 17:46:05 -08:00
David Harris	944e33dcd6	Fixed spelling of operation in FPU	2024-02-15 17:22:32 -08:00
David Harris	c664c9717d	Commented fcvtmod behavior in specialcase	2024-02-15 17:19:21 -08:00
Rose Thompson	1fd678b433	Optimized the align logic for loads.	2024-02-14 12:14:19 -06:00
David Harris	6f53adad80	ifu cachefsm coverage	2024-02-08 13:15:06 -08:00
Kevin Kim	15da037794	added back comment	2024-02-07 15:40:52 -08:00
Kevin Kim	61c8b4d269	shift correction fix	2024-02-07 15:04:19 -08:00
David Harris	e7364290e3	Restored instead of in testbench because prevents coverage analysis. Improved FPU coverage	2024-02-07 06:27:53 -08:00
David Harris	c41e1c3a1c	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2024-02-04 19:02:49 -08:00
David Harris	66c1c71a56	Coverage improvements	2024-02-04 18:56:40 -08:00
Rose Thompson	7a4d485f5b	Merge branch 'main' of https://github.com/openhwgroup/cvw	2024-02-04 14:19:50 -06:00
David Harris	5d8d82414b	Coverage improvements	2024-02-04 11:40:38 -08:00
harshinisrinath	c7b647bde7	Wrote exclusions for ifu and lsu peripherals which were always supported	2024-02-01 17:12:33 -08:00
Rose Thompson	bd06a5ff88	Rough draft removal of duplicate BPBTAWrongE logic.	2024-02-01 16:57:33 -06:00
Rose Thompson	e900bb09db	Merge branch 'main' of https://github.com/openhwgroup/cvw	2024-02-01 12:12:05 -06:00
Rose Thompson	87d91c5b14	Coverage updates.	2024-02-01 12:12:01 -06:00
David Harris	1c62c5e433	Fixed logic to work with FLEN < XLEN	2024-01-31 20:24:16 -08:00
Rose Thompson	ccf61853cf	New coverage for ebu.	2024-01-31 14:55:25 -06:00
David Harris	0abfe5cb55	Fixed some lint errors in derived configs	2024-01-31 11:39:59 -08:00
Rose Thompson	aa15a63d9c	Merge branch 'main' of https://github.com/openhwgroup/cvw	2024-01-31 13:12:32 -06:00
David Harris	91e21f5a85	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2024-01-30 08:53:18 -08:00
David Harris	06778088ab	Merge pull request #603 from stineje/main ... Update cvt bug that was caught with new testbench-fp	2024-01-30 08:52:01 -08:00
James E. Stine	7e036e6f75	Update cvt bug that was caught with new testbench-fp	2024-01-30 10:51:07 -06:00
David Harris	f37c7bb1f6	Incorporated RAM_LATENCY and BURST_EN as parameters rather than define in code. Still need to update testbench to use this	2024-01-30 06:27:18 -08:00
David Harris	3db5b6d9a9	Fix FLI to support quads	2024-01-29 14:51:21 -08:00
Rose Thompson	e3574238a7	Merge branch 'main' of https://github.com/openhwgroup/cvw	2024-01-29 13:18:16 -06:00
David Harris	45e2317636	Added Wally github address to header comments	2024-01-29 05:38:11 -08:00
David Harris	e8dde265be	More coverage: CacheWay	2024-01-26 16:14:36 -08:00
David Harris	3620a10c0b	Improved hptw and I CacheWays coverage	2024-01-26 14:55:51 -08:00
Rose Thompson	cbc44a68ab	Merge branch 'main' of https://github.com/openhwgroup/cvw	2024-01-26 12:50:36 -06:00
David Harris	1c1d3eb956	HPTW coverage improvements	2024-01-26 10:46:38 -08:00
Rose Thompson	c0e04dd622	Merge branch 'main' of https://github.com/openhwgroup/cvw	2024-01-26 10:09:44 -06:00
David Harris	2449e06e55	Fixed FPU coverage, solved Issue 596 by misaligned AMO throwing access fault when misaligned non-amo are supported	2024-01-25 21:03:41 -08:00
Rose Thompson	fd032a7e10	Draft implementation of synth rvvi.	2024-01-24 15:06:13 -06:00