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https://github.com/openhwgroup/cvw
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Draft implementation of synth rvvi.
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Rose Thompson
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77
src/wally/csrindextoaddr.sv
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77
src/wally/csrindextoaddr.sv
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///////////////////////////////////////////
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// csrindextoaddr.sv
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//
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// Written: Rose Thompson ross1728@gmail.com
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// Created: 24 January 2024
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// Modified: 24 January 2024
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//
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// Purpose: Converts the rvvi CSR index into the CSR address
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//
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// Documentation:
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module csrindextoaddr #(parameter NUM_CSRS = 36) (
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input logic [ROWS-1:0] CSRWen,
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output logic [11:0] CSRAddr);
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always_comb begin
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case(CSRWen) begin
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36'h0_0000_0000: CSRAddr = 13'h000;
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36'h0_0000_0001: CSRAddr = 13'h300;
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36'h0_0000_0002: CSRAddr = 13'h310;
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36'h0_0000_0004: CSRAddr = 13'h305;
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36'h0_0000_0008: CSRAddr = 13'h341;
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36'h0_0000_0010: CSRAddr = 13'h306;
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36'h0_0000_0020: CSRAddr = 13'h320;
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36'h0_0000_0040: CSRAddr = 13'h302;
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36'h0_0000_0080: CSRAddr = 13'h303;
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36'h0_0000_0100: CSRAddr = 13'h344;
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36'h0_0000_0200: CSRAddr = 13'h304;
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36'h0_0000_0400: CSRAddr = 13'h301;
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36'h0_0000_0800: CSRAddr = 13'h30A;
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36'h0_0000_1000: CSRAddr = 13'hF14;
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36'h0_0000_2000: CSRAddr = 13'h340;
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36'h0_0000_4000: CSRAddr = 13'h342;
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36'h0_0000_8000: CSRAddr = 13'h343;
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36'h0_0001_0000: CSRAddr = 13'hF11;
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36'h0_0002_0000: CSRAddr = 13'hF12;
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36'h0_0004_0000: CSRAddr = 13'hF13;
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36'h0_0008_0000: CSRAddr = 13'hF15;
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36'h0_0010_0000: CSRAddr = 13'h34A;
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36'h0_0020_0000: CSRAddr = 13'h100;
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36'h0_0040_0000: CSRAddr = 13'h104;
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36'h0_0080_0000: CSRAddr = 13'h105;
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36'h0_0100_0000: CSRAddr = 13'h141;
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36'h0_0200_0000: CSRAddr = 13'h106;
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36'h0_0400_0000: CSRAddr = 13'h10A;
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36'h0_0800_0000: CSRAddr = 13'h180;
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36'h0_1000_0000: CSRAddr = 13'h140;
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36'h0_2000_0000: CSRAddr = 13'h143;
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36'h0_4000_0000: CSRAddr = 13'h142;
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36'h0_8000_0000: CSRAddr = 13'h144;
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36'h1_0000_0000: CSRAddr = 13'h14D;
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36'h2_0000_0000: CSRAddr = 13'h001;
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36'h4_0000_0000: CSRAddr = 13'h002;
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36'h8_0000_0000: CSRAddr = 13'h003;
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default : CSRAddr = 13'h000;
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end
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end
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endmodule
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47
src/wally/priorityaomux.sv
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src/wally/priorityaomux.sv
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///////////////////////////////////////////
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// priorityaomux.sv
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//
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// Written: Rose Thompson ross1728@gmail.com
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// Created: 24 January 2024
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// Modified: 24 January 2024
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//
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// Purpose: priority AND-OR MUX.
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//
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// Documentation:
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module priorityaomux #(parameter ROWS = 8, COLS = 64) (
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input logic [ROWS-1:0] Sel,
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input var logic [COLS-1:0] A [ROWS-1:0],
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output logic [COLS-1:0] Y,
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output logic [ROWS-1:0] SelPriority);
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logic [ROWS-1:0] SelPriority;
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logic [COLS-1:0] AMasked [ROWS-1:0];
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genvar index;
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priorityonehot #(ROWS) priorityonehot(Sel, SelPriority);
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for(index = 0; index < ROWS; index = index + 1) begin
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assign AMasked[index] = SelPriority[index] ? A[index] : '0;
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end
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or_rows #(ROWS, COLS) or_rows(AMasked, Y);
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endmodule
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41
src/wally/regchangedetect.sv
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41
src/wally/regchangedetect.sv
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///////////////////////////////////////////
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// regchangedetect.sv
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//
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// Written: Rose Thompson ross1728@gmail.com
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// Created: 24 January 2024
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// Modified: 24 January 2024
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//
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// Purpose:
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//
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// Documentation:
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module regchangedetect #(parameter XLEN = 64) (
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input clk, reset,
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input logic [XLEN-1:0] Value,
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output logic Change);
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logic [XLEN-1:0] ValueD;
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flopr #(XLEN) register(clk, reset, Value, ValueD);
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assign Change = |(Value ^ ValueD);
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endmodule
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@ -28,14 +28,16 @@
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////////////////////////////////////////////////////////////////////////////////////////////////
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module rvvisynth import cvw::*; #(parameter cvw_t P,
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parameter integer MAX_CSR)(
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parameter integer MAX_CSRS)(
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input logic clk, reset,
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output logic valid,
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output logic [163+P.XLEN-1:0] Requied,
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output logic [12+2*P.XLEN-1:0] Registers,
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output logic [12+MAX_CSR*(P.XLEN+12)-1:0] CSRs
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output logic [12+MAX_CSRS*(P.XLEN+12)-1:0] CSRs
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);
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localparam TOTAL_CSRS = 36;
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// pipeline controlls
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logic StallW, FlushW;
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// required
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@ -50,7 +52,12 @@ module rvvisynth import cvw::*; #(parameter cvw_t P,
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logic [4:0] GPRAddr, FPRAddr;
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logic [P.XLEN-1:0] GPRValue, FPRValue;
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logic [P.XLEN-1:0] XLENZeros;
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logic [P.XLEN-1:0] CSRArray [TOTAL_CSRS-1:0];
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logic [TOTAL_CSRS-1:0] CSRArrayWen;
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logic [MAX_CSRS-1:0] CSRValue [P.XLEN-1:0];
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logic [MAX_CSRS-1:0] CSRWen [TOTAL_CSRS-1:0];
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logic [MAX_CSRS-1:0] CSRAddr [11:0];
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// get signals from the core.
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assign StallW = testbench.dut.core.StallW;
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assign FlushW = testbench.dut.core.FlushW;
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@ -68,6 +75,44 @@ module rvvisynth import cvw::*; #(parameter cvw_t P,
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assign FPRWen = testbench.dut.core.fpu.fpu.fregfile.we4;
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assign FPRValue = testbench.dut.core.fpu.fpu.fregfile.wd4;
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assign CSRArray[0] = testbench.dut.core.priv.priv.csr.csrm.MSTATUS_REGW; // 12'h300
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assign CSRArray[1] = testbench.dut.core.priv.priv.csr.csrm.MSTATUSH_REGW; // 12'h310
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assign CSRArray[2] = testbench.dut.core.priv.priv.csr.csrm.MTVEC_REGW; // 12'h305
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assign CSRArray[3] = testbench.dut.core.priv.priv.csr.csrm.MEPC_REGW; // 12'h341
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assign CSRArray[4] = testbench.dut.core.priv.priv.csr.csrm.MCOUNTEREN_REGW; // 12'h306
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assign CSRArray[5] = testbench.dut.core.priv.priv.csr.csrm.MCOUNTINHIBIT_REGW; // 12'h320
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assign CSRArray[6] = testbench.dut.core.priv.priv.csr.csrm.MEDELEG_REGW; // 12'h302
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assign CSRArray[7] = testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW; // 12'h303
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assign CSRArray[8] = testbench.dut.core.priv.priv.csr.csrm.MIP_REGW; // 12'h344
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assign CSRArray[9] = testbench.dut.core.priv.priv.csr.csrm.MIE_REGW; // 12'h304
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assign CSRArray[10] = testbench.dut.core.priv.priv.csr.csrm.MISA_REGW; // 12'h301
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assign CSRArray[11] = testbench.dut.core.priv.priv.csr.csrm.MENVCFG_REGW; // 12'h30A
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assign CSRArray[12] = testbench.dut.core.priv.priv.csr.csrm.MHARTID_REGW; // 12'hF14
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assign CSRArray[13] = testbench.dut.core.priv.priv.csr.csrm.MSCRATCH_REGW; // 12'h340
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assign CSRArray[14] = testbench.dut.core.priv.priv.csr.csrm.MCAUSE_REGW; // 12'h342
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assign CSRArray[15] = testbench.dut.core.priv.priv.csr.csrm.MTVAL_REGW; // 12'h343
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assign CSRArray[16] = 0; // 12'hF11
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assign CSRArray[17] = 0; // 12'hF12
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assign CSRArray[18] = {{P.XLEN-12{1'b0}}, 12'h100}; //P.XLEN'h100; // 12'hF13
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assign CSRArray[19] = 0; // 12'hF15
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assign CSRArray[20] = 0; // 12'h34A
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// supervisor CSRs
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assign CSRArray[21] = testbench.dut.core.priv.priv.csr.csrs.csrs.SSTATUS_REGW; // 12'h100
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assign CSRArray[22] = testbench.dut.core.priv.priv.csr.csrm.MIE_REGW & 12'h222; // 12'h104
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assign CSRArray[23] = testbench.dut.core.priv.priv.csr.csrs.csrs.STVEC_REGW; // 12'h105
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assign CSRArray[24] = testbench.dut.core.priv.priv.csr.csrs.csrs.SEPC_REGW; // 12'h141
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assign CSRArray[25] = testbench.dut.core.priv.priv.csr.csrs.csrs.SCOUNTEREN_REGW; // 12'h106
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assign CSRArray[26] = testbench.dut.core.priv.priv.csr.csrs.csrs.SENVCFG_REGW; // 12'h10A
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assign CSRArray[27] = testbench.dut.core.priv.priv.csr.csrs.csrs.SATP_REGW; // 12'h180
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assign CSRArray[28] = testbench.dut.core.priv.priv.csr.csrs.csrs.SSCRATCH_REGW; // 12'h140
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assign CSRArray[29] = testbench.dut.core.priv.priv.csr.csrs.csrs.STVAL_REGW; // 12'h143
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assign CSRArray[30] = testbench.dut.core.priv.priv.csr.csrs.csrs.SCAUSE_REGW; // 12'h142
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assign CSRArray[31] = testbench.dut.core.priv.priv.csr.csrm.MIP_REGW & 12'h222 & testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW; // 12'h144
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assign CSRArray[32] = testbench.dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW; // 12'h14D
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// user CSRs
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assign CSRArray[33] = testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW; // 12'h001
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assign CSRArray[34] = testbench.dut.core.priv.priv.csr.csru.csru.FRM_REGW; // 12'h002
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assign CSRArray[35] = {testbench.dut.core.priv.priv.csr.csru.csru.FRM_REGW, testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW}; // 12'h003
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//
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assign XLENZeros = '0;
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@ -89,5 +134,27 @@ module rvvisynth import cvw::*; #(parameter cvw_t P,
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{FPRWen, GPRWen} == 2'b10 ? {FPRValue, FPRAddr, XLENZeros, 5'b0, FPRWen, GPRWen} :
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{XLENZeros, 5'b0, XLENZeros, 5'b0, FPRWen, GPRWen};
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// the CSRs are complex
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// 1. we need to get the CSR values
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// 2. we check if the CSR value changes by registering the value then XORing with the old value.
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// 3. Then use priorityaomux to collect CSR values and addresses for compating into the compressed rvvi format
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// step 2
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genvar index;
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for (index = 0; index < TOTAL_CSRS; index = index + 1) begin
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regchangedetect #(P.XLEN) changedetect(clk, reset, CSRArray[index], CSRArrayWen[index]);
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end
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// step 3a
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for(index = 0; index < MAX_CSRS; index = index + 1) begin
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logic [NUM_CSRS-index-1:0] CSRWenShort;
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priorityaomux #(NUM_CSRS-index, P.XLEN) priorityaomux(CSRArrayWen[MAX_CSRS-1:index], CSRArray[MAX_CSRS-1:index], CSRValue[index], CSRWenShort);
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assign CSRWen[index] = {{{index}{1'b0}}, CSRWenShort};
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// step 3b
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csrindextoaddr #(NUM_CSRS) csrindextoaddr(CSRWen, CSRAddr);
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assign CSRs[(index+1) * P.XLEN - 1 + 12 + 12: index * P.XLEN + 12] = {CSRValue[index], CSRAddr[index]};
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end
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endmodule
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