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Fix FLI to support quads

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This commit is contained in:
David Harris 2024-01-29 14:51:21 -08:00
parent 32c102d89a
commit 3db5b6d9a9
2 changed files with 2 additions and 2 deletions
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2
sim/lint-wally
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@ -1,6 +1,6 @@
#!/bin/bash
# check for warnings in Verilog code
# The verilator lint tool is faster and better than Modelsim so it is best to run this first.
# The verilator lint tool is faster and better than Questa so it is best to run this first.
export PATH=$PATH:/usr/local/bin/
verilator=`which verilator`

2
src/fpu/fli.sv
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@ -175,7 +175,7 @@ module fli import cvw::*; #(parameter cvw_t P) (
////////////////////////////
if (P.Q_SUPPORTED) begin
logic [63:0] QImm;
logic [127:0] QImm;
always_comb begin
case(Rs1)
0: QImm = 128'hBFFF0000000000000000000000000000;