Added Wally github address to header comments

bin/CModelBTBAccuracy.sh

@@ -9,6 +9,7 @@
 ##          Computes the geometric mean for btb accuracy
 ##
 ## A component of the CORE-V-WALLY configurable RISC-V project.
+## https://github.com/openhwgroup/cvw
 ##
 ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 ##

bin/CModelBranchAccuracy.sh

@@ -9,6 +9,7 @@
 ##          Computes the geometric mean.
 ##
 ## A component of the CORE-V-WALLY configurable RISC-V project.
+## https://github.com/openhwgroup/cvw
 ##
 ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 ##

bin/CacheSim.py

@@ -10,6 +10,7 @@
 ## Purpose: Simulate a L1 D$ or I$ for comparison with Wally
 ##
 ## A component of the CORE-V-WALLY configurable RISC-V project.
+## https://github.com/openhwgroup/cvw
 ##
 ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 ##

bin/SeparateBranch.sh

@@ -12,6 +12,7 @@
 ##          separated by benchmark application.  Example names are aha-mot64bd_sizeopt_speed_branch.log
 ##
 ## A component of the CORE-V-WALLY configurable RISC-V project.
+## https://github.com/openhwgroup/cvw
 ##
 ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 ##

bin/derivgen.pl

@@ -0,0 +1,58 @@
+#!/bin/perl -W
+
+###########################################
+## derivgen.pl
+##
+## Written: David_Harris@hmc.edu 
+## Created: 29 January 2024
+## Modified: 
+##
+## Purpose: Read config/derivlist.txt and generate config/deriv/*/config.vh
+##          derivative configurations from the base configurations
+##
+## A component of the CORE-V-WALLY configurable RISC-V project.
+## https://github.com/openhwgroup/cvw
+## https://github.com/openhwgroup/cvw
+##
+## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+##
+## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+##
+## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+## except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+## may obtain a copy of the License at
+##
+## https:##solderpad.org/licenses/SHL-2.1/
+##
+## Unless required by applicable law or agreed to in writing, any work distributed under the 
+## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+## either express or implied. See the License for the specific language governing permissions 
+## and limitations under the License.
+################################################################################################
+
+
+use strict;
+use warnings;
+import os;
+
+if ($#ARGV != 0) {
+    die("Usage: $0 workpath [e.g. $0 \$WALLY/addins/riscv-arch-test/work")
+}
+my $mypath = $ARGV[0];
+my @dirs = glob($mypath.'/*/*');
+foreach my $dir (@dirs) {
+    $dir =~ /.*\/(.*)\/(.*)/;
+    my $arch = $1;
+    my $ext = $2;
+    my $contents = `grep --with-filename "<begin_signature>:" $dir/*.objdump`;
+    my @lines = split('\n', $contents);
+    print "$arch/$ext";
+    foreach my $line (@lines) {
+        $line =~ /.*\/(.*)\.elf.objdump:(\S*)/;
+        my $fname = $1;
+        my $adr = $2;
+        my $partialaddress = substr($adr, -6);
+        print ",\n\t\t\"$arch/$ext/$fname\", \"$partialaddress\"";
+    }
+    print("\n\n");
+}

bin/elf2hex.sh

@@ -9,6 +9,7 @@
 ##          Imperas and riscv-arch-test benchmarks
 ##
 ## A component of the CORE-V-WALLY configurable RISC-V project.
+## https://github.com/openhwgroup/cvw
 ##
 ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 ##

bin/exe2memfile.pl

@@ -11,6 +11,7 @@
 ##          to read into a Verilog simulation with $readmemh
 ##
 ## A component of the CORE-V-WALLY configurable RISC-V project.
+## https://github.com/openhwgroup/cvw
 ##
 ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 ##

bin/fparchtest.sh

@@ -0,0 +1,21 @@
+#!/usr/bin/bash
+#
+# fparchtest.sh
+# David_Harris@hmc.edu 26 December 2023
+#
+# Drive the riscv-isac and riscv-ctg tools to generate floating-point tests
+
+# Set up with (not retested)
+# cd ~/repos
+# git clone https://github.com/riscv/riscv-ctg.git
+# git clone https://github.com/riscv/riscv-isac.git
+# pip3 install git+https://github.com/riscv/riscv-ctg.git
+# pip3 install git+https://github.com/riscv/riscv-isac.git
+# Put ~/.local/bin in $PATH to find riscv_isac and riscv_ctg
+
+RISCVCTG=/home/harris/repos/riscv-ctg
+
+#riscv_isac --verbose debug  normalize -c $RISCVCTG/sample_cgfs/dataset.cgf -c $RISCVCTG/sample_cgfs/sample_cgfs_fext/RV32F/fadd.s.cgf -o $RISCVCTG/tests/normalizedfadd.cgf -x 32
+#riscv_isac --verbose debug  normalize -c $RISCVCTG/sample_cgfs/dataset.cgf -c $RISCVCTG/sample_cgfs/sample_cgfs_fext/RV32H/fadd_b1.s.cgf -o $RISCVCTG/tests/normalizedfadd16_b1.cgf -x 32
+riscv_ctg -cf $RISCVCTG/tests/normalizedfadd16_b1.cgf -d $RISCVCTG/tests --base-isa rv32i --verbose debug
+#riscv_ctg -cf $RISCVCTG/sample_cgfs/dataset.cgf -cf  $RISCVCTG/sample_cgfs/rv32im.cgf -d $RISCVCTG/tests --base-isa rv32i # --verbose debug

bin/imperas-one-time.sh

@@ -9,6 +9,7 @@
 ## Purpose: One time setup script for running imperas.
 ## 
 ## A component of the CORE-V-WALLY configurable RISC-V project.
+## https://github.com/openhwgroup/cvw
 ## 
 ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 ##

bin/libppa.pl

@@ -13,6 +13,7 @@
 ## and for TSMC change the $cellname to the actual name of the inverter.
 ##
 ## A component of the CORE-V-WALLY configurable RISC-V project.
+## https://github.com/openhwgroup/cvw
 ##
 ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 ##

bin/parseHPMC.py

@@ -8,6 +8,7 @@
 ## Purpose: Parses the performance counters from a modelsim trace.
 ##
 ## A component of the CORE-V-WALLY configurable RISC-V project.
+## https://github.com/openhwgroup/cvw
 ##
 ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 ##

bin/testcount.pl

@@ -12,6 +12,7 @@
 ##          and count how many tests are in each
 ##
 ## A component of the CORE-V-WALLY configurable RISC-V project.
+## https://github.com/openhwgroup/cvw
 ##
 ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 ##

bin/testlist.pl

@@ -11,6 +11,7 @@
 ##          and generate a list of tests and signature addresses for tests.vh
 ##
 ## A component of the CORE-V-WALLY configurable RISC-V project.
+## https://github.com/openhwgroup/cvw
 ##
 ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 ##

bin/vclean.pl

@@ -11,6 +11,7 @@
 ##          verilator should do this, but it also reports partially used signals
 ##
 ## A component of the CORE-V-WALLY configurable RISC-V project.
+## https://github.com/openhwgroup/cvw
 ##
 ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 ##

bin/wally-tool-chain-install.sh

@@ -10,6 +10,7 @@
 ## Purpose: Open source tool chain installation script
 ##
 ## A component of the CORE-V-WALLY configurable RISC-V project.
+## https://github.com/openhwgroup/cvw
 ##
 ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 ##

config/derivlist.txt

@@ -0,0 +1,73 @@
+###########################################
+## derivlist.txt
+## Wally Derivative Configuration List
+##
+## Written: David_Harris@hmc.edu 
+## Created: 29 January 2024
+## Modified: 
+##
+## Purpose: Used by sim/make deriv to generate derivative configurations
+##          in config/deriv that are variants of the base configurations.
+##
+## A component of the CORE-V-WALLY configurable RISC-V project.
+## https://github.com/openhwgroup/cvw
+##
+## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+##
+## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+##
+## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+## except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+## may obtain a copy of the License at
+##
+## https:##solderpad.org/licenses/SHL-2.1/
+##
+## Unless required by applicable law or agreed to in writing, any work distributed under the 
+## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+## either express or implied. See the License for the specific language governing permissions 
+## and limitations under the License.
+################################################################################################
+
+# Format:
+# begin a derivative with "deriv <derivative name> <base configuration name> <inherited config name>
+# Followed by a list of parameters and their new value in the derivative configuration
+# All other parameter values are inherited from the original configuration
+# If <inherited config name> is not empty, all the list of parameter changes in the inherited 
+# configuration are also applied to this configuration
+
+deriv   buildroot   rv64gc
+RESET_VECTOR    64'h1000
+UNCORE_RAM_RANGE    64'h0FFFFFFF
+UNCORE_RAM_PRELOAD  1
+GPIO_LOOPBACK_TEST  0
+SPI_LOOBACK_TEST    0   
+UART_PRESCALE       0
+PLIC_NUM_SRC        32'd53
+
+deriv fpga  rv64gc buildroot
+BOOTROM_PRELOAD     1
+UNCORE_RAM_BASE     64'h2000
+UNCORE_RAM_RANGE    64'hFFF
+EXT_MEM_SUPPORTED   1
+EXT_MEM_BASE        64'h80000000
+EXT_MEM_RANGE       64'h0FFFFFFF
+SDC_SUPPORTED       1
+PLIC_SDC_ID         32'd20
+BPRED_SIZE          32'd12
+
+deriv   syn_rv32e   rv32e
+DTIM_RANGE          32'h1FF
+IROM_RANGE          32'h1FF
+BOOTROM_RANGE       32'h1FF
+UNCORE_RAM_RANGE    32'h1FF
+BOOTROM_RANGE       32'h1FF
+WAYSIZEINBYTES      32'd512
+NUMWAYS             32'd1
+BPRED_SIZE          32'd5
+BTB_SIZE            32'd5 
+
+deriv syn_rv32i rv32i syn_rv32e
+deriv syn_rv32imc rv32imc syn_rv32e
+deriv syn_rv32gc rv32gc syn_rv32e
+deriv syn_rv64i rv64i syn_rv32e
+deriv syn_rv64gc rv64gc syn_rv32e

docs/Dockerfile

@@ -7,6 +7,7 @@
 ## Purpose: Dockerfile for Wally docker container creation
 ## 
 ## A component of the CORE-V-WALLY configurable RISC-V project.
+## https://github.com/openhwgroup/cvw
 ## 
 ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 ##

fpga/generator/insert_debug_comment.sh

@@ -7,6 +7,7 @@
 ## Modified: 20 January 2023
 ##
 ## A component of the CORE-V-WALLY configurable RISC-V project.
+## https://github.com/openhwgroup/cvw
 ##
 ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 ##

fpga/probe

@@ -7,6 +7,7 @@
 ## Modified: 16 August 2023
 ##
 ## A component of the CORE-V-WALLY configurable RISC-V project.
+## https://github.com/openhwgroup/cvw
 ##
 ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 ##

fpga/proberange

@@ -7,6 +7,7 @@
 ## Modified: 16 August 2023
 ##
 ## A component of the CORE-V-WALLY configurable RISC-V project.
+## https://github.com/openhwgroup/cvw
 ##
 ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 ##

fpga/probes

@@ -7,6 +7,7 @@
 ## Modified: 16 August 2023
 ##
 ## A component of the CORE-V-WALLY configurable RISC-V project.
+## https://github.com/openhwgroup/cvw
 ##
 ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 ##

gitflow.txt

@@ -1,5 +1,6 @@
 ###########################################
 ## A component of the CORE-V-WALLY configurable RISC-V project.
+## https://github.com/openhwgroup/cvw
 ##
 ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 ##

sim/coverage-exclusions-rv64gc.do

@@ -7,6 +7,7 @@
 #//          For example, signals hardwired to 0 should not be checked for toggle coverage
 #//
 #// A component of the CORE-V-WALLY configurable RISC-V project.
+#// https://github.com/openhwgroup/cvw
 #// 
 #// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 #//

sim/rv64gc_CacheSim.py

@@ -10,6 +10,7 @@
 ## Purpose: Run the cache simulator on each rv64gc test suite in turn. 
 ##
 ## A component of the CORE-V-WALLY configurable RISC-V project.
+## https://github.com/openhwgroup/cvw
 ##
 ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 ##

sim/sim-imperas

@@ -10,6 +10,7 @@
 ## Purpose: Run wally with imperas
 ## 
 ## A component of the CORE-V-WALLY configurable RISC-V project.
+## https://github.com/openhwgroup/cvw
 ## 
 ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 ##

src/cache/cache.sv

@@ -10,6 +10,7 @@
 // Documentation: RISC-V System on Chip Design Chapter 7 (Figures 7.9, 7.10, and 7.19)
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 //
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/cache/cacheLRU.sv

@@ -10,6 +10,7 @@
 // Documentation: RISC-V System on Chip Design Chapter 7 (Figures 7.8 and 7.15 to 7.18)
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 //
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/cache/cachefsm.sv

@@ -10,6 +10,7 @@
 // Documentation: RISC-V System on Chip Design Chapter 7 (Figure 7.14 and Table 7.1)
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 //
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/cache/cacheway.sv

@@ -10,6 +10,7 @@
 // Documentation: RISC-V System on Chip Design Chapter 7 (Figure 7.11)
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/cache/subcachelineread.sv

@@ -10,6 +10,7 @@
 // Documentation: RISC-V System on Chip Design Chapter 7
 
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 //
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/ebu/ahbcacheinterface.sv

@@ -10,6 +10,7 @@
 // Documentation: RISC-V System on Chip Design Chapter 9 (Figure 9.8)
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/ebu/ahbinterface.sv

@@ -10,6 +10,7 @@
 // Documentation: RISC-V System on Chip Design Chapter 6 (Figure 6.21)
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/ebu/buscachefsm.sv

@@ -10,6 +10,7 @@
 // Documentation: RISC-V System on Chip Design Chapter 9 (Figure 9.9)
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/ebu/busfsm.sv

@@ -10,6 +10,7 @@
 // Documentation: RISC-V System on Chip Design Chapter 6 (Figure 6.23)
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/ebu/controllerinput.sv

@@ -14,6 +14,7 @@
 // Documentation: RISC-V System on Chip Design Chapter 6 (Figure 6.25)
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/ebu/ebu.sv

@@ -14,6 +14,7 @@
 // Documentation: RISC-V System on Chip Design Chapter 6 (Figures 6.25 and 6.26)
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/ebu/ebufsmarb.sv

@@ -11,6 +11,7 @@
 // Documentation: RISC-V System on Chip Design Chapter 6 (Figures 6.25 and 6.26)
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/fpu/fclassify.sv

@@ -9,6 +9,7 @@
 // Documentation: RISC-V System on Chip Design Chapter 13
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/fpu/fcmp.sv

@@ -9,6 +9,7 @@
 // Documentation: RISC-V System on Chip Design Chapter 13
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/fpu/fctrl.sv

@@ -9,6 +9,7 @@
 // Documentation: RISC-V System on Chip Design Chapter 13
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/fpu/fdivsqrt/fdivsqrt.sv

@@ -9,6 +9,7 @@
 // Documentation: RISC-V System on Chip Design Chapter 13
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/fpu/fdivsqrt/fdivsqrtcycles.sv

@@ -9,6 +9,7 @@
 // Documentation: RISC-V System on Chip Design Chapter 13
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/fpu/fdivsqrt/fdivsqrtexpcalc.sv

@@ -9,6 +9,7 @@
 // Documentation: RISC-V System on Chip Design Chapter 13
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/fpu/fdivsqrt/fdivsqrtfgen2.sv

@@ -9,6 +9,7 @@
 // Documentation: RISC-V System on Chip Design Chapter 13
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/fpu/fdivsqrt/fdivsqrtfgen4.sv

@@ -9,6 +9,7 @@
 // Documentation: RISC-V System on Chip Design Chapter 13
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/fpu/fdivsqrt/fdivsqrtfsm.sv

@@ -9,6 +9,7 @@
 // Documentation: RISC-V System on Chip Design Chapter 13
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/fpu/fdivsqrt/fdivsqrtiter.sv

@@ -9,6 +9,7 @@
 // Documentation: RISC-V System on Chip Design Chapter 13
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/fpu/fdivsqrt/fdivsqrtpostproc.sv

@@ -9,6 +9,7 @@
 // Documentation: RISC-V System on Chip Design Chapter 13
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/fpu/fdivsqrt/fdivsqrtpreproc.sv

@@ -9,6 +9,7 @@
 // Documentation: RISC-V System on Chip Design Chapter 13
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/fpu/fdivsqrt/fdivsqrtstage2.sv

@@ -9,6 +9,7 @@
 // Documentation: RISC-V System on Chip Design Chapter 13
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/fpu/fdivsqrt/fdivsqrtstage4.sv

@@ -9,6 +9,7 @@
 // Documentation: RISC-V System on Chip Design Chapter 13
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/fpu/fdivsqrt/fdivsqrtuotfc2.sv

@@ -9,6 +9,7 @@
 // Documentation: RISC-V System on Chip Design Chapter 13
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/fpu/fdivsqrt/fdivsqrtuotfc4.sv

@@ -9,6 +9,7 @@
 // Documentation: RISC-V System on Chip Design Chapter 13
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/fpu/fdivsqrt/fdivsqrtuslc2.sv

@@ -9,6 +9,7 @@
 // Documentation: RISC-V System on Chip Design Chapter 13
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/fpu/fdivsqrt/fdivsqrtuslc4.sv

@@ -9,6 +9,7 @@
 // Documentation: RISC-V System on Chip Design Chapter 13
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv

@@ -9,6 +9,7 @@
 // Documentation: RISC-V System on Chip Design Chapter 13
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/fpu/fhazard.sv

@@ -9,6 +9,7 @@
 // Documentation: RISC-V System on Chip Design Chapter 13
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/fpu/fli.sv

@@ -9,6 +9,7 @@
 // Documentation: RISC-V System on Chip Design Chapter 16
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/fpu/fma/fma.sv

@@ -9,6 +9,7 @@
 // Documentation: RISC-V System on Chip Design Chapter 13 (Figure 13.7, 9)
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/fpu/fma/fmaadd.sv

@@ -9,6 +9,7 @@
 // Documentation: RISC-V System on Chip Design Chapter 13 (Figure 13.11)
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/fpu/fma/fmaalign.sv

@@ -9,6 +9,7 @@
 // Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.10)
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/fpu/fma/fmaexpadd.sv

@@ -9,6 +9,7 @@
 // Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.9)
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/fpu/fma/fmalza.sv

@@ -10,6 +10,7 @@
 //    See also [Schmookler & Nowka, Leading zero anticipation and detection, IEEE Sym. Computer Arithmetic, 2001]
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/fpu/fma/fmamult.sv

@@ -9,6 +9,7 @@
 // Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.7)
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/fpu/fma/fmasign.sv

@@ -9,6 +9,7 @@
 // Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.8)
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/fpu/fpu.sv

@@ -9,6 +9,7 @@
 // Documentation: RISC-V System on Chip Design Chapter 13
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/fpu/fregfile.sv

@@ -9,6 +9,7 @@
 // Documentation: RISC-V System on Chip Design Chapter 13
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/fpu/fsgninj.sv

@@ -9,6 +9,7 @@
 // Documentation: RISC-V System on Chip Design Chapter 13
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/fpu/postproc/cvtshiftcalc.sv

@@ -9,6 +9,7 @@
 // Documentation: RISC-V System on Chip Design Chapter 13
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/fpu/postproc/divshiftcalc.sv

@@ -9,6 +9,7 @@
 // Documentation: RISC-V System on Chip Design Chapter 13
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/fpu/postproc/flags.sv

@@ -9,6 +9,7 @@
 // Documentation: RISC-V System on Chip Design Chapter 13
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/fpu/postproc/fmashiftcalc.sv

@@ -9,6 +9,7 @@
 // Documentation: RISC-V System on Chip Design Chapter 13
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/fpu/postproc/negateintres.sv

@@ -9,6 +9,7 @@
 // Documentation: RISC-V System on Chip Design Chapter 13
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/fpu/postproc/normshift.sv

@@ -9,6 +9,7 @@
 // Documentation: RISC-V System on Chip Design Chapter 13
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/fpu/postproc/postprocess.sv

@@ -9,6 +9,7 @@
 // Documentation: RISC-V System on Chip Design Chapter 13
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/fpu/postproc/resultsign.sv

@@ -9,6 +9,7 @@
 // Documentation: RISC-V System on Chip Design Chapter 13
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/fpu/postproc/round.sv

@@ -9,6 +9,7 @@
 // Documentation: RISC-V System on Chip Design Chapter 13
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/fpu/postproc/roundsign.sv

@@ -9,6 +9,7 @@
 // Documentation: RISC-V System on Chip Design Chapter 13
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/fpu/postproc/shiftcorrection.sv

@@ -9,6 +9,7 @@
 // Documentation: RISC-V System on Chip Design Chapter 13
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/fpu/postproc/specialcase.sv

@@ -9,6 +9,7 @@
 // Documentation: RISC-V System on Chip Design Chapter 13
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/fpu/unpack.sv

@@ -9,6 +9,7 @@
 // Documentation: RISC-V System on Chip Design Chapter 13
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/fpu/unpackinput.sv

@@ -9,6 +9,7 @@
 // Documentation: RISC-V System on Chip Design Chapter 13
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/generic/adder.sv

@@ -7,6 +7,7 @@
 // Purpose: Adder
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/generic/aplusbeq0.sv

@@ -7,6 +7,7 @@
 // Purpose: Determine if A+B = 0.  Used in FP divider.
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/generic/arrs.sv

@@ -10,6 +10,7 @@
 //          rising edge, but then syncs the falling edge to the posedge clk.
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/generic/binencoder.sv

@@ -6,6 +6,7 @@
 // Purpose: one-hot to binary encoding.
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 //
 // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
 //

src/generic/clockgater.sv

@@ -7,6 +7,7 @@
 // Purpose: Clock gater model. Must use standard cell for synthesis.
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/generic/counter.sv

@@ -7,6 +7,7 @@
 // Purpose: Counter with reset and enable
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/generic/csa.sv

@@ -7,6 +7,7 @@
 // Purpose: 3:2 carry-save adder
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/generic/decoder.sv

@@ -7,6 +7,7 @@
 // Purpose: Binary encoding to one-hot decoder
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 //
 // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
 //

src/generic/flop/flop.sv

@@ -7,6 +7,7 @@
 // Purpose: D flip-flop
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/generic/flop/flopen.sv

@@ -7,6 +7,7 @@
 // Purpose: D flip-flop with enable
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/generic/flop/flopenl.sv

@@ -7,6 +7,7 @@
 // Purpose: D flip-flop with enable and synchronous load
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/generic/flop/flopenr.sv

@@ -7,6 +7,7 @@
 // Purpose: D flip-flop with enable, synchronous reset
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/generic/flop/flopenrc.sv

@@ -7,6 +7,7 @@
 // Purpose: D flip-flop with enable, synchronous reset, enabled clear
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/generic/flop/flopens.sv

@@ -7,6 +7,7 @@
 // Purpose: D flip-flop with enable, synchronous set
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/generic/flop/flopr.sv

@@ -7,6 +7,7 @@
 // Purpose: D flip-flop with synchronous reset
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/generic/flop/floprc.sv

@@ -7,6 +7,7 @@
 // Purpose: D flip-flop with synchronous reset and clear
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/generic/flop/synchronizer.sv

@@ -7,6 +7,7 @@
 // Purpose: Two-stage flip-flop synchronizer
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

src/generic/lzc.sv

@@ -6,6 +6,7 @@
 // Purpose: Leading Zero Counter
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //