Rose Thompson cbc44a68ab Merge branch 'main' of https://github.com/openhwgroup/cvw		2024-01-26 12:50:36 -06:00
..
cache	Coverage improvements	2024-01-22 09:49:24 -08:00
ebu	Atomics work correctly without a d cache.	2024-01-16 10:43:20 -06:00
fpu	Fixed FPU coverage, solved Issue 596 by misaligned AMO throwing access fault when misaligned non-amo are supported	2024-01-25 21:03:41 -08:00
generic	Revert RAM logic to bit change.	2023-12-20 13:10:20 -06:00
hazard	Moved forwarding logic into controller	2023-12-26 21:17:01 -08:00
ieu	Added StoreStall back to csrc.	2024-01-18 14:43:34 -06:00
ifu	Added logic for the non-cache atomics.	2024-01-15 17:47:17 -06:00
lsu	Lint passes with 32-bit no D$, but many regressions fail.	2024-01-18 09:48:44 -06:00
mdu	turn off IDIVONFPU when FSUPPORTED=0. Already checked in sim, but need it in synth too for feature sweep	2023-11-17 20:25:24 -08:00
mmu	HPTW coverage improvements	2024-01-26 10:46:38 -08:00
privileged	Added StoreStall back to csrc.	2024-01-18 14:43:34 -06:00
uncore	Reversed numbering of adrdecs to make it easier to add new peripherals without renumbering the old ones; update figure to match	2023-12-21 12:29:37 -08:00
wally	Added StoreStall back to csrc.	2024-01-18 14:43:34 -06:00
cvw.sv	Tested Zfh support using unreleased version of risch-arch-test Zfh tests. Fixed two bugs in fmv to/from int.	2024-01-15 13:24:57 -08:00