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569 Commits

Author SHA1 Message Date
Rose Thompson
5ab88a5daa Updated to simplify configOptions. 2024-02-06 22:07:06 -06:00
David Harris
d71efedab5
Merge pull request #619 from ross144/main 
Merged all regression tests except imperas linux boot into testbench.sv.
 2024-02-06 16:19:42 -08:00
Rose Thompson
da65928f04 Fixed issue with branch deriv configs. 2024-02-06 16:07:41 -06:00
David Harris
dfee790ad7 Fixed derivative generation when derivs don't already exist. Fixed lint to print success when no failures. Added Zfh fma tests. Some fp tests not running yet. 2024-02-06 12:35:56 -08:00
Rose Thompson
58580445ab Only output instruction count when the csrs are implemented. 2024-02-05 14:42:27 -06:00
Rose Thompson
8b5970fdc4 Buildroot now reports every 100K instructions as before. 2024-02-05 13:19:48 -06:00
Rose Thompson
c9176f108e Fixed paths to buildroot objdump label and addr files. 2024-02-05 13:09:31 -06:00
Rose Thompson
17380a68d5 Moved buildroot testbench to the main testbench. 
However I don't have a positive control or negative indicator to
say when the test completes or passes.
 2024-02-05 13:03:48 -06:00
Rose Thompson
44e87f3e3e First cut at removing the linux testbench and merging build root into the main testbench. 2024-02-05 12:46:14 -06:00
David Harris
66c1c71a56 Coverage improvements 2024-02-04 18:56:40 -08:00
David Harris
4e376680be Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2024-02-04 09:34:48 -08:00
Jordan Carlin
0312476fb3 Update tlb camline ASID coverage to use single file 2024-02-03 09:48:57 -08:00
David Harris
fd5e492b2a Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2024-02-01 20:47:20 -08:00
Jordan Carlin
8633f263a2 Complete coverage of tlb camlines in IFU 2024-02-01 20:41:05 -08:00
David Harris
efdc571f59 Removed redundant assertion 2024-02-01 20:14:40 -08:00
Rose Thompson
d59daf9a6f Fixed odd bug in the testbench which wasn't skipping signature check for coverage tests. 2024-02-01 12:22:28 -06:00
David Harris
49714cb282 Fixed assertions to throw fatal error, improved nightly regression to have passing cases 2024-01-31 21:39:18 -08:00
David Harris
111f592613 factor divsqrt out of floating-point test cases to run on more derived configs 2024-01-31 14:52:15 -08:00
David Harris
bf7e20e846 IEEE754 derivatives for testfloat 2024-01-30 09:49:27 -08:00
James E. Stine
0d9e2fdf60 update Boolean logic for all testing for divide 2024-01-29 17:37:35 -06:00
James E. Stine
95a97faf3f Fixes testbench issues in testing against all vectors. Still a bug in ui32_to_f16_rz.sv - but will fix. Some things can be optimized. Overall, adds a FSM to test things more effectively. Actually is faster than previously as it assumed everything took the same number of cycles. Again, some things can be optimized 2024-01-29 16:46:34 -06:00
David Harris
171430a695 FPU and PMP tests 2024-01-21 14:41:22 -08:00
David Harris
17c9be7695 Cleanup typos, remove Zicond from riscof until it is working 2024-01-18 21:36:52 -08:00
David Harris
74b242ce5c Partial implementation of fcvtmod.w.d; flags disagree in one case where Sail might be wrong, and result 134 is wrong because of overflow 2024-01-17 12:25:06 -08:00
David Harris
4cfc86140c Zfa fmvh complete and passing tests: 2024-01-17 06:18:00 -08:00
David Harris
07e7e02241 Coded Zfa fmvp but no tests exist 2024-01-16 21:26:42 -08:00
David Harris
8654375f26 Zfa fminm/fmaxm/fltq/fleq implemented and tested 2024-01-16 20:03:54 -08:00
David Harris
0588d611ea Zfa fli support working for F and D 2024-01-16 17:27:40 -08:00
David Harris
1a77c08f6e Fixed issues 575 and 477 about FPU tests failing when Zfh = 1. 2024-01-16 10:46:44 -08:00
David Harris
0d56a281b9 Cleaned up indentation in testbench-fp 2024-01-15 13:25:46 -08:00
David Harris
da4eca4854 Tested Zfh support using unreleased version of risch-arch-test Zfh tests. Fixed two bugs in fmv to/from int. 2024-01-15 13:24:57 -08:00
David Harris
9e78a7e290 Incorporated jstine fixes of FPU special case and testbench for conversion 2024-01-15 07:25:08 -08:00
David Harris
6226c3db96
Revert "Fixes for Issue #541" 2024-01-12 07:50:13 -08:00
James E. Stine
dbe8394651 Update testbench-fp.sv to check result and flags for cvtint and cmp. This addresses fix for Issue #541. It also adds a temporary fix to avoid issues between tests. This will be fixed in an upcoming push where we use scanf instead of readmemh to help keep compatibility with Verilator. Additional testing is needed of new testbench-fp.sv before can push in new tb with scanf 2024-01-12 00:32:18 -06:00
David Harris
9eb6d9c8b8 Added Zicond support 2024-01-11 07:37:15 -08:00
James E. Stine
828d6bc619 more optimized check on Issue #546 2024-01-09 09:22:39 -06:00
James E. Stine
cfb27de8a3 Fix Issue #541 where FlagMatch was not added which I forgot (apologies) 2024-01-09 08:57:41 -06:00
James E. Stine
f91b749f91 Fix typo missed with === on Issue #541 2024-01-08 22:01:52 -06:00
James E. Stine
79d7bb60ea Address Issue #541 where CVTINT or CMP in testfloat were not checked. The solution was to check inside the nested for loop. This was done to avoid issue related to the values changing between each cvtint or subsequent operation 2024-01-08 21:28:47 -06:00
David Harris
d93684be21 Verilate running (slowly) 2024-01-07 21:30:33 -08:00
David Harris
7cd02351d9 Updated testbench to count size of signature without searching for x. Now runs with Verilator. 2024-01-07 09:00:19 -08:00
David Harris
caedab679a Rewrote testbench to count signature entries rather than looking for x; this will facilitate Verilator which does not use x 2024-01-07 07:14:12 -08:00
David Harris
34f97201ee Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2024-01-06 08:19:56 -08:00
David Harris
167e061a1c Fixed truncated begin_signature in testbench 2024-01-06 08:19:46 -08:00
Rose Thompson
ab07d64195 Fixes coremark. Maybe works with verilator. 2024-01-06 00:41:57 -06:00
David Harris
ed623f1a71 Fixed unsupported riscof YAML string; preparing for Verilator -G testcase 2024-01-05 20:06:21 -08:00
David Harris
d229dc06ee Coverage improvements; remove incorrect logic checking NAPOT nonleaf PTE 2024-01-02 00:35:17 -08:00
David Harris
52b6d1d163 restored tlbNAPOT coverage tests 2023-12-31 09:55:58 -08:00
David Harris
b3ff1035c4 Propagated MIP-based tracer interrupts to testbench-linux-imperas 2023-12-21 11:47:49 -08:00
David Harris
45b5658d06 Updated Imperas testbench to use MIP bits to communicate pending interrupts 2023-12-21 11:05:26 -08:00
David Harris
8552369687 Merged PR538, delete unused tests 2023-12-20 13:30:31 -08:00
Rose Thompson
70d0169019 All regression tests which matter are running! 2023-12-20 14:57:52 -06:00
Rose Thompson
1b59182d59 Updated tests with ending label. 2023-12-20 14:55:37 -06:00
Rose Thompson
b68dd74f89 Reverted logic to bit change. 2023-12-20 13:16:32 -06:00
Rose Thompson
a8ab3c8342 Ok that is a stange bug. 
The testbench used logic for the shadow ram, but the memory used bit. This caused questa to allocate huge amounts of memory and crash. Changing shadow ram to bit fixed the issue.
 2023-12-20 12:25:34 -06:00
Rose Thompson
9ee1ffe8fe Almost working with modelsim and verilator. 2023-12-20 11:29:31 -06:00
David Harris
5dbca251d8 Defined new Zicboz and Zcb tests 2023-12-19 13:24:11 -08:00
Rose Thompson
4f59bd492d Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-12-19 12:06:04 -06:00
Rose Thompson
2e792606dd More progress. Most tests are passing in modelsim. 2023-12-19 12:06:00 -06:00
Rose Thompson
74238defc3 Progress. 2023-12-18 20:23:19 -06:00
David Harris
6186181d46
Merge pull request #537 from ross144/main 
Almost having working Verilator.  One issue in the testbench remains.
 2023-12-18 18:13:56 -08:00
Rose Thompson
1e1759c258 Restored the one hack change which prevents verilator from working. 2023-12-18 17:00:53 -06:00
Rose Thompson
408bb2c35b Yay! I got verilator to compile our testbench! Does it actually work I don't know. 2023-12-18 16:44:34 -06:00
Rose Thompson
0f7b6ada04 Cleanup. 
Verilator still has issues with riscassertions.sv and the testbench
 2023-12-18 16:38:56 -06:00
Rose Thompson
b7b245fe2f functionName.sv is now linting for rv64gc. 2023-12-18 16:37:26 -06:00
Rose Thompson
c1ac153a4f Closer to verilator support. 2023-12-18 16:26:56 -06:00
Rose Thompson
58942b246b Kind of a frustrating set of changes to get the verilator errors out of the copyShadow module. 2023-12-18 13:34:14 -06:00
Rose Thompson
4a3cc8b9c8 More progress towards verilator. 2023-12-18 13:26:43 -06:00
Rose Thompson
5062a8c89c Added parameter for cache's SRAM length. 
Progress towards verilator support.
 2023-12-18 12:50:49 -06:00
David Harris
6ba3ae662f Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-12-17 19:04:50 -08:00
James E. Stine
f4c1713ed4 Fix issue with running all and then going from one operand width to another. Issue is due to signals resolving between sizes. I did not catch it before because I did not run through the complete exhaustive tests. This time, went through all tests and tested all the data sizes. 2023-12-17 20:55:06 -06:00
David Harris
6cb4a9e905 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-12-15 19:27:10 -08:00
David Harris
a138ef37b1 Switched to using riscv-arch-test rv32e_m suite. Need to rename it from rv32e_unratified (PR pending) 2023-12-15 19:26:50 -08:00
James E. Stine
8d8bad61d4 Fix to take care of Issue #507. Issue was caused with time delay in testbench-fp.sv that interfered with the if statement in the DIVSQRT condition for generating a vector. This original time delay was given to guarantee that the previous operation would complete. However, the testbench was modified to make sure this would not happen and this time delay is not needed obviating any issue that caused Issue #507. Some other small enhancements were made to the testbench-fp.sv for beautification, as well. A full test was run on the testbench to check its validity. 2023-12-15 17:02:11 -06:00
David Harris
38f4d9baf8 Use riscv-arch-test arch32e instead of outdated wally-riscv-arch-test wally32e 2023-12-15 05:05:53 -08:00
David Harris
68d96a929c Fixed hierarchical path to EcallFaultM in testbench 2023-12-13 16:37:54 -08:00
David Harris
ff26baf7e8 Rolled back attempt to support Verilator 2023-12-13 12:53:44 -08:00
David Harris
aff61ea97a Fixed Linux makefile; load branch predictor RAMs at startup for sim; fixed comment in trap; starting to make testbench more compatible with Verilator 2023-12-13 11:33:59 -08:00
David Harris
b268a3b9d3 Added SPI support to Imperas testbenches 2023-12-07 09:44:31 -08:00
David Harris
c0801263f1 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-11-23 20:43:22 -08:00
David Harris
bcc20c6bd5 Merge pull request #505 from stineje/main 
Update fix for cvtint testbench-fp
 2023-11-23 20:43:00 -08:00
David Harris
3df4c13daa Updated wallyTracer for Linux boot and wally-batch.do to remove buildroot checkpoint support 2023-11-23 20:36:45 -08:00
David Harris
1f57df7f8b Fixed reference to deleted atomic signal in cache 2023-11-23 20:29:10 -08:00
James E. Stine
1ab7522064 Update fix for cvtint testbench-fp 2023-11-23 17:56:51 -06:00
Rose Thompson
1dac4d221e Disable the trace for normal operation. 2023-11-21 13:49:07 -06:00
Rose Thompson
c77a47b403 Output the instruction trace to the logs directory. 2023-11-21 13:47:58 -06:00
Rose Thompson
b02bd6c835 Finally we got the wally tracer working with linux. 2023-11-21 13:45:55 -06:00
Rose Thompson
3fd6d3464c We are logging now. 2023-11-21 13:02:34 -06:00
Rose Thompson
6ff8d19157 Added code to the wallyTracer to support outputing an instruction trace. 2023-11-21 12:28:19 -06:00
Jacob Pease
a1e7158bd9 Merge branch 'main' of github.com:openhwgroup/cvw 2023-11-18 19:20:48 -06:00
David Harris
8baa5b2e7b Merge pull request #483 from ross144/main 
Fixed branch predictor embench generation results
 2023-11-17 10:07:30 -08:00
Rose Thompson
38b327eaf8 Fixed testbench so it runs with BPRED_LOGGER but not PrintHPMCounters. 2023-11-17 11:21:25 -06:00
Jacob Pease
23e5fca2a7 Merge branch 'main' of github.com:jacobpease/cvw 2023-11-16 14:04:11 -06:00
David Harris
94201e993f Merge pull request #481 from ross144/main 
Fixed the BTB logger so sim_bp correctly reports BTB performance
 2023-11-15 17:45:38 -08:00
Rose Thompson
bc935b1b3b Fixed second bug in the logger script when branch logging enabled but counter logger not. 2023-11-15 14:56:02 -06:00
Rose Thompson
5d4a89b27c Fixed bug in the btb branch logging. 
We were only logging branch instructions not all control flow instructions which dramatically skewed the results for sim_bp.
 2023-11-15 14:51:47 -06:00
David Harris
cfaeeae25a Added cmoz support to imperas.ic and adjusted imperas testbench to no longer need FPGA parameter 2023-11-15 08:15:01 -08:00
Rose Thompson
feb45b9b59 Patched up linux imperas testbench. 2023-11-14 14:20:13 -06:00
Rose Thompson
efc1d732d8 Fixed the imperas testbench to be compatible with the config changes. 2023-11-14 12:57:44 -06:00
David Harris
a77bea9954 Merge pull request #472 from ross144/main 
Merge Zicclsm into main branch and removes the FPGA config.  FPGA makefile now automatically creates the config when building
 2023-11-14 08:34:06 -08:00
Rose Thompson
95fc5f4a1c Towards removing the FPGA config file. 2023-11-13 17:20:26 -06:00
Rose Thompson
da59cb71a9 Commented out the arch64priv misaligned load/store tests since we added Zicclsm to the rv64gc config. 2023-11-13 14:12:27 -06:00
Rose Thompson
540d8d930d Cleanup. 
Linux makefile
wally tracer.  probably reduce some complexity here.
 2023-11-13 14:04:43 -06:00
David Harris
6ac83c776e Cleaned up number of bits in fdivsqrt 2023-11-11 15:50:06 -08:00
David Harris
2bf5143163 Bug fixes related to size of fpdivsqrt bit count and number of cycles 2023-11-11 05:58:53 -08:00
David Harris
448ced00c5 Fixed testbench-fp to reflect signal name changes 2023-11-11 04:05:34 -08:00
Rose Thompson
b74bfbeefd Merge branch 'main' into Zicclsm 2023-11-10 16:15:32 -06:00
Rose Thompson
baacb6f6eb Missed tests.vh. 2023-11-10 16:10:10 -06:00
David Harris
bddd2d573e Shortened path to PCSrcE in logger to avoid problematic hierarchical reference 2023-11-05 07:06:53 -08:00
David Harris
b0dbf3a984 Testbench fixes to add SPI and make string pp static in testbench.fp to solve compiler issue 2023-11-04 20:36:05 -07:00
David Harris
568aa3c4a6 Verilator improvements 2023-11-04 03:21:07 -07:00
David Harris
4de21c206f Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-11-03 16:04:10 -07:00
David Harris
dd072c80f2 Updated testbenches to capture InstrM because it may be optimized out of IFU 2023-11-03 05:24:15 -07:00
David Harris
09aebbf252 Fixed regression error of watchdog timeout when PCM is optimized out of the IFU 2023-11-03 04:38:27 -07:00
naichewa
a08356fdaa correct exclusion tags and reset testbench 2023-11-01 10:34:39 -07:00
naichewa
e3d8162279 harris code review 3 2023-11-01 10:14:15 -07:00
naichewa
7dd3f24d6c Merge branch 'main' into spi 2023-10-30 17:01:41 -07:00
naichewa
2330f4ee63 hardware interlock 2023-10-30 17:00:20 -07:00
Jacob Pease
3e891ee635 Merge branch 'main' of github.com:openhwgroup/cvw 2023-10-17 14:13:28 -05:00
Jacob Pease
2b1c604016 Slight modification to testbench.sv 2023-10-17 14:13:18 -05:00
Rose Thompson
010fbf7319 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-10-17 10:01:35 -05:00
Rose Thompson
faea7db1b2 Reverted linux testbench to not check for match against QEMU. 2023-10-17 10:00:50 -05:00
naichewa
0ff9ce527d Merge branch 'main' into spi 2023-10-16 22:59:50 -07:00
naichewa
4941fe1769 sync fifo passes 2023-10-16 22:57:02 -07:00
David Harris
fab9fbd7f1 Merged testbench 2023-10-16 13:52:24 -07:00
David Harris
1a6e57f8c0 Renamed wally-config to config in many comments 2023-10-16 13:49:09 -07:00
David Harris
ac4216b43d Incorporated new AMO tests from riscv-arch-test 2023-10-16 10:25:45 -07:00
Rose Thompson
8f2ca2ae15 Added missing files. 2023-10-13 15:10:58 -05:00
Rose Thompson
8d4cdcbd1a Renamed testbench_imperas.sv to testbench-imperas.sv 2023-10-13 14:56:45 -05:00
Rose Thompson
c1d6fddea8 Removed P.FPGA from testbench. 2023-10-13 14:08:17 -05:00
naichewa
d5d4f9d044 transferred spi changes in ECA-authorized commit 2023-10-12 13:36:57 -07:00
Lee Moore
0a0d6dd25e Merge branch 'openhwgroup:main' into main 2023-10-06 11:46:45 +01:00
Ross Thompson
fc83f33615 Oups. When fixing the linux-imperasdv testbench I accidentally introduced a bug to the tracer. 2023-10-05 13:00:46 -05:00
Ross Thompson
824f37bba4 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-10-05 10:39:06 -05:00
Ross Thompson
81c44a4cb3 Fixed imperas linux testbench. 2023-10-04 17:11:47 -05:00
David Harris
28752303be Added ZCA/ZCF/ZCD/ZCB support. Doesn't break regression, but not tested. Need to get tests for Zcb. Draft tests are in riscv-arch-test but not yet committed there 2023-10-04 12:28:12 -07:00
James E. Stine
58e7be2338 Fix testfloat testbench to work properly with parameters 2023-10-03 08:11:45 -05:00
eroom1966
381cfdcb4b bring upto date with latest IDV 2023-09-21 11:29:31 +01:00
Ross Thompson
271c7e43ab Merge pull request #403 from davidharrishmc/dev 
Initial TLB NAPOT tests
 2023-08-29 16:43:35 -05:00
David Harris
91429f3f02 Initial TLB NAPOT tests 2023-08-29 12:39:24 -07:00
Ross Thompson
ac0b1fbdb7 Fixed testbench_imperas.sv 2023-08-29 09:01:35 -05:00
David Harris
8d3ff59673 Completed basic tests of svnapot and svpbmt 2023-08-28 06:57:35 -07:00
David Harris
7a092a2275 Fixed merge conflict for ZICBOP 2023-08-25 18:41:57 -07:00
David Harris
c6631ef808 Added N and PBMT bits to MMU PTE 2023-08-24 19:44:46 -07:00
Ross Thompson
cd3349bd26 Added rv32 cboz test. 2023-08-24 17:02:53 -05:00
Ross Thompson
00e65c4ae7 Oups there was a bug in the SATP fix. RV32GC was broken by the changes. 2023-08-23 09:42:46 -05:00
David Harris
d801916d97 Merge pull request #383 from ross144/main 
Adds Zicbom support for D-cache only.  I-cache not yet supported.  Tests 32 and 64 bit versions.  Please rebuild regressions wally32 and wally64.  To save rebuild time edit lines 11-12 of tests/riscof/Makefile
 2023-08-21 13:32:00 -07:00
Ross Thompson
310b700550 Have a working 32 bit cbom test! 2023-08-21 13:46:09 -05:00
Ross Thompson
d4c6ba627d Working CBO tests for 64 bit! 2023-08-21 12:55:07 -05:00
David Harris
2738423441 Improved CSRU coverage with priv.S 2023-08-20 12:49:31 -07:00
Ross Thompson
a89a1e675c Merge branch 'boot' into mergeBoot 
Merges Jacob's new sdc controller into wally.
 2023-07-21 17:43:45 -05:00
Ross Thompson
e4d6a9f8c6 Removed all old configuration files. 2023-07-19 10:28:54 -05:00
Ross Thompson
b756b248b4 Wow. The newest version of Vivado does not like the enums as parameters. 
The solution is simple.  I changed the type to logic [31:0] and defined macros for the branch predictor types as 32 bit integers.
 2023-07-18 15:07:10 -05:00
Ross Thompson
59022099c7 Fixed the icache and dcache overlogging issue. 2023-07-14 15:47:05 -05:00
Ross Thompson
33d8e5687e Merge branch 'main' of github.com:ross144/cvw 2023-07-11 15:09:07 -05:00
Ross Thompson
99073a70c0 Added wfi and interrupt to tracer. 2023-07-11 15:09:04 -05:00
Ross Thompson
625192d9a4 Merge branch 'main' of github.com:ross144/cvw into main 2023-07-11 15:08:26 -05:00
Ross Thompson
38f32805ae Created separate temporary testbench for xcelium. 2023-07-11 15:07:33 -05:00
Ross Thompson
4653f8e704 Simplificaiton of function tracker. 2023-07-11 10:51:17 -05:00
Ross Thompson
27f6f00402 Changes for xcelium. 2023-07-07 18:22:28 -05:00
Ross Thompson
9a49ec0b98 Removed duplicate signal name from testbench. 2023-07-07 16:34:08 -05:00
Ross Thompson
2ce8b66574 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-07-06 14:55:43 -05:00
David Harris
b04763bcf2 Commented SVADU requirements for wally32priv mmu tests 2023-07-04 11:34:07 -07:00
David Harris
001d3cfdc5 Added logic to warn about x in memory reads. Added cbo instruction names to testbench decoder 2023-07-02 13:29:27 -07:00
James E. Stine
48bec40902 Modification (temporary) to testbench-fp.sv to allow testing of anything FMA. This might need to be changed with OpCtrl to make more robust for future expansion. 2023-06-29 08:46:11 -05:00
James E. Stine
3cfec29cc7 Minor tweak to fix vectors not working for fadd. 2023-06-26 14:25:44 -05:00
James E. Stine
786329b11d Fix items related to testing of TestFloat that were not always matching. The issue resulted due to the repeat statement that interferes with the always block. I separated the two to allow them to work correctly 2023-06-26 10:14:49 -05:00
James E. Stine
97b1c01dc0 Modify testbench-fp.sv to handle parameterization as well some other minor mods. Have to make a better FPUActive desgination but for now works 2023-06-22 15:27:17 -05:00
James E. Stine
66643eb78e Update sim-testfloat to fix errors due to bad config element. I am not sure of the reasoning, but the specific path to the testvector was not getting inserted in Questa. This modification also adds features to test individualized tests (.e.g, binary16 only) -- documentation is added in the FPbuild.txt file 2023-06-20 17:26:54 -05:00
Ross Thompson
a8f11dcad0 FPGA updates. 2023-06-20 11:11:34 -05:00
Ross Thompson
f5cee3fb66 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-06-18 16:37:19 -05:00
David Harris
5d6eb40c2d Fixed embench to run all tests, even ones not in 1.0 2023-06-17 20:38:51 -07:00
David Harris
2db94e7ddd Replaced zext.h with zext.h_64 in rv64 tests because old one is obsolete 2023-06-16 16:07:28 -07:00
Ross Thompson
443c568994 Vivado requires an intermediate wrapper file for parameterization. 2023-06-16 16:30:14 -05:00
David Harris
b1bfba7995 erge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-06-16 10:32:37 -07:00
David Harris
ea1f731cd5 Merge pull request #342 from ross144/main 
Testbench generates embench output files
 2023-06-16 10:32:18 -07:00
Ross Thompson
7f79c0a855 Modified the testbench to generate the required files for embench scripts. 2023-06-16 12:27:22 -05:00
David Harris
924a3ea3cf Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-06-16 10:03:48 -07:00
David Harris
ba2ee7453b Merge pull request #341 from ross144/main 
Fix embench so it does not crash
 2023-06-16 10:03:41 -07:00
Ross Thompson
4d76e83318 embench testbench no longer crashes. 2023-06-16 11:54:41 -05:00
David Harris
c2913f49a3 Added assertions for ZICNTR and ZIHPM 2023-06-16 09:26:02 -07:00
eroom1966
5f358d1af7 add changes for latest IDV file layout 2023-06-16 16:43:53 +01:00
Ross Thompson
d46500bfe0 Fixed the imperas testbench to work with parameters. 2023-06-16 08:59:52 -05:00
Ross Thompson
f3d35f914a Have the linux testbench working in the mean time. Before the consolidation. 2023-06-15 16:18:37 -05:00
Ross Thompson
4428babda9 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-06-15 15:38:38 -05:00
Ross Thompson
85567841eb Merge branch 'testbench-params2' 2023-06-15 15:31:13 -05:00
Ross Thompson
d2219023c3 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-06-15 14:57:23 -05:00
Ross Thompson
af046d4772 Major cleanup of testbench. 2023-06-15 14:57:05 -05:00
Ross Thompson
75b5c23edd Actually removed old `define configuration file for rv64gc. There were a lot of dangling problems. 2023-06-15 14:05:44 -05:00
Ross Thompson
b8a243827b Found a whole bunch of files still using the old `define configurations. 2023-06-15 13:09:07 -05:00
David Harris
45ee4c2f9f Added BMU instructions to instruction name decoder 2023-06-15 09:26:09 -07:00
Ross Thompson
301d54fea8 Significant refactoring of testbench. 2023-06-14 17:02:49 -05:00
Ross Thompson
4d2bb0ea83 Removed old configs from function name module. 2023-06-14 16:35:55 -05:00
Ross Thompson
8f09e17dc7 Found and fixed the source of the new testbench slow down. I accidentally increased the size of the signature buffer by 10x. 2023-06-14 14:11:25 -05:00
Ross Thompson
6330e8084c more testbench improvements. 2023-06-14 12:23:26 -05:00
Ross Thompson
6e42b9f865 Continued improvements to testbench. 2023-06-14 12:11:55 -05:00
Ross Thompson
10c6c08136 Resolved the duplicated check signature issue. 2023-06-14 11:50:12 -05:00
Ross Thompson
3a78d4ca73 Fixed another issue with the timing of memory resets in the new testbench. 2023-06-13 16:24:38 -05:00
Ross Thompson
af8ca85a5b Now have most of the regression tests running again. 2023-06-13 15:09:40 -05:00
Ross Thompson
836bc4a4f7 Cleaned up testbench more. 2023-06-13 14:05:17 -05:00
Ross Thompson
4bdecf8c6d Compacted memory resets. 2023-06-13 13:57:58 -05:00
Ross Thompson
91a22c3a8a More cleanup. 2023-06-13 13:54:07 -05:00
Ross Thompson
9869b26556 Fixed the multliple reads of the same preload memory file. 2023-06-13 13:52:02 -05:00
Ross Thompson
df62f3964c The testbench now at least runs the arch64i in rv64gc config. Still has several issues 
1. need to remove all dead code
2. seems to still be double reading memory files sometimes.
3. batch mode does not work.
 2023-06-13 13:18:46 -05:00
David Harris
004aeda362 Revert "Update for new layout of ImperasDV files" 2023-06-13 04:17:56 -07:00
Ross Thompson
fe72264de3 The new testbench is almost working except the shadow copy is not working. 2023-06-12 15:08:23 -05:00
Ross Thompson
9eeac21113 Progress towards new testbench. 2023-06-12 14:06:17 -05:00
Ross Thompson
3ef2031791 Created temporary wrapper for lint. 2023-06-12 11:49:51 -05:00
Ross Thompson
ee4352975c This parameterizes the testbench but does not use the verilator updates or the new testbench. 2023-06-12 11:00:30 -05:00
eroom1966
d61ed17730 Update for new layout of ImperasDV files 2023-06-12 09:29:07 +01:00
Ross Thompson
8d1dee5764 Removed comments around commented code for verilator. 2023-06-11 15:30:51 -05:00
Ross Thompson
e27dfb8ce0 Merge branch 'verilator' 2023-06-11 15:28:04 -05:00
James E. Stine
67d21ae3a6 Update testbench-fp thanks to Kevin's help - also fixed add which was broken due to config 2023-06-11 15:15:47 -05:00
David Harris
f68b9c224a Fixed WALLY-trap test case to use menvcfg 2023-06-09 15:24:26 -07:00
Ross Thompson
39c8f11191 Fixed the garbled output in embench transcript. 2023-06-08 10:43:46 -05:00
Ross Thompson
4ddbbd6948 Merge pull request #314 from davidharrishmc/dev 
Make and FP script improvements
 2023-06-06 12:38:26 -04:00
Ross Thompson
918464c236 Found the coremark performance issue. The testbench was continuously forcing the BTB to all zeros. Once fixed it resolved the performance problem. 2023-06-05 15:42:05 -05:00
Ross Thompson
1ceea51d8b Changes required to make verilator compile wally's testbench to c++. Not actually tested in simulation yet. 2023-05-31 16:51:00 -05:00
David Harris
65dd99af0c Support all testfloat tests with parameterized design 2023-05-31 06:30:21 -07:00
Ross Thompson
8648d0c25c Hacked it together, but I think testfloat is working. 2023-05-30 15:51:13 -05:00
Ross Thompson
04d0fd94f0 Merge branch 'param-lim-merge' 2023-05-26 16:25:35 -05:00
Ross Thompson
88cc473c68 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-05-24 13:00:50 -05:00
Ross Thompson
930fb67308 Trying to figure out why the parameterization slowed down modelsim so much. 2023-05-24 12:44:42 -05:00
Ross Thompson
2ddb8c7c78 Merge pull request #297 from davidharrishmc/dev 
Verilator testbench changes
 2023-05-22 13:29:54 -04:00
David Harris
163b05f1ce Removed force from branch predictor initialization 2023-05-22 09:57:41 -07:00
David Harris
84dac82def Initial testbench cleanup for Verilator 2023-05-22 09:51:46 -07:00
Ross Thompson
664231c0da Merge branch 'localhistory' 
Repair to wave file.
Created implementations of local history. Part of my Ph.D. research.
 2023-05-22 10:13:31 -05:00
David Harris
7b0d1a7883 Factored FMA tests out of the main 32/64 f/d tests to run in parallel and speed up sim 2023-05-16 11:37:01 -07:00
Ross Thompson
3a98fb8680 Baseline localhistory with speculative repair built. 2023-05-05 15:23:45 -05:00
Ross Thompson
8b0791b6b5 I think ahead pipelining is working for local history. 2023-05-03 12:52:32 -05:00
Ross Thompson
0904a9b97f Swapped the m and k parameters for local history predictor. 2023-05-02 10:52:41 -05:00
Kevin Wan
9ca738547e fixed tests.vh test lines 2023-04-28 07:47:59 -07:00
Kevin Wan
39c9cd5ee9 added tests for pmppriority module 2023-04-27 16:12:43 -07:00
Noah Limpert
4ec31de316 complete camline coverage on IFU and LSU 2023-04-27 14:26:10 -07:00
Noah Limpert
a0e71c26cb Add in a test that makes match 3 = 0 for all tlb lines 2023-04-20 14:50:06 -07:00
Noah Limpert
7ca44de126 Commiting changes to add coverage to ASID, Global, Megapage size checks. 2023-04-20 14:38:13 -07:00
David Harris
6e612a1693 Update tests.vh 
Missing comma from merge
 2023-04-19 06:23:05 -07:00
David Harris
4cbffd7972 Merge branch 'main' into coverage4 2023-04-19 06:16:07 -07:00
David Harris
b63dff098a Merge branch 'main' into main 2023-04-19 04:50:12 -07:00
David Harris
156a098884 Merge branch 'main' into main 2023-04-19 04:46:51 -07:00
Alec Vercruysse
b3a3af8ed3 add D$ test case to trigger a FlushStage while SetDirtyWay=1 
This hits some conditional coverage in each cacheway.
A cache store hit happens at the same time as a StoreAmoMisalignedFault.
 2023-04-19 01:34:01 -07:00
Alec Vercruysse
cd803bfa44 Cover CacheWay edge case: CacheDataMem we=1 while ce=0. 
This test basically triggers an i$ miss during a d$ (hit) store
operation. It requires some tricky timing (e.g. a flushD right
before the relevant store). I use a script to generate the test.
 2023-04-19 01:34:01 -07:00
Liam
9b72d6ac37 Update tests.vh 2023-04-18 23:15:47 -07:00
Kevin Wan
771124e265 Completely covers all PMPCFG_ARRAY_REGW cases 2023-04-18 21:50:48 -07:00
Kevin Wan
1bdae2285d PMPCFG_ARRAY_REGW cases 2023-04-18 18:43:50 -07:00
Kevin Thomas
db0ca8695a Add PR#252 test file to coverage 2023-04-18 17:57:56 -05:00
Limnanthes Serafini
2d9de7b58f Merge branch 'openhwgroup:main' into code_quality 2023-04-13 19:59:58 -07:00
Limnanthes Serafini
ff72cbc1b2 Finished up testbench reformatting 2023-04-13 19:18:26 -07:00
Limnanthes Serafini
b9c97c6a8c Further indents 2023-04-13 19:07:43 -07:00
Limnanthes Serafini
44356559bc testbench code visual improvements 2023-04-13 19:06:09 -07:00