Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-03 10:15:19 +00:00
Code Issues Packages Projects Releases Wiki Activity

Merge pull request #297 from davidharrishmc/dev

Browse Source 
Verilator testbench changes
This commit is contained in:
Ross Thompson 2023-05-22 13:29:54 -04:00 committed by GitHub
commit 2ddb8c7c78
1 changed files with 14 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

36
testbench/testbench.sv
View File

@ -256,7 +256,7 @@ module testbench;
$readmemh(romfilename, dut.uncore.uncore.bootrom.bootrom.memory.ROM);
$readmemh(sdcfilename, sdcard.sdcard.FLASHmem);
// force sdc timers
force dut.uncore.uncore.sdc.SDC.LimitTimers = 1;
dut.uncore.uncore.sdc.SDC.LimitTimers = 1;
end else begin
if (`IROM_SUPPORTED) $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
else if (`BUS_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
@ -324,10 +324,10 @@ module testbench;
$display("Embench Benchmark: %s is done.", tests[test]);
if (riscofTest) outputfile = {pathname, tests[test], "/ref/ref.sim.output"};
else outputfile = {pathname, tests[test], ".sim.output"};
outputFilePointer = $fopen(outputfile);
outputFilePointer = $fopen(outputfile, "w");
i = 0;
while ($unsigned(i) < $unsigned(5'd5)) begin
$fdisplayh(outputFilePointer, DCacheFlushFSM.ShadowRAM[testadr+i]);
$fdisplay("%x %s", outputFilePointer, DCacheFlushFSM.ShadowRAM[testadr+i]);
i = i + 1;
end
$fclose(outputFilePointer);
@ -540,23 +540,15 @@ module testbench;
if (`BPRED_SUPPORTED) begin
integer adrindex;
always @(*) begin
if(reset) begin
for(adrindex = 0; adrindex < 2**`BTB_SIZE; adrindex++) begin
force dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0;
// initialize branch predictor on reset
always @(posedge reset) begin
for(adrindex = 0; adrindex < 2**`BTB_SIZE; adrindex++) begin
dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0;
end
for(adrindex = 0; adrindex < 2**`BPRED_SIZE; adrindex++) begin
force dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0;
dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0;
end
#1;
for(adrindex = 0; adrindex < 2**`BTB_SIZE; adrindex++) begin
release dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex];
end
for(adrindex = 0; adrindex < 2**`BPRED_SIZE; adrindex++) begin
release dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex];
end
end
end
end
end
@ -578,7 +570,7 @@ module testbench;
assign InvalEdge = dut.core.ifu.InvalidateICacheM & ~InvalDelayed;
initial begin
LogFile = $psprintf("ICache.log");
LogFile = "ICache.log";
file = $fopen(LogFile, "w");
$fwrite(file, "BEGIN %s\n", memfilename);
end
@ -621,7 +613,7 @@ module testbench;
(AccessTypeString != "NULL");
initial begin
LogFile = $psprintf("DCache.log");
LogFile = "DCache.log";
file = $fopen(LogFile, "w");
$fwrite(file, "BEGIN %s\n", memfilename);
end
@ -647,7 +639,8 @@ module testbench;
flop #(1) ResetDReg(clk, reset, resetD);
assign resetEdge = ~reset & resetD;
initial begin
LogFile = $psprintf("branch_%s%0d.log", `BPRED_TYPE, `BPRED_SIZE);
LogFile = "branch.log"; // will break some of Ross's research analysis scripts
//LogFile = $psprintf("branch_%s%0d.log", `BPRED_TYPE, `BPRED_SIZE);
file = $fopen(LogFile, "w");
end
always @(posedge clk) begin
@ -746,8 +739,7 @@ module DCacheFlushFSM
integer i, j, k, l;
always @(posedge clk) begin
if (start) begin #1
#1
if (start) begin
for(i = 0; i < numlines; i++) begin
for(j = 0; j < numways; j++) begin
for(l = 0; l < cachesramwords; l++) begin