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Use riscv-arch-test arch32e instead of outdated wally-riscv-arch-test wally32e

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This commit is contained in:
David Harris 2023-12-15 05:05:53 -08:00
parent 51b43bffa3
commit 38f4d9baf8
6 changed files with 103 additions and 71 deletions
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2
sim/regression-wally
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@ -107,7 +107,7 @@ for test in tests32i:
configs.append(tc)
tests32e = ["wally32e"]
tests32e = ["arch32e"]
for test in tests32e:
tc = TestCase(
name=test,

79
testbench/testbench.sv
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@ -93,33 +93,33 @@ module testbench;
//tests = '{};
if (P.XLEN == 64) begin // RV64
case (TEST)
"arch64i": tests = arch64i;
"arch64priv": tests = arch64priv;
"arch64i": tests = arch64i;
"arch64priv": tests = arch64priv;
"arch64c": if (P.C_SUPPORTED)
if (P.ZICSR_SUPPORTED) tests = {arch64c, arch64cpriv};
else tests = {arch64c};
else tests = {arch64c};
"arch64m": if (P.M_SUPPORTED) tests = arch64m;
"arch64a": if (P.A_SUPPORTED) tests = arch64a;
"arch64f": if (P.F_SUPPORTED) tests = arch64f;
"arch64d": if (P.D_SUPPORTED) tests = arch64d;
"arch64f_fma": if (P.F_SUPPORTED) tests = arch64f_fma;
"arch64d_fma": if (P.D_SUPPORTED) tests = arch64d_fma;
"arch64f_fma": if (P.F_SUPPORTED) tests = arch64f_fma;
"arch64d_fma": if (P.D_SUPPORTED) tests = arch64d_fma;
"arch64zi": if (P.ZIFENCEI_SUPPORTED) tests = arch64zi;
"imperas64i": tests = imperas64i;
"imperas64i": tests = imperas64i;
"imperas64f": if (P.F_SUPPORTED) tests = imperas64f;
"imperas64d": if (P.D_SUPPORTED) tests = imperas64d;
"imperas64m": if (P.M_SUPPORTED) tests = imperas64m;
"wally64a": if (P.A_SUPPORTED) tests = wally64a;
"imperas64c": if (P.C_SUPPORTED) tests = imperas64c;
else tests = imperas64iNOc;
"custom": tests = custom;
"wally64i": tests = wally64i;
"wally64priv": tests = wally64priv;
"wally64periph": tests = wally64periph;
"coremark": tests = coremark;
"fpga": tests = fpga;
"ahb" : tests = ahb;
"coverage64gc" : tests = coverage64gc;
else tests = imperas64iNOc;
"custom": tests = custom;
"wally64i": tests = wally64i;
"wally64priv": tests = wally64priv;
"wally64periph": tests = wally64periph;
"coremark": tests = coremark;
"fpga": tests = fpga;
"ahb" : tests = ahb;
"coverage64gc" : tests = coverage64gc;
"arch64zba": if (P.ZBA_SUPPORTED) tests = arch64zba;
"arch64zbb": if (P.ZBB_SUPPORTED) tests = arch64zbb;
"arch64zbc": if (P.ZBC_SUPPORTED) tests = arch64zbc;
@ -127,30 +127,30 @@ module testbench;
endcase
end else begin // RV32
case (TEST)
"arch32i": tests = arch32i;
"arch32priv": tests = arch32priv;
"arch32e": tests = arch32e;
"arch32i": tests = arch32i;
"arch32priv": tests = arch32priv;
"arch32c": if (P.C_SUPPORTED)
if (P.ZICSR_SUPPORTED) tests = {arch32c, arch32cpriv};
else tests = {arch32c};
else tests = {arch32c};
"arch32m": if (P.M_SUPPORTED) tests = arch32m;
"arch32a": if (P.A_SUPPORTED) tests = arch32a;
"arch32f": if (P.F_SUPPORTED) tests = arch32f;
"arch32d": if (P.D_SUPPORTED) tests = arch32d;
"arch32f_fma": if (P.F_SUPPORTED) tests = arch32f_fma;
"arch32d_fma": if (P.D_SUPPORTED) tests = arch32d_fma;
"arch32f_fma": if (P.F_SUPPORTED) tests = arch32f_fma;
"arch32d_fma": if (P.D_SUPPORTED) tests = arch32d_fma;
"arch32zi": if (P.ZIFENCEI_SUPPORTED) tests = arch32zi;
"imperas32i": tests = imperas32i;
"imperas32i": tests = imperas32i;
"imperas32f": if (P.F_SUPPORTED) tests = imperas32f;
"imperas32m": if (P.M_SUPPORTED) tests = imperas32m;
"wally32a": if (P.A_SUPPORTED) tests = wally32a;
"imperas32c": if (P.C_SUPPORTED) tests = imperas32c;
else tests = imperas32iNOc;
"wally32i": tests = wally32i;
"wally32e": tests = wally32e;
"wally32priv": tests = wally32priv;
"wally32periph": tests = wally32periph;
"embench": tests = embench;
"coremark": tests = coremark;
else tests = imperas32iNOc;
"wally32i": tests = wally32i;
"wally32priv": tests = wally32priv;
"wally32periph": tests = wally32periph;
"embench": tests = embench;
"coremark": tests = coremark;
"arch32zba": if (P.ZBA_SUPPORTED) tests = arch32zba;
"arch32zbb": if (P.ZBB_SUPPORTED) tests = arch32zbb;
"arch32zbc": if (P.ZBC_SUPPORTED) tests = arch32zbc;
@ -321,6 +321,28 @@ module testbench;
// Some memories are not reset, but should be zeros or set to some initial value for simulation
////////////////////////////////////////////////////////////////////////////////
integer adrindex;
if (P.UNCORE_RAM_SUPPORTED)
always @(posedge clk)
if (ResetMem) // program memory is sometimes reset
for (adrindex=0; adrindex<(P.UNCORE_RAM_RANGE>>1+(P.XLEN/32)); adrindex = adrindex+1)
dut.uncore.uncore.ram.ram.memory.RAM[adrindex] = '0;
if (P.BPRED_SUPPORTED)
always @(posedge clk)
if(reset) begin // branch predictor must always be reset
for(adrindex = 0; adrindex < 2**P.BTB_SIZE; adrindex++)
dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0;
for(adrindex = 0; adrindex < 2**P.BPRED_SIZE; adrindex++)
dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0;
end
if (P.BPRED_SUPPORTED & (P.BPRED_TYPE == `BP_LOCAL_AHEAD | P.BPRED_TYPE == `BP_LOCAL_REPAIR)) // local history only
always @(posedge clk)
if(reset) // branch predictor must always be reset
for(adrindex = 0; adrindex < 2**P.BPRED_NUM_LHR; adrindex++)
dut.core.ifu.bpred.bpred.Predictor.DirPredictor.BHT.mem[adrindex] = 0;
/*
always @(posedge clk) begin
if (ResetMem) // program memory is sometimes reset
if (P.UNCORE_RAM_SUPPORTED)
@ -339,6 +361,7 @@ module testbench;
end
end
end
*/
////////////////////////////////////////////////////////////////////////////////
// load memories with program image

81
testbench/tests.vh
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@ -1961,6 +1961,46 @@ string arch64zbs[] = '{
"rv32i_m/I/src/xori-01.S"
};
string arch32e[] = '{
`RISCVARCHTEST,
"rv32e_unratified/E/src/add-01.S",
"rv32e_unratified/E/src/addi-01.S",
"rv32e_unratified/E/src/and-01.S",
"rv32e_unratified/E/src/andi-01.S",
"rv32e_unratified/E/src/auipc-01.S",
"rv32e_unratified/E/src/bge-01.S",
"rv32e_unratified/E/src/bgeu-01.S",
"rv32e_unratified/E/src/blt-01.S",
"rv32e_unratified/E/src/bltu-01.S",
"rv32e_unratified/E/src/bne-01.S",
"rv32e_unratified/E/src/jal-01.S",
"rv32e_unratified/E/src/jalr-01.S",
"rv32e_unratified/E/src/lb-align-01.S",
"rv32e_unratified/E/src/lbu-align-01.S",
"rv32e_unratified/E/src/lh-align-01.S",
"rv32e_unratified/E/src/lhu-align-01.S",
"rv32e_unratified/E/src/lui-01.S",
"rv32e_unratified/E/src/lw-align-01.S",
"rv32e_unratified/E/src/or-01.S",
"rv32e_unratified/E/src/ori-01.S",
"rv32e_unratified/E/src/sb-align-01.S",
"rv32e_unratified/E/src/sh-align-01.S",
"rv32e_unratified/E/src/sll-01.S",
"rv32e_unratified/E/src/slli-01.S",
"rv32e_unratified/E/src/slt-01.S",
"rv32e_unratified/E/src/slti-01.S",
"rv32e_unratified/E/src/sltiu-01.S",
"rv32e_unratified/E/src/sltu-01.S",
"rv32e_unratified/E/src/sra-01.S",
"rv32e_unratified/E/src/srai-01.S",
"rv32e_unratified/E/src/srl-01.S",
"rv32e_unratified/E/src/srli-01.S",
"rv32e_unratified/E/src/sub-01.S",
"rv32e_unratified/E/src/sw-align-01.S",
"rv32e_unratified/E/src/xor-01.S",
"rv32e_unratified/E/src/xori-01.S"
};
string wally64i[] = '{
`WALLYTEST,
"rv64i_m/I/src/WALLY-ADD.S",
@ -2017,46 +2057,6 @@ string arch64zbs[] = '{
"rv64i_m/privilege/src/WALLY-spi-01.S"
};
string wally32e[] = '{
`WALLYTEST,
"rv32i_m/I/src/E-add-01.S",
"rv32i_m/I/src/E-addi-01.S",
"rv32i_m/I/src/E-and-01.S",
"rv32i_m/I/src/E-andi-01.S",
"rv32i_m/I/src/E-auipc-01.S",
"rv32i_m/I/src/E-bge-01.S",
"rv32i_m/I/src/E-bgeu-01.S",
"rv32i_m/I/src/E-blt-01.S",
"rv32i_m/I/src/E-bltu-01.S",
"rv32i_m/I/src/E-bne-01.S",
"rv32i_m/I/src/E-jal-01.S",
"rv32i_m/I/src/E-jalr-01.S",
"rv32i_m/I/src/E-lb-align-01.S",
"rv32i_m/I/src/E-lbu-align-01.S",
"rv32i_m/I/src/E-lh-align-01.S",
"rv32i_m/I/src/E-lhu-align-01.S",
"rv32i_m/I/src/E-lui-01.S",
"rv32i_m/I/src/E-lw-align-01.S",
"rv32i_m/I/src/E-or-01.S",
"rv32i_m/I/src/E-ori-01.S",
"rv32i_m/I/src/E-sb-align-01.S",
"rv32i_m/I/src/E-sh-align-01.S",
"rv32i_m/I/src/E-sll-01.S",
"rv32i_m/I/src/E-slli-01.S",
"rv32i_m/I/src/E-slt-01.S",
"rv32i_m/I/src/E-slti-01.S",
"rv32i_m/I/src/E-sltiu-01.S",
"rv32i_m/I/src/E-sltu-01.S",
"rv32i_m/I/src/E-sra-01.S",
"rv32i_m/I/src/E-srai-01.S",
"rv32i_m/I/src/E-srl-01.S",
"rv32i_m/I/src/E-srli-01.S",
"rv32i_m/I/src/E-sub-01.S",
"rv32i_m/I/src/E-sw-align-01.S",
"rv32i_m/I/src/E-xor-01.S",
"rv32i_m/I/src/E-xori-01.S"
};
string wally32i[] = '{
`WALLYTEST,
"rv32i_m/I/src/WALLY-ADD.S",
@ -2102,7 +2102,6 @@ string arch64zbs[] = '{
"rv32i_m/privilege/src/WALLY-plic-01.S",
"rv32i_m/privilege/src/WALLY-plic-s-01.S",
"rv32i_m/privilege/src/WALLY-spi-01.S"
};
string wally32periph[] = '{

8
tests/riscof/Makefile
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@ -8,7 +8,7 @@ wally_workdir = $(work)/wally-riscv-arch-test
current_dir = $(shell pwd)
#XLEN ?= 64
all: root arch32 wally32 wally32e arch64 wally64
all: root arch32 wally32 arch32e arch64 wally64
wally-riscv-arch-test: root wally32 wally64
root:
@ -20,10 +20,16 @@ root:
sed 's,{0},$(current_dir),g;s,{1},64gc,g' config.ini > config64.ini
sed 's,{0},$(current_dir),g;s,{1},32e,g' config.ini > config32e.ini
arch32e:
riscof run --work-dir=$(work_dir) --config=config32e.ini --suite=$(arch_dir)/riscv-test-suite/ --env=$(arch_dir)/riscv-test-suite/env --no-browser
rsync -a $(work_dir)/rv32i_m/ $(arch_workdir)/rv32i_m/ || echo "error suppressed"
rsync -a $(work_dir)/rv32e_unratified/ $(arch_workdir)/rv32e_unratified/ || echo "error suppressed"
arch32:
riscof run --work-dir=$(work_dir) --config=config32.ini --suite=$(arch_dir)/riscv-test-suite/ --env=$(arch_dir)/riscv-test-suite/env --no-browser
rsync -a $(work_dir)/rv32i_m/ $(arch_workdir)/rv32i_m/ || echo "error suppressed"
arch64:
riscof run --work-dir=$(work_dir) --config=config64.ini --suite=$(arch_dir)/riscv-test-suite/ --env=$(arch_dir)/riscv-test-suite/env --no-browser
rsync -a $(work_dir)/rv64i_m/ $(arch_workdir)/rv64i_m/ || echo "error suppressed"

2
tests/riscof/sail_cSim/riscof_sail_cSim.py
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@ -55,6 +55,8 @@ class sail_cSim(pluginTemplate):
self.compile_cmd = self.compile_cmd+' -mabi='+('lp64 ' if 64 in ispec['supported_xlen'] else ('ilp32e ' if "E" in ispec["ISA"] else 'ilp32 '))
if "I" in ispec["ISA"]:
self.isa += 'i'
if "E" in ispec["ISA"]:
self.isa += 'e'
if "M" in ispec["ISA"]:
self.isa += 'm'
if "A" in ispec["ISA"]:

2
tests/riscof/spike/riscof_spike.py
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@ -97,6 +97,8 @@ class spike(pluginTemplate):
self.isa = 'rv' + self.xlen
if "I" in ispec["ISA"]:
self.isa += 'i'
if "E" in ispec["ISA"]:
self.isa += 'e'
if "M" in ispec["ISA"]:
self.isa += 'm'
if "A" in ispec["ISA"]: