David Harris 6cb4a9e905 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev		2023-12-15 19:27:10 -08:00
..
common	Fixed Linux makefile; load branch predictor RAMs at startup for sim; fixed comment in trap; starting to make testbench more compatible with Verilator	2023-12-13 11:33:59 -08:00
fp	Removed pipelined level of hierarchy	2023-02-02 14:14:11 -08:00
sdc	Towards removing the FPGA config file.	2023-11-13 17:20:26 -06:00
testbench-fp.sv	Fix to take care of Issue #507. Issue was caused with time delay in testbench-fp.sv that interfered with the if statement in the DIVSQRT condition for generating a vector. This original time delay was given to guarantee that the previous operation would complete. However, the testbench was modified to make sure this would not happen and this time delay is not needed obviating any issue that caused Issue #507. Some other small enhancements were made to the testbench-fp.sv for beautification, as well. A full test was run on the testbench to check its validity.	2023-12-15 17:02:11 -06:00
testbench-imperas.sv	Added SPI support to Imperas testbenches	2023-12-07 09:44:31 -08:00
testbench-linux-imperas.sv	Added SPI support to Imperas testbenches	2023-12-07 09:44:31 -08:00
testbench-linux.sv	Testbench fixes to add SPI and make string pp static in testbench.fp to solve compiler issue	2023-11-04 20:36:05 -07:00
testbench-xcelium.sv	Testbench fixes to add SPI and make string pp static in testbench.fp to solve compiler issue	2023-11-04 20:36:05 -07:00
testbench.sv	Use riscv-arch-test arch32e instead of outdated wally-riscv-arch-test wally32e	2023-12-15 05:05:53 -08:00
tests-fp.vh	Update testbench-fp to run TestFloat for all FP operations	2023-04-11 22:16:20 -05:00
tests.vh	Switched to using riscv-arch-test rv32e_m suite. Need to rename it from rv32e_unratified (PR pending)	2023-12-15 19:26:50 -08:00
wallywrapper.sv	Verilator improvements	2023-11-04 03:21:07 -07:00