Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-02 17:55:19 +00:00
Code Issues Packages Projects Releases Wiki Activity

Switched to using riscv-arch-test rv32e_m suite. Need to rename it from rv32e_unratified (PR pending)

Browse Source
This commit is contained in:
David Harris 2023-12-15 19:26:50 -08:00
parent 38f4d9baf8
commit a138ef37b1
40 changed files with 42 additions and 51283 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

72
testbench/tests.vh
View File

@ -1963,42 +1963,42 @@ string arch64zbs[] = '{
string arch32e[] = '{
`RISCVARCHTEST,
"rv32e_unratified/E/src/add-01.S",
"rv32e_unratified/E/src/addi-01.S",
"rv32e_unratified/E/src/and-01.S",
"rv32e_unratified/E/src/andi-01.S",
"rv32e_unratified/E/src/auipc-01.S",
"rv32e_unratified/E/src/bge-01.S",
"rv32e_unratified/E/src/bgeu-01.S",
"rv32e_unratified/E/src/blt-01.S",
"rv32e_unratified/E/src/bltu-01.S",
"rv32e_unratified/E/src/bne-01.S",
"rv32e_unratified/E/src/jal-01.S",
"rv32e_unratified/E/src/jalr-01.S",
"rv32e_unratified/E/src/lb-align-01.S",
"rv32e_unratified/E/src/lbu-align-01.S",
"rv32e_unratified/E/src/lh-align-01.S",
"rv32e_unratified/E/src/lhu-align-01.S",
"rv32e_unratified/E/src/lui-01.S",
"rv32e_unratified/E/src/lw-align-01.S",
"rv32e_unratified/E/src/or-01.S",
"rv32e_unratified/E/src/ori-01.S",
"rv32e_unratified/E/src/sb-align-01.S",
"rv32e_unratified/E/src/sh-align-01.S",
"rv32e_unratified/E/src/sll-01.S",
"rv32e_unratified/E/src/slli-01.S",
"rv32e_unratified/E/src/slt-01.S",
"rv32e_unratified/E/src/slti-01.S",
"rv32e_unratified/E/src/sltiu-01.S",
"rv32e_unratified/E/src/sltu-01.S",
"rv32e_unratified/E/src/sra-01.S",
"rv32e_unratified/E/src/srai-01.S",
"rv32e_unratified/E/src/srl-01.S",
"rv32e_unratified/E/src/srli-01.S",
"rv32e_unratified/E/src/sub-01.S",
"rv32e_unratified/E/src/sw-align-01.S",
"rv32e_unratified/E/src/xor-01.S",
"rv32e_unratified/E/src/xori-01.S"
"rv32e_m/E/src/add-01.S",
"rv32e_m/E/src/addi-01.S",
"rv32e_m/E/src/and-01.S",
"rv32e_m/E/src/andi-01.S",
"rv32e_m/E/src/auipc-01.S",
"rv32e_m/E/src/bge-01.S",
"rv32e_m/E/src/bgeu-01.S",
"rv32e_m/E/src/blt-01.S",
"rv32e_m/E/src/bltu-01.S",
"rv32e_m/E/src/bne-01.S",
"rv32e_m/E/src/jal-01.S",
"rv32e_m/E/src/jalr-01.S",
"rv32e_m/E/src/lb-align-01.S",
"rv32e_m/E/src/lbu-align-01.S",
"rv32e_m/E/src/lh-align-01.S",
"rv32e_m/E/src/lhu-align-01.S",
"rv32e_m/E/src/lui-01.S",
"rv32e_m/E/src/lw-align-01.S",
"rv32e_m/E/src/or-01.S",
"rv32e_m/E/src/ori-01.S",
"rv32e_m/E/src/sb-align-01.S",
"rv32e_m/E/src/sh-align-01.S",
"rv32e_m/E/src/sll-01.S",
"rv32e_m/E/src/slli-01.S",
"rv32e_m/E/src/slt-01.S",
"rv32e_m/E/src/slti-01.S",
"rv32e_m/E/src/sltiu-01.S",
"rv32e_m/E/src/sltu-01.S",
"rv32e_m/E/src/sra-01.S",
"rv32e_m/E/src/srai-01.S",
"rv32e_m/E/src/srl-01.S",
"rv32e_m/E/src/srli-01.S",
"rv32e_m/E/src/sub-01.S",
"rv32e_m/E/src/sw-align-01.S",
"rv32e_m/E/src/xor-01.S",
"rv32e_m/E/src/xori-01.S"
};
string wally64i[] = '{

13
tests/riscof/Makefile
View File

@ -8,7 +8,7 @@ wally_workdir = $(work)/wally-riscv-arch-test
current_dir = $(shell pwd)
#XLEN ?= 64
all: root arch32 wally32 arch32e arch64 wally64
all: root arch32e arch32 wally32 arch64 wally64
wally-riscv-arch-test: root wally32 wally64
root:
@ -22,8 +22,7 @@ root:
arch32e:
riscof run --work-dir=$(work_dir) --config=config32e.ini --suite=$(arch_dir)/riscv-test-suite/ --env=$(arch_dir)/riscv-test-suite/env --no-browser
rsync -a $(work_dir)/rv32i_m/ $(arch_workdir)/rv32i_m/ || echo "error suppressed"
rsync -a $(work_dir)/rv32e_unratified/ $(arch_workdir)/rv32e_unratified/ || echo "error suppressed"
rsync -a $(work_dir)/rv32e_m/ $(arch_workdir)/rv32e_m/ || echo "error suppressed"
arch32:
riscof run --work-dir=$(work_dir) --config=config32.ini --suite=$(arch_dir)/riscv-test-suite/ --env=$(arch_dir)/riscv-test-suite/env --no-browser
@ -44,10 +43,10 @@ wally64:
riscof run --work-dir=$(work_dir) --config=config64.ini --suite=$(wally_dir)/riscv-test-suite/ --env=$(wally_dir)/riscv-test-suite/env --no-browser --no-dut-run
rsync -a $(work_dir)/rv64i_m/ $(wally_workdir)/rv64i_m/ || echo "error suppressed"
wally32e:
riscof run --work-dir=$(work_dir) --config=config32e.ini --suite=$(wally_dir)/riscv-test-suite/ --env=$(wally_dir)/riscv-test-suite/env --no-browser --no-dut-run
rsync -a $(work_dir)/rv32i_m/ $(wally_workdir)/rv32i_m/ || echo "error suppressed"
rsync -a $(work_dir)/rv32e_unratified/ $(wally_workdir)/rv32e_unratified/ || echo "error suppressed"
#wally32e:
# riscof run --work-dir=$(work_dir) --config=config32e.ini --suite=$(wally_dir)/riscv-test-suite/ --env=$(wally_dir)/riscv-test-suite/env --no-browser --no-dut-run
# rsync -a $(work_dir)/rv32i_m/ $(wally_workdir)/rv32i_m/ || echo "error suppressed"
# rsync -a $(work_dir)/rv32e_unratified/ $(wally_workdir)/rv32e_unratified/ || echo "error suppressed"
memfile:

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/Makefile
View File

@ -1,3 +0,0 @@
include ../../Makefile.include
$(eval $(call compile_template,-march=rv32ec -mabi=ilp32e -DXLEN=$(XLEN)))

61
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/Makefrag
View File

@ -1,61 +0,0 @@
# RISC-V Architecture Test RV32E Makefrag
#
# Copyright (c) 2017, Codasip Ltd.
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
# * Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# * Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# * Neither the name of the Codasip Ltd. nor the
# names of its contributors may be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd. BE LIABLE FOR ANY
# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Description: Makefrag for RV32E architectural tests
rv32e_sc_tests = \
cadd-01 \
caddi-01 \
caddi16sp-01 \
caddi4spn-01 \
cand-01 \
candi-01 \
cbeqz-01 \
cbnez-01 \
cj-01 \
cjal-01 \
cjalr-01 \
cjr-01 \
cli-01 \
clui-01 \
clw-01 \
clwsp-01 \
cmv-01 \
cnop-01 \
cor-01 \
cslli-01 \
csrai-01 \
csrli-01 \
csub-01 \
csw-01 \
cswsp-01 \
cxor-01
rv32e_tests = $(addsuffix .elf, $(rv32e_sc_tests))
target_tests += $(rv32e_tests)

2980
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cadd-01.S
View File

File diff suppressed because it is too large Load Diff

1950
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/caddi-01.S
View File

File diff suppressed because it is too large Load Diff

430
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/caddi16sp-01.S
View File

@ -1,430 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Wed Aug 4 06:39:00 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.addi16sp instruction of the RISC-V C extension for the caddi16sp covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32EC")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",caddi16sp)
RVTEST_SIGBASE( x1,signature_x1_1)
inst_0:
// rd==x2, imm_val == -512, rs1_val == 4194304, rs1_val != imm_val, rs1_val > 0 and imm_val < 0
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x400000; immval:-0x200
TEST_CI_OP( c.addi16sp, x2, 0x3ffe00, 0x400000, -0x200, x1, 0, x3)
inst_1:
// rs1_val == 2147483647, imm_val == 128, rs1_val > 0 and imm_val > 0, rs1_val == (2**(xlen-1)-1)
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x7fffffff; immval:0x80
TEST_CI_OP( c.addi16sp, x2, 0x8000007f, 0x7fffffff, 0x80, x1, 4, x3)
inst_2:
// rs1_val == -1073741825, rs1_val < 0 and imm_val > 0
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x40000001; immval:0x60
TEST_CI_OP( c.addi16sp, x2, 0xc000005f, -0x40000001, 0x60, x1, 8, x3)
inst_3:
// rs1_val == -536870913, rs1_val < 0 and imm_val < 0
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x20000001; immval:-0x60
TEST_CI_OP( c.addi16sp, x2, 0xdfffff9f, -0x20000001, -0x60, x1, 12, x3)
inst_4:
// rs1_val == -268435457, imm_val == -352
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x10000001; immval:-0x160
TEST_CI_OP( c.addi16sp, x2, 0xeffffe9f, -0x10000001, -0x160, x1, 16, x3)
inst_5:
// rs1_val == -134217729, imm_val == -80
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x8000001; immval:-0x50
TEST_CI_OP( c.addi16sp, x2, 0xf7ffffaf, -0x8000001, -0x50, x1, 20, x3)
inst_6:
// rs1_val == -67108865, imm_val == -144
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x4000001; immval:-0x90
TEST_CI_OP( c.addi16sp, x2, 0xfbffff6f, -0x4000001, -0x90, x1, 24, x3)
inst_7:
// rs1_val == -33554433,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x2000001; immval:0xf0
TEST_CI_OP( c.addi16sp, x2, 0xfe0000ef, -0x2000001, 0xf0, x1, 28, x3)
inst_8:
// rs1_val == -16777217,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x1000001; immval:-0x80
TEST_CI_OP( c.addi16sp, x2, 0xfeffff7f, -0x1000001, -0x80, x1, 32, x3)
inst_9:
// rs1_val == -8388609,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x800001; immval:-0x70
TEST_CI_OP( c.addi16sp, x2, 0xff7fff8f, -0x800001, -0x70, x1, 36, x3)
inst_10:
// rs1_val == -4194305, imm_val == 64
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x400001; immval:0x40
TEST_CI_OP( c.addi16sp, x2, 0xffc0003f, -0x400001, 0x40, x1, 40, x3)
inst_11:
// rs1_val == -2097153,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x200001; immval:-0x160
TEST_CI_OP( c.addi16sp, x2, 0xffdffe9f, -0x200001, -0x160, x1, 44, x3)
inst_12:
// rs1_val == -1048577, imm_val == 16
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x100001; immval:0x10
TEST_CI_OP( c.addi16sp, x2, 0xfff0000f, -0x100001, 0x10, x1, 48, x3)
inst_13:
// rs1_val == -524289,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x80001; immval:0x10
TEST_CI_OP( c.addi16sp, x2, 0xfff8000f, -0x80001, 0x10, x1, 52, x3)
inst_14:
// rs1_val == -262145,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x40001; immval:-0x100
TEST_CI_OP( c.addi16sp, x2, 0xfffbfeff, -0x40001, -0x100, x1, 56, x3)
inst_15:
// rs1_val == -131073, imm_val == 336
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x20001; immval:0x150
TEST_CI_OP( c.addi16sp, x2, 0xfffe014f, -0x20001, 0x150, x1, 60, x3)
inst_16:
// rs1_val == -65537,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x10001; immval:-0x50
TEST_CI_OP( c.addi16sp, x2, 0xfffeffaf, -0x10001, -0x50, x1, 64, x3)
inst_17:
// rs1_val == -32769,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x8001; immval:0x40
TEST_CI_OP( c.addi16sp, x2, 0xffff803f, -0x8001, 0x40, x1, 68, x3)
inst_18:
// rs1_val == -16385,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x4001; immval:0x50
TEST_CI_OP( c.addi16sp, x2, 0xffffc04f, -0x4001, 0x50, x1, 72, x3)
inst_19:
// rs1_val == -8193,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x2001; immval:-0x40
TEST_CI_OP( c.addi16sp, x2, 0xffffdfbf, -0x2001, -0x40, x1, 76, x3)
inst_20:
// rs1_val == -4097,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x1001; immval:0x80
TEST_CI_OP( c.addi16sp, x2, 0xfffff07f, -0x1001, 0x80, x1, 80, x3)
inst_21:
// rs1_val == -2049,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x801; immval:0x80
TEST_CI_OP( c.addi16sp, x2, 0xfffff87f, -0x801, 0x80, x1, 84, x3)
inst_22:
// rs1_val == -1025,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x401; immval:-0x10
TEST_CI_OP( c.addi16sp, x2, 0xfffffbef, -0x401, -0x10, x1, 88, x3)
inst_23:
// rs1_val == -513,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x201; immval:0x150
TEST_CI_OP( c.addi16sp, x2, 0xffffff4f, -0x201, 0x150, x1, 92, x3)
inst_24:
// rs1_val == -257, imm_val == -32
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x101; immval:-0x20
TEST_CI_OP( c.addi16sp, x2, 0xfffffedf, -0x101, -0x20, x1, 96, x3)
inst_25:
// rs1_val == -129,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x81; immval:-0x20
TEST_CI_OP( c.addi16sp, x2, 0xffffff5f, -0x81, -0x20, x1, 100, x3)
inst_26:
// rs1_val == -65,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x41; immval:0x90
TEST_CI_OP( c.addi16sp, x2, 0x4f, -0x41, 0x90, x1, 104, x3)
inst_27:
// rs1_val == -33,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x21; immval:0x10
TEST_CI_OP( c.addi16sp, x2, 0xffffffef, -0x21, 0x10, x1, 108, x3)
inst_28:
// rs1_val == -17,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x11; immval:-0x160
TEST_CI_OP( c.addi16sp, x2, 0xfffffe8f, -0x11, -0x160, x1, 112, x3)
inst_29:
// rs1_val == -9,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x9; immval:-0x60
TEST_CI_OP( c.addi16sp, x2, 0xffffff97, -0x9, -0x60, x1, 116, x3)
inst_30:
// rs1_val == -5,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x5; immval:-0x100
TEST_CI_OP( c.addi16sp, x2, 0xfffffefb, -0x5, -0x100, x1, 120, x3)
inst_31:
// rs1_val == -3,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x3; immval:-0x90
TEST_CI_OP( c.addi16sp, x2, 0xffffff6d, -0x3, -0x90, x1, 124, x3)
inst_32:
// rs1_val == -2,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x2; immval:0x70
TEST_CI_OP( c.addi16sp, x2, 0x6e, -0x2, 0x70, x1, 128, x3)
inst_33:
// imm_val == 496,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x400000; immval:0x1f0
TEST_CI_OP( c.addi16sp, x2, 0x4001f0, 0x400000, 0x1f0, x1, 132, x3)
inst_34:
// imm_val == -272,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x5; immval:-0x110
TEST_CI_OP( c.addi16sp, x2, 0xfffffeeb, -0x5, -0x110, x1, 136, x3)
inst_35:
// imm_val == -48,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x400001; immval:-0x30
TEST_CI_OP( c.addi16sp, x2, 0xffbfffcf, -0x400001, -0x30, x1, 140, x3)
inst_36:
// rs1_val == -2147483648, rs1_val == (-2**(xlen-1))
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x80000000; immval:-0xa0
TEST_CI_OP( c.addi16sp, x2, 0x7fffff60, -0x80000000, -0xa0, x1, 144, x3)
inst_37:
// rs1_val == 1073741824, imm_val == 256
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x40000000; immval:0x100
TEST_CI_OP( c.addi16sp, x2, 0x40000100, 0x40000000, 0x100, x1, 148, x3)
inst_38:
// rs1_val == 536870912,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x20000000; immval:-0x10
TEST_CI_OP( c.addi16sp, x2, 0x1ffffff0, 0x20000000, -0x10, x1, 152, x3)
inst_39:
// rs1_val == 268435456,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x10000000; immval:0x30
TEST_CI_OP( c.addi16sp, x2, 0x10000030, 0x10000000, 0x30, x1, 156, x3)
inst_40:
// rs1_val == 134217728,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x8000000; immval:-0xa0
TEST_CI_OP( c.addi16sp, x2, 0x7ffff60, 0x8000000, -0xa0, x1, 160, x3)
inst_41:
// rs1_val == 64,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x40; immval:0x80
TEST_CI_OP( c.addi16sp, x2, 0xc0, 0x40, 0x80, x1, 164, x3)
inst_42:
// rs1_val == 32,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x20; immval:0x1f0
TEST_CI_OP( c.addi16sp, x2, 0x210, 0x20, 0x1f0, x1, 168, x3)
inst_43:
// rs1_val == 16,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x10; immval:0x1f0
TEST_CI_OP( c.addi16sp, x2, 0x200, 0x10, 0x1f0, x1, 172, x3)
inst_44:
// rs1_val == 8,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x8; immval:0x70
TEST_CI_OP( c.addi16sp, x2, 0x78, 0x8, 0x70, x1, 176, x3)
inst_45:
// rs1_val == 4,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x4; immval:-0x110
TEST_CI_OP( c.addi16sp, x2, 0xfffffef4, 0x4, -0x110, x1, 180, x3)
inst_46:
// rs1_val == 2,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x2; immval:-0x50
TEST_CI_OP( c.addi16sp, x2, 0xffffffb2, 0x2, -0x50, x1, 184, x3)
inst_47:
// rs1_val == 1,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x1; immval:0x50
TEST_CI_OP( c.addi16sp, x2, 0x51, 0x1, 0x50, x1, 188, x3)
inst_48:
// imm_val == 32,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x9; immval:0x20
TEST_CI_OP( c.addi16sp, x2, 0x29, 0x9, 0x20, x1, 192, x3)
inst_49:
// rs1_val == -1431655766,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x55555556; immval:0x30
TEST_CI_OP( c.addi16sp, x2, 0xaaaaaada, -0x55555556, 0x30, x1, 196, x3)
inst_50:
// rs1_val == 1431655765,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x55555555; immval:0x60
TEST_CI_OP( c.addi16sp, x2, 0x555555b5, 0x55555555, 0x60, x1, 200, x3)
inst_51:
// rs1_val == 0,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x0; immval:-0x100
TEST_CI_OP( c.addi16sp, x2, 0xffffff00, 0x0, -0x100, x1, 204, x3)
inst_52:
// rs1_val == imm_val,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x40; immval:0x40
TEST_CI_OP( c.addi16sp, x2, 0x80, 0x40, 0x40, x1, 208, x3)
inst_53:
// rs1_val == 67108864,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x4000000; immval:-0x200
TEST_CI_OP( c.addi16sp, x2, 0x3fffe00, 0x4000000, -0x200, x1, 212, x3)
inst_54:
// rs1_val == 33554432,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x2000000; immval:-0x200
TEST_CI_OP( c.addi16sp, x2, 0x1fffe00, 0x2000000, -0x200, x1, 216, x3)
inst_55:
// rs1_val == 16777216,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x1000000; immval:-0x40
TEST_CI_OP( c.addi16sp, x2, 0xffffc0, 0x1000000, -0x40, x1, 220, x3)
inst_56:
// rs1_val == 8388608,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x800000; immval:0x10
TEST_CI_OP( c.addi16sp, x2, 0x800010, 0x800000, 0x10, x1, 224, x3)
inst_57:
// rs1_val == 2097152,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x200000; immval:0x20
TEST_CI_OP( c.addi16sp, x2, 0x200020, 0x200000, 0x20, x1, 228, x3)
inst_58:
// rs1_val == 1048576,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x100000; immval:0x90
TEST_CI_OP( c.addi16sp, x2, 0x100090, 0x100000, 0x90, x1, 232, x3)
inst_59:
// rs1_val == 524288,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x80000; immval:0x50
TEST_CI_OP( c.addi16sp, x2, 0x80050, 0x80000, 0x50, x1, 236, x3)
inst_60:
// rs1_val == 262144,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x40000; immval:-0x160
TEST_CI_OP( c.addi16sp, x2, 0x3fea0, 0x40000, -0x160, x1, 240, x3)
inst_61:
// rs1_val == 131072,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x20000; immval:-0xa0
TEST_CI_OP( c.addi16sp, x2, 0x1ff60, 0x20000, -0xa0, x1, 244, x3)
inst_62:
// rs1_val == 65536,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x10000; immval:0x150
TEST_CI_OP( c.addi16sp, x2, 0x10150, 0x10000, 0x150, x1, 248, x3)
inst_63:
// rs1_val == 32768,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x8000; immval:0x1f0
TEST_CI_OP( c.addi16sp, x2, 0x81f0, 0x8000, 0x1f0, x1, 252, x3)
inst_64:
// rs1_val == 16384,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x4000; immval:0x40
TEST_CI_OP( c.addi16sp, x2, 0x4040, 0x4000, 0x40, x1, 256, x3)
inst_65:
// rs1_val == 8192,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x2000; immval:0x80
TEST_CI_OP( c.addi16sp, x2, 0x2080, 0x2000, 0x80, x1, 260, x3)
inst_66:
// rs1_val == 4096,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x1000; immval:0x1f0
TEST_CI_OP( c.addi16sp, x2, 0x11f0, 0x1000, 0x1f0, x1, 264, x3)
inst_67:
// rs1_val == 2048,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x800; immval:0x100
TEST_CI_OP( c.addi16sp, x2, 0x900, 0x800, 0x100, x1, 268, x3)
inst_68:
// rs1_val == 1024,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x400; immval:0x1f0
TEST_CI_OP( c.addi16sp, x2, 0x5f0, 0x400, 0x1f0, x1, 272, x3)
inst_69:
// rs1_val == 512,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x200; immval:0x150
TEST_CI_OP( c.addi16sp, x2, 0x350, 0x200, 0x150, x1, 276, x3)
inst_70:
// rs1_val == 256,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x100; immval:0x1f0
TEST_CI_OP( c.addi16sp, x2, 0x2f0, 0x100, 0x1f0, x1, 280, x3)
inst_71:
// rs1_val == 128,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x80; immval:0x30
TEST_CI_OP( c.addi16sp, x2, 0xb0, 0x80, 0x30, x1, 284, x3)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x1_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x1_1:
.fill 72*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
RVMODEL_DATA_END

165
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/caddi4spn-01.S
View File

@ -1,165 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Wed Aug 4 06:39:00 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.addi4spn instruction of the RISC-V C extension for the caddi4spn covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32EC")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",caddi4spn)
RVTEST_SIGBASE( x1,signature_x1_1)
inst_0:
// rd==x10, imm_val == 1020, imm_val > 0
// opcode:c.addi4spn; dest:x10; immval:0x3fc
TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x3fc, 0x3fc, x1, 0, x2)
inst_1:
// rd==x13, imm_val == 508,
// opcode:c.addi4spn; dest:x13; immval:0x1fc
TEST_CADDI4SPN_OP( c.addi4spn, x13, 0x1fc, 0x1fc, x1, 4, x2)
inst_2:
// rd==x9, imm_val == 764,
// opcode:c.addi4spn; dest:x9; immval:0x2fc
TEST_CADDI4SPN_OP( c.addi4spn, x9, 0x2fc, 0x2fc, x1, 8, x2)
inst_3:
// rd==x8, imm_val == 892,
// opcode:c.addi4spn; dest:x8; immval:0x37c
TEST_CADDI4SPN_OP( c.addi4spn, x8, 0x37c, 0x37c, x1, 12, x2)
inst_4:
// rd==x14, imm_val == 956,
// opcode:c.addi4spn; dest:x14; immval:0x3bc
TEST_CADDI4SPN_OP( c.addi4spn, x14, 0x3bc, 0x3bc, x1, 16, x2)
inst_5:
// rd==x11, imm_val == 988,
// opcode:c.addi4spn; dest:x11; immval:0x3dc
TEST_CADDI4SPN_OP( c.addi4spn, x11, 0x3dc, 0x3dc, x1, 20, x2)
inst_6:
// rd==x15, imm_val == 1004,
// opcode:c.addi4spn; dest:x15; immval:0x3ec
TEST_CADDI4SPN_OP( c.addi4spn, x15, 0x3ec, 0x3ec, x1, 24, x2)
inst_7:
// rd==x12, imm_val == 1012,
// opcode:c.addi4spn; dest:x12; immval:0x3f4
TEST_CADDI4SPN_OP( c.addi4spn, x12, 0x3f4, 0x3f4, x1, 28, x2)
inst_8:
// imm_val == 1016,
// opcode:c.addi4spn; dest:x10; immval:0x3f8
TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x3f8, 0x3f8, x1, 32, x2)
inst_9:
// imm_val == 512,
// opcode:c.addi4spn; dest:x10; immval:0x200
TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x200, 0x200, x1, 36, x2)
inst_10:
// imm_val == 256,
// opcode:c.addi4spn; dest:x10; immval:0x100
TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x100, 0x100, x1, 40, x2)
inst_11:
// imm_val == 128,
// opcode:c.addi4spn; dest:x10; immval:0x80
TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x80, 0x80, x1, 44, x2)
inst_12:
// imm_val == 4,
// opcode:c.addi4spn; dest:x10; immval:0x4
TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x4, 0x4, x1, 48, x2)
inst_13:
// imm_val == 680,
// opcode:c.addi4spn; dest:x10; immval:0x2a8
TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x2a8, 0x2a8, x1, 52, x2)
inst_14:
// imm_val == 340,
// opcode:c.addi4spn; dest:x10; immval:0x154
TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x154, 0x154, x1, 56, x2)
inst_15:
// imm_val == 64,
// opcode:c.addi4spn; dest:x10; immval:0x40
TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x40, 0x40, x1, 60, x2)
inst_16:
// imm_val == 32,
// opcode:c.addi4spn; dest:x10; immval:0x20
TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x20, 0x20, x1, 64, x2)
inst_17:
// imm_val == 16,
// opcode:c.addi4spn; dest:x10; immval:0x10
TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x10, 0x10, x1, 68, x2)
inst_18:
// imm_val == 8,
// opcode:c.addi4spn; dest:x10; immval:0x8
TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x8, 0x8, x1, 72, x2)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x1_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x1_1:
.fill 19*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
RVMODEL_DATA_END

3005
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cand-01.S
View File

File diff suppressed because it is too large Load Diff

1940
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/candi-01.S
View File

File diff suppressed because it is too large Load Diff

490
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cbeqz-01.S
View File

@ -1,490 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Wed Aug 4 06:39:00 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.beqz instruction of the RISC-V C extension for the cbeqz covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32EC")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",cbeqz)
RVTEST_SIGBASE( x1,signature_x1_1)
inst_0:
// rs1==x10, rs1_val < 0 and imm_val < 0, rs1_val == -4097
// opcode:c.beqz; op1:x10; op1val:-0x1001; immval:0xac
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x1001, 0xac, 1b, x1, 0)
inst_1:
// rs1==x14, rs1_val == 2147483647, rs1_val == (2**(xlen-1)-1), rs1_val > 0 and imm_val < 0
// opcode:c.beqz; op1:x14; op1val:0x7fffffff; immval:0x14
TEST_CBRANCH_OP(c.beqz, x2, x14, 0x7fffffff, 0x14, 1b, x1, 4)
inst_2:
// rs1==x8, rs1_val == -1073741825, rs1_val < 0 and imm_val > 0
// opcode:c.beqz; op1:x8; op1val:-0x40000001; immval:0x20
TEST_CBRANCH_OP(c.beqz, x2, x8, -0x40000001, 0x20, 3f, x1, 8)
inst_3:
// rs1==x15, rs1_val == -536870913,
// opcode:c.beqz; op1:x15; op1val:-0x20000001; immval:0xac
TEST_CBRANCH_OP(c.beqz, x2, x15, -0x20000001, 0xac, 1b, x1, 12)
inst_4:
// rs1==x12, rs1_val == -268435457,
// opcode:c.beqz; op1:x12; op1val:-0x10000001; immval:0x12
TEST_CBRANCH_OP(c.beqz, x2, x12, -0x10000001, 0x12, 3f, x1, 16)
inst_5:
// rs1==x13, rs1_val == -134217729,
// opcode:c.beqz; op1:x13; op1val:-0x8000001; immval:0x7e
TEST_CBRANCH_OP(c.beqz, x2, x13, -0x8000001, 0x7e, 3f, x1, 20)
inst_6:
// rs1==x11, rs1_val == -67108865,
// opcode:c.beqz; op1:x11; op1val:-0x4000001; immval:0xe
TEST_CBRANCH_OP(c.beqz, x2, x11, -0x4000001, 0xe, 1b, x1, 24)
inst_7:
// rs1==x9, rs1_val == -33554433,
// opcode:c.beqz; op1:x9; op1val:-0x2000001; immval:0xc
TEST_CBRANCH_OP(c.beqz, x2, x9, -0x2000001, 0xc, 1b, x1, 28)
inst_8:
// rs1_val == -16777217,
// opcode:c.beqz; op1:x10; op1val:-0x1000001; immval:0x20
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x1000001, 0x20, 3f, x1, 32)
inst_9:
// rs1_val == -8388609,
// opcode:c.beqz; op1:x10; op1val:-0x800001; immval:0x80
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x800001, 0x80, 1b, x1, 36)
inst_10:
// rs1_val == -4194305,
// opcode:c.beqz; op1:x10; op1val:-0x400001; immval:0xe
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x400001, 0xe, 1b, x1, 40)
inst_11:
// rs1_val == -2097153,
// opcode:c.beqz; op1:x10; op1val:-0x200001; immval:0x40
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x200001, 0x40, 3f, x1, 44)
inst_12:
// rs1_val == -1048577,
// opcode:c.beqz; op1:x10; op1val:-0x100001; immval:0x22
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x100001, 0x22, 1b, x1, 48)
inst_13:
// rs1_val == -524289,
// opcode:c.beqz; op1:x10; op1val:-0x80001; immval:0x82
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x80001, 0x82, 1b, x1, 52)
inst_14:
// rs1_val == -262145,
// opcode:c.beqz; op1:x10; op1val:-0x40001; immval:0xc
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x40001, 0xc, 3f, x1, 56)
inst_15:
// rs1_val == -131073,
// opcode:c.beqz; op1:x10; op1val:-0x20001; immval:0x6
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x20001, 0x6, 3f, x1, 60)
inst_16:
// rs1_val == -65537,
// opcode:c.beqz; op1:x10; op1val:-0x10001; immval:0x12
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x10001, 0x12, 3f, x1, 64)
inst_17:
// rs1_val == -32769,
// opcode:c.beqz; op1:x10; op1val:-0x8001; immval:0x42
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x8001, 0x42, 1b, x1, 68)
inst_18:
// rs1_val == -16385,
// opcode:c.beqz; op1:x10; op1val:-0x4001; immval:0x80
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x4001, 0x80, 3f, x1, 72)
inst_19:
// rs1_val == -8193,
// opcode:c.beqz; op1:x10; op1val:-0x2001; immval:0x7e
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x2001, 0x7e, 3f, x1, 76)
inst_20:
// rs1_val == -2049,
// opcode:c.beqz; op1:x10; op1val:-0x801; immval:0xe
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x801, 0xe, 1b, x1, 80)
inst_21:
// rs1_val == -1025,
// opcode:c.beqz; op1:x10; op1val:-0x401; immval:0x80
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x401, 0x80, 1b, x1, 84)
inst_22:
// rs1_val == -513,
// opcode:c.beqz; op1:x10; op1val:-0x201; immval:0xc
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x201, 0xc, 3f, x1, 88)
inst_23:
// rs1_val == -257,
// opcode:c.beqz; op1:x10; op1val:-0x101; immval:0xa
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x101, 0xa, 1b, x1, 92)
inst_24:
// rs1_val == -129,
// opcode:c.beqz; op1:x10; op1val:-0x81; immval:0x14
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x81, 0x14, 1b, x1, 96)
inst_25:
// rs1_val == -65,
// opcode:c.beqz; op1:x10; op1val:-0x41; immval:0xa
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x41, 0xa, 1b, x1, 100)
inst_26:
// rs1_val == -33,
// opcode:c.beqz; op1:x10; op1val:-0x21; immval:0xac
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x21, 0xac, 1b, x1, 104)
inst_27:
// rs1_val == -17,
// opcode:c.beqz; op1:x10; op1val:-0x11; immval:0x12
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x11, 0x12, 1b, x1, 108)
inst_28:
// rs1_val == -9,
// opcode:c.beqz; op1:x10; op1val:-0x9; immval:0x20
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x9, 0x20, 3f, x1, 112)
inst_29:
// rs1_val == -5,
// opcode:c.beqz; op1:x10; op1val:-0x5; immval:0x42
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x5, 0x42, 1b, x1, 116)
inst_30:
// rs1_val == -3,
// opcode:c.beqz; op1:x10; op1val:-0x3; immval:0x42
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x3, 0x42, 1b, x1, 120)
inst_31:
// rs1_val == -2,
// opcode:c.beqz; op1:x10; op1val:-0x2; immval:0xa
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x2, 0xa, 3f, x1, 124)
inst_32:
// rs1_val == -2147483648, rs1_val == (-2**(xlen-1))
// opcode:c.beqz; op1:x10; op1val:-0x80000000; immval:0x6
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x80000000, 0x6, 3f, x1, 128)
inst_33:
// rs1_val == 1073741824, rs1_val > 0 and imm_val > 0
// opcode:c.beqz; op1:x10; op1val:0x40000000; immval:0x7e
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x40000000, 0x7e, 3f, x1, 132)
inst_34:
// rs1_val == 536870912,
// opcode:c.beqz; op1:x10; op1val:0x20000000; immval:0x22
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x20000000, 0x22, 1b, x1, 136)
inst_35:
// rs1_val == 268435456,
// opcode:c.beqz; op1:x10; op1val:0x10000000; immval:0x40
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x10000000, 0x40, 3f, x1, 140)
inst_36:
// rs1_val == 134217728,
// opcode:c.beqz; op1:x10; op1val:0x8000000; immval:0x80
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x8000000, 0x80, 3f, x1, 144)
inst_37:
// rs1_val == 67108864,
// opcode:c.beqz; op1:x10; op1val:0x4000000; immval:0x80
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x4000000, 0x80, 3f, x1, 148)
inst_38:
// rs1_val == 33554432,
// opcode:c.beqz; op1:x10; op1val:0x2000000; immval:0x22
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x2000000, 0x22, 1b, x1, 152)
inst_39:
// rs1_val == 16777216,
// opcode:c.beqz; op1:x10; op1val:0x1000000; immval:0x40
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x1000000, 0x40, 3f, x1, 156)
inst_40:
// rs1_val == 8388608,
// opcode:c.beqz; op1:x10; op1val:0x800000; immval:0xe
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x800000, 0xe, 3f, x1, 160)
inst_41:
// rs1_val == 4194304,
// opcode:c.beqz; op1:x10; op1val:0x400000; immval:0x80
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x400000, 0x80, 3f, x1, 164)
inst_42:
// rs1_val == 2097152,
// opcode:c.beqz; op1:x10; op1val:0x200000; immval:0xe
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x200000, 0xe, 3f, x1, 168)
inst_43:
// rs1_val == 1048576,
// opcode:c.beqz; op1:x10; op1val:0x100000; immval:0x6
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x100000, 0x6, 1b, x1, 172)
inst_44:
// rs1_val == 524288,
// opcode:c.beqz; op1:x10; op1val:0x80000; immval:0x82
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x80000, 0x82, 1b, x1, 176)
inst_45:
// rs1_val == 262144,
// opcode:c.beqz; op1:x10; op1val:0x40000; immval:0x42
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x40000, 0x42, 1b, x1, 180)
inst_46:
// rs1_val == 131072,
// opcode:c.beqz; op1:x10; op1val:0x20000; immval:0xc
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x20000, 0xc, 1b, x1, 184)
inst_47:
// rs1_val == 65536,
// opcode:c.beqz; op1:x10; op1val:0x10000; immval:0x82
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x10000, 0x82, 1b, x1, 188)
inst_48:
// rs1_val == 32768,
// opcode:c.beqz; op1:x10; op1val:0x8000; immval:0x4
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x8000, 0x4, 1b, x1, 192)
inst_49:
// rs1_val == 16384,
// opcode:c.beqz; op1:x10; op1val:0x4000; immval:0xa
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x4000, 0xa, 1b, x1, 196)
inst_50:
// rs1_val == 8192,
// opcode:c.beqz; op1:x10; op1val:0x2000; immval:0x80
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x2000, 0x80, 1b, x1, 200)
inst_51:
// rs1_val == 4096,
// opcode:c.beqz; op1:x10; op1val:0x1000; immval:0x40
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x1000, 0x40, 3f, x1, 204)
inst_52:
// rs1_val == 2048,
// opcode:c.beqz; op1:x10; op1val:0x800; immval:0x20
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x800, 0x20, 3f, x1, 208)
inst_53:
// rs1_val == 1024,
// opcode:c.beqz; op1:x10; op1val:0x400; immval:0xc
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x400, 0xc, 3f, x1, 212)
inst_54:
// rs1_val == 512,
// opcode:c.beqz; op1:x10; op1val:0x200; immval:0x10
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x200, 0x10, 1b, x1, 216)
inst_55:
// rs1_val == 256,
// opcode:c.beqz; op1:x10; op1val:0x100; immval:0x7e
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x100, 0x7e, 3f, x1, 220)
inst_56:
// rs1_val == 128,
// opcode:c.beqz; op1:x10; op1val:0x80; immval:0x6
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x80, 0x6, 3f, x1, 224)
inst_57:
// rs1_val == 64,
// opcode:c.beqz; op1:x10; op1val:0x40; immval:0xa
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x40, 0xa, 3f, x1, 228)
inst_58:
// rs1_val == 32,
// opcode:c.beqz; op1:x10; op1val:0x20; immval:0x12
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x20, 0x12, 1b, x1, 232)
inst_59:
// rs1_val == 16,
// opcode:c.beqz; op1:x10; op1val:0x10; immval:0x4
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x10, 0x4, 1b, x1, 236)
inst_60:
// rs1_val == 1,
// opcode:c.beqz; op1:x10; op1val:0x1; immval:0xe
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x1, 0xe, 3f, x1, 240)
inst_61:
// rs1_val==46341,
// opcode:c.beqz; op1:x10; op1val:0xb505; immval:0x10
TEST_CBRANCH_OP(c.beqz, x2, x10, 0xb505, 0x10, 1b, x1, 244)
inst_62:
// rs1_val==-46339,
// opcode:c.beqz; op1:x10; op1val:-0xb503; immval:0x82
TEST_CBRANCH_OP(c.beqz, x2, x10, -0xb503, 0x82, 1b, x1, 248)
inst_63:
// rs1_val==1717986919,
// opcode:c.beqz; op1:x10; op1val:0x66666667; immval:0x8
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x66666667, 0x8, 3f, x1, 252)
inst_64:
// rs1_val==858993460,
// opcode:c.beqz; op1:x10; op1val:0x33333334; immval:0x8
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x33333334, 0x8, 3f, x1, 256)
inst_65:
// rs1_val==6,
// opcode:c.beqz; op1:x10; op1val:0x6; immval:0x6
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x6, 0x6, 1b, x1, 260)
inst_66:
// rs1_val==-1431655765,
// opcode:c.beqz; op1:x10; op1val:-0x55555555; immval:0x80
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x55555555, 0x80, 3f, x1, 264)
inst_67:
// rs1_val==1431655766,
// opcode:c.beqz; op1:x10; op1val:0x55555556; immval:0x14
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x55555556, 0x14, 1b, x1, 268)
inst_68:
// rs1_val==4, rs1_val == 4
// opcode:c.beqz; op1:x10; op1val:0x4; immval:0x82
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x4, 0x82, 1b, x1, 272)
inst_69:
// rs1_val==46339,
// opcode:c.beqz; op1:x10; op1val:0xb503; immval:0x14
TEST_CBRANCH_OP(c.beqz, x2, x10, 0xb503, 0x14, 1b, x1, 276)
inst_70:
// rs1_val==0, rs1_val == 0, rs1_val == 0 and imm_val > 0
// opcode:c.beqz; op1:x10; op1val:0x0; immval:0xe
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x0, 0xe, 3f, x1, 280)
inst_71:
// rs1_val==1717986917,
// opcode:c.beqz; op1:x10; op1val:0x66666665; immval:0x80
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x66666665, 0x80, 3f, x1, 284)
inst_72:
// rs1_val==858993458,
// opcode:c.beqz; op1:x10; op1val:0x33333332; immval:0xa
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x33333332, 0xa, 1b, x1, 288)
inst_73:
// rs1_val==1431655764,
// opcode:c.beqz; op1:x10; op1val:0x55555554; immval:0xc
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x55555554, 0xc, 1b, x1, 292)
inst_74:
// rs1_val==2, rs1_val == 2
// opcode:c.beqz; op1:x10; op1val:0x2; immval:0xa
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x2, 0xa, 1b, x1, 296)
inst_75:
// rs1_val==46340,
// opcode:c.beqz; op1:x10; op1val:0xb504; immval:0x8
TEST_CBRANCH_OP(c.beqz, x2, x10, 0xb504, 0x8, 1b, x1, 300)
inst_76:
// rs1_val==-46340,
// opcode:c.beqz; op1:x10; op1val:-0xb504; immval:0x7e
TEST_CBRANCH_OP(c.beqz, x2, x10, -0xb504, 0x7e, 3f, x1, 304)
inst_77:
// rs1_val==1717986918,
// opcode:c.beqz; op1:x10; op1val:0x66666666; immval:0xe
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x66666666, 0xe, 3f, x1, 308)
inst_78:
// rs1_val==858993459,
// opcode:c.beqz; op1:x10; op1val:0x33333333; immval:0x12
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x33333333, 0x12, 3f, x1, 312)
inst_79:
// rs1_val==5,
// opcode:c.beqz; op1:x10; op1val:0x5; immval:0x10
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x5, 0x10, 1b, x1, 316)
inst_80:
// rs1_val==-1431655766, rs1_val == -1431655766
// opcode:c.beqz; op1:x10; op1val:-0x55555556; immval:0x40
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x55555556, 0x40, 3f, x1, 320)
inst_81:
// rs1_val == 1431655765, rs1_val==1431655765
// opcode:c.beqz; op1:x10; op1val:0x55555555; immval:0x12
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x55555555, 0x12, 1b, x1, 324)
inst_82:
// rs1_val == 8,
// opcode:c.beqz; op1:x10; op1val:0x8; immval:0xe
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x8, 0xe, 1b, x1, 328)
inst_83:
// rs1_val==3,
// opcode:c.beqz; op1:x10; op1val:0x3; immval:0x4
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x3, 0x4, 1b, x1, 332)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x1_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x1_1:
.fill 84*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
RVMODEL_DATA_END

490
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cbnez-01.S
View File

@ -1,490 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Wed Aug 4 06:39:00 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.bnez instruction of the RISC-V C extension for the cbnez covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32EC")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",cbnez)
RVTEST_SIGBASE( x1,signature_x1_1)
inst_0:
// rs1==x11, rs1_val < 0 and imm_val < 0, rs1_val == -524289
// opcode: c.bnez; op1:x11; op1val:-0x80001; immval:0x4
TEST_CBRANCH_OP(c.bnez, x2, x11, -0x80001, 0x4, 1b, x1, 0)
inst_1:
// rs1==x10, rs1_val == 2147483647, rs1_val > 0 and imm_val > 0, rs1_val == (2**(xlen-1)-1)
// opcode: c.bnez; op1:x10; op1val:0x7fffffff; immval:0x7e
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x7fffffff, 0x7e, 3f, x1, 4)
inst_2:
// rs1==x8, rs1_val == -1073741825, rs1_val < 0 and imm_val > 0
// opcode: c.bnez; op1:x8; op1val:-0x40000001; immval:0xaa
TEST_CBRANCH_OP(c.bnez, x2, x8, -0x40000001, 0xaa, 3f, x1, 8)
inst_3:
// rs1==x12, rs1_val == -536870913,
// opcode: c.bnez; op1:x12; op1val:-0x20000001; immval:0xe
TEST_CBRANCH_OP(c.bnez, x2, x12, -0x20000001, 0xe, 1b, x1, 12)
inst_4:
// rs1==x15, rs1_val == -268435457,
// opcode: c.bnez; op1:x15; op1val:-0x10000001; immval:0x8
TEST_CBRANCH_OP(c.bnez, x2, x15, -0x10000001, 0x8, 3f, x1, 16)
inst_5:
// rs1==x13, rs1_val == -134217729,
// opcode: c.bnez; op1:x13; op1val:-0x8000001; immval:0xa
TEST_CBRANCH_OP(c.bnez, x2, x13, -0x8000001, 0xa, 1b, x1, 20)
inst_6:
// rs1==x9, rs1_val == -67108865,
// opcode: c.bnez; op1:x9; op1val:-0x4000001; immval:0xe
TEST_CBRANCH_OP(c.bnez, x2, x9, -0x4000001, 0xe, 1b, x1, 24)
inst_7:
// rs1==x14, rs1_val == -33554433,
// opcode: c.bnez; op1:x14; op1val:-0x2000001; immval:0x4
TEST_CBRANCH_OP(c.bnez, x2, x14, -0x2000001, 0x4, 3f, x1, 28)
inst_8:
// rs1_val == -16777217,
// opcode: c.bnez; op1:x10; op1val:-0x1000001; immval:0xaa
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x1000001, 0xaa, 3f, x1, 32)
inst_9:
// rs1_val == -8388609,
// opcode: c.bnez; op1:x10; op1val:-0x800001; immval:0xc
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x800001, 0xc, 3f, x1, 36)
inst_10:
// rs1_val == -4194305,
// opcode: c.bnez; op1:x10; op1val:-0x400001; immval:0x6
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x400001, 0x6, 1b, x1, 40)
inst_11:
// rs1_val == -2097153,
// opcode: c.bnez; op1:x10; op1val:-0x200001; immval:0x40
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x200001, 0x40, 3f, x1, 44)
inst_12:
// rs1_val == -1048577,
// opcode: c.bnez; op1:x10; op1val:-0x100001; immval:0xaa
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x100001, 0xaa, 3f, x1, 48)
inst_13:
// rs1_val == -262145,
// opcode: c.bnez; op1:x10; op1val:-0x40001; immval:0xe
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x40001, 0xe, 3f, x1, 52)
inst_14:
// rs1_val == -131073,
// opcode: c.bnez; op1:x10; op1val:-0x20001; immval:0x20
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x20001, 0x20, 3f, x1, 56)
inst_15:
// rs1_val == -65537,
// opcode: c.bnez; op1:x10; op1val:-0x10001; immval:0x40
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x10001, 0x40, 3f, x1, 60)
inst_16:
// rs1_val == -32769,
// opcode: c.bnez; op1:x10; op1val:-0x8001; immval:0xa
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x8001, 0xa, 1b, x1, 64)
inst_17:
// rs1_val == -16385,
// opcode: c.bnez; op1:x10; op1val:-0x4001; immval:0x12
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x4001, 0x12, 3f, x1, 68)
inst_18:
// rs1_val == -8193,
// opcode: c.bnez; op1:x10; op1val:-0x2001; immval:0xc
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x2001, 0xc, 1b, x1, 72)
inst_19:
// rs1_val == -4097,
// opcode: c.bnez; op1:x10; op1val:-0x1001; immval:0x42
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x1001, 0x42, 1b, x1, 76)
inst_20:
// rs1_val == -2049,
// opcode: c.bnez; op1:x10; op1val:-0x801; immval:0x80
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x801, 0x80, 3f, x1, 80)
inst_21:
// rs1_val == -1025,
// opcode: c.bnez; op1:x10; op1val:-0x401; immval:0x12
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x401, 0x12, 3f, x1, 84)
inst_22:
// rs1_val == -513,
// opcode: c.bnez; op1:x10; op1val:-0x201; immval:0x82
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x201, 0x82, 1b, x1, 88)
inst_23:
// rs1_val == -257,
// opcode: c.bnez; op1:x10; op1val:-0x101; immval:0x80
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x101, 0x80, 1b, x1, 92)
inst_24:
// rs1_val == -129,
// opcode: c.bnez; op1:x10; op1val:-0x81; immval:0xe
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x81, 0xe, 3f, x1, 96)
inst_25:
// rs1_val == -65,
// opcode: c.bnez; op1:x10; op1val:-0x41; immval:0x10
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x41, 0x10, 3f, x1, 100)
inst_26:
// rs1_val == -33,
// opcode: c.bnez; op1:x10; op1val:-0x21; immval:0x7e
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x21, 0x7e, 3f, x1, 104)
inst_27:
// rs1_val == -17,
// opcode: c.bnez; op1:x10; op1val:-0x11; immval:0x20
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x11, 0x20, 3f, x1, 108)
inst_28:
// rs1_val == -9,
// opcode: c.bnez; op1:x10; op1val:-0x9; immval:0x4
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x9, 0x4, 1b, x1, 112)
inst_29:
// rs1_val == -5,
// opcode: c.bnez; op1:x10; op1val:-0x5; immval:0x80
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x5, 0x80, 1b, x1, 116)
inst_30:
// rs1_val == -3,
// opcode: c.bnez; op1:x10; op1val:-0x3; immval:0xaa
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x3, 0xaa, 3f, x1, 120)
inst_31:
// rs1_val == -2,
// opcode: c.bnez; op1:x10; op1val:-0x2; immval:0x10
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x2, 0x10, 1b, x1, 124)
inst_32:
// rs1_val == -2147483648, rs1_val == (-2**(xlen-1))
// opcode: c.bnez; op1:x10; op1val:-0x80000000; immval:0x80
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x80000000, 0x80, 1b, x1, 128)
inst_33:
// rs1_val == 1073741824,
// opcode: c.bnez; op1:x10; op1val:0x40000000; immval:0x7e
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x40000000, 0x7e, 3f, x1, 132)
inst_34:
// rs1_val == 536870912, rs1_val > 0 and imm_val < 0
// opcode: c.bnez; op1:x10; op1val:0x20000000; immval:0xc
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x20000000, 0xc, 1b, x1, 136)
inst_35:
// rs1_val == 268435456,
// opcode: c.bnez; op1:x10; op1val:0x10000000; immval:0x7e
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x10000000, 0x7e, 3f, x1, 140)
inst_36:
// rs1_val == 134217728,
// opcode: c.bnez; op1:x10; op1val:0x8000000; immval:0x82
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x8000000, 0x82, 1b, x1, 144)
inst_37:
// rs1_val == 67108864,
// opcode: c.bnez; op1:x10; op1val:0x4000000; immval:0xaa
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x4000000, 0xaa, 3f, x1, 148)
inst_38:
// rs1_val == 33554432,
// opcode: c.bnez; op1:x10; op1val:0x2000000; immval:0xe
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x2000000, 0xe, 1b, x1, 152)
inst_39:
// rs1_val == 16777216,
// opcode: c.bnez; op1:x10; op1val:0x1000000; immval:0xc
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x1000000, 0xc, 3f, x1, 156)
inst_40:
// rs1_val == 8388608,
// opcode: c.bnez; op1:x10; op1val:0x800000; immval:0x20
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x800000, 0x20, 3f, x1, 160)
inst_41:
// rs1_val == 4194304,
// opcode: c.bnez; op1:x10; op1val:0x400000; immval:0x8
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x400000, 0x8, 3f, x1, 164)
inst_42:
// rs1_val == 2097152,
// opcode: c.bnez; op1:x10; op1val:0x200000; immval:0x22
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x200000, 0x22, 1b, x1, 168)
inst_43:
// rs1_val == 1048576,
// opcode: c.bnez; op1:x10; op1val:0x100000; immval:0x4
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x100000, 0x4, 1b, x1, 172)
inst_44:
// rs1_val == 524288,
// opcode: c.bnez; op1:x10; op1val:0x80000; immval:0x8
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x80000, 0x8, 1b, x1, 176)
inst_45:
// rs1_val == 262144,
// opcode: c.bnez; op1:x10; op1val:0x40000; immval:0x6
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x40000, 0x6, 1b, x1, 180)
inst_46:
// rs1_val == 131072,
// opcode: c.bnez; op1:x10; op1val:0x20000; immval:0x6
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x20000, 0x6, 1b, x1, 184)
inst_47:
// rs1_val == 65536,
// opcode: c.bnez; op1:x10; op1val:0x10000; immval:0x7e
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x10000, 0x7e, 3f, x1, 188)
inst_48:
// rs1_val == 32768,
// opcode: c.bnez; op1:x10; op1val:0x8000; immval:0x7e
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x8000, 0x7e, 3f, x1, 192)
inst_49:
// rs1_val == 16384,
// opcode: c.bnez; op1:x10; op1val:0x4000; immval:0xac
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x4000, 0xac, 1b, x1, 196)
inst_50:
// rs1_val == 8192,
// opcode: c.bnez; op1:x10; op1val:0x2000; immval:0x10
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x2000, 0x10, 3f, x1, 200)
inst_51:
// rs1_val == 4096,
// opcode: c.bnez; op1:x10; op1val:0x1000; immval:0xc
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x1000, 0xc, 1b, x1, 204)
inst_52:
// rs1_val == 2048,
// opcode: c.bnez; op1:x10; op1val:0x800; immval:0x7e
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x800, 0x7e, 3f, x1, 208)
inst_53:
// rs1_val == 1024,
// opcode: c.bnez; op1:x10; op1val:0x400; immval:0xa
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x400, 0xa, 1b, x1, 212)
inst_54:
// rs1_val == 512,
// opcode: c.bnez; op1:x10; op1val:0x200; immval:0x12
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x200, 0x12, 3f, x1, 216)
inst_55:
// rs1_val == 256,
// opcode: c.bnez; op1:x10; op1val:0x100; immval:0xe
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x100, 0xe, 3f, x1, 220)
inst_56:
// rs1_val == 128,
// opcode: c.bnez; op1:x10; op1val:0x80; immval:0xe
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x80, 0xe, 1b, x1, 224)
inst_57:
// rs1_val == 64,
// opcode: c.bnez; op1:x10; op1val:0x40; immval:0x22
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x40, 0x22, 1b, x1, 228)
inst_58:
// rs1_val == 32,
// opcode: c.bnez; op1:x10; op1val:0x20; immval:0x4
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x20, 0x4, 1b, x1, 232)
inst_59:
// rs1_val == 16,
// opcode: c.bnez; op1:x10; op1val:0x10; immval:0x8
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x10, 0x8, 3f, x1, 236)
inst_60:
// rs1_val == 1,
// opcode: c.bnez; op1:x10; op1val:0x1; immval:0x4
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x1, 0x4, 3f, x1, 240)
inst_61:
// rs1_val==46341,
// opcode: c.bnez; op1:x10; op1val:0xb505; immval:0x12
TEST_CBRANCH_OP(c.bnez, x2, x10, 0xb505, 0x12, 1b, x1, 244)
inst_62:
// rs1_val==-46339,
// opcode: c.bnez; op1:x10; op1val:-0xb503; immval:0x22
TEST_CBRANCH_OP(c.bnez, x2, x10, -0xb503, 0x22, 1b, x1, 248)
inst_63:
// rs1_val==1717986919,
// opcode: c.bnez; op1:x10; op1val:0x66666667; immval:0x8
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x66666667, 0x8, 3f, x1, 252)
inst_64:
// rs1_val==858993460,
// opcode: c.bnez; op1:x10; op1val:0x33333334; immval:0x4
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x33333334, 0x4, 1b, x1, 256)
inst_65:
// rs1_val==6,
// opcode: c.bnez; op1:x10; op1val:0x6; immval:0x6
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x6, 0x6, 1b, x1, 260)
inst_66:
// rs1_val==-1431655765,
// opcode: c.bnez; op1:x10; op1val:-0x55555555; immval:0x20
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x55555555, 0x20, 3f, x1, 264)
inst_67:
// rs1_val==1431655766,
// opcode: c.bnez; op1:x10; op1val:0x55555556; immval:0x12
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x55555556, 0x12, 3f, x1, 268)
inst_68:
// rs1_val==4, rs1_val == 4
// opcode: c.bnez; op1:x10; op1val:0x4; immval:0xac
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x4, 0xac, 1b, x1, 272)
inst_69:
// rs1_val==46339,
// opcode: c.bnez; op1:x10; op1val:0xb503; immval:0x7e
TEST_CBRANCH_OP(c.bnez, x2, x10, 0xb503, 0x7e, 3f, x1, 276)
inst_70:
// rs1_val==0, rs1_val == 0, rs1_val == 0 and imm_val < 0
// opcode: c.bnez; op1:x10; op1val:0x0; immval:0x12
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x0, 0x12, 1b, x1, 280)
inst_71:
// rs1_val==1717986917,
// opcode: c.bnez; op1:x10; op1val:0x66666665; immval:0x8
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x66666665, 0x8, 3f, x1, 284)
inst_72:
// rs1_val==858993458,
// opcode: c.bnez; op1:x10; op1val:0x33333332; immval:0x80
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x33333332, 0x80, 1b, x1, 288)
inst_73:
// rs1_val==1431655764,
// opcode: c.bnez; op1:x10; op1val:0x55555554; immval:0x12
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x55555554, 0x12, 3f, x1, 292)
inst_74:
// rs1_val==2, rs1_val == 2
// opcode: c.bnez; op1:x10; op1val:0x2; immval:0x12
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x2, 0x12, 1b, x1, 296)
inst_75:
// rs1_val==46340,
// opcode: c.bnez; op1:x10; op1val:0xb504; immval:0xaa
TEST_CBRANCH_OP(c.bnez, x2, x10, 0xb504, 0xaa, 3f, x1, 300)
inst_76:
// rs1_val==-46340,
// opcode: c.bnez; op1:x10; op1val:-0xb504; immval:0x4
TEST_CBRANCH_OP(c.bnez, x2, x10, -0xb504, 0x4, 1b, x1, 304)
inst_77:
// rs1_val==1717986918,
// opcode: c.bnez; op1:x10; op1val:0x66666666; immval:0x8
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x66666666, 0x8, 3f, x1, 308)
inst_78:
// rs1_val==858993459,
// opcode: c.bnez; op1:x10; op1val:0x33333333; immval:0x22
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x33333333, 0x22, 1b, x1, 312)
inst_79:
// rs1_val==5,
// opcode: c.bnez; op1:x10; op1val:0x5; immval:0x12
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x5, 0x12, 1b, x1, 316)
inst_80:
// rs1_val==-1431655766, rs1_val == -1431655766
// opcode: c.bnez; op1:x10; op1val:-0x55555556; immval:0xac
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x55555556, 0xac, 1b, x1, 320)
inst_81:
// rs1_val==1431655765, rs1_val == 1431655765
// opcode: c.bnez; op1:x10; op1val:0x55555555; immval:0x4
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x55555555, 0x4, 1b, x1, 324)
inst_82:
// rs1_val == 8,
// opcode: c.bnez; op1:x10; op1val:0x8; immval:0xaa
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x8, 0xaa, 3f, x1, 328)
inst_83:
// rs1_val==3,
// opcode: c.bnez; op1:x10; op1val:0x3; immval:0xaa
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x3, 0xaa, 3f, x1, 332)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x1_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x1_1:
.fill 84*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
RVMODEL_DATA_END

155
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cj-01.S
View File

@ -1,155 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Wed Aug 4 06:39:00 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.j instruction of the RISC-V C extension for the cj covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32EC")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",cj)
RVTEST_SIGBASE( x1,signature_x1_1)
inst_0:
// imm_val < 0, imm_val == -66
// opcode:c.j; immval:0x42
TEST_CJ_OP(c.j, x2, 0x42, 1b, x1, 0)
inst_1:
// imm_val == -1026,
// opcode:c.j; immval:0x402
TEST_CJ_OP(c.j, x2, 0x402, 1b, x1, 4)
inst_2:
// imm_val == -514,
// opcode:c.j; immval:0x202
TEST_CJ_OP(c.j, x2, 0x202, 1b, x1, 8)
inst_3:
// imm_val == -258,
// opcode:c.j; immval:0x102
TEST_CJ_OP(c.j, x2, 0x102, 1b, x1, 12)
inst_4:
// imm_val == -130,
// opcode:c.j; immval:0x82
TEST_CJ_OP(c.j, x2, 0x82, 1b, x1, 16)
inst_5:
// imm_val == -34,
// opcode:c.j; immval:0x22
TEST_CJ_OP(c.j, x2, 0x22, 1b, x1, 20)
inst_6:
// imm_val == -18,
// opcode:c.j; immval:0x12
TEST_CJ_OP(c.j, x2, 0x12, 1b, x1, 24)
inst_7:
// imm_val == -10,
// opcode:c.j; immval:0xa
TEST_CJ_OP(c.j, x2, 0xa, 1b, x1, 28)
inst_8:
// imm_val == 1024, imm_val > 0
// opcode:c.j; immval:0x400
TEST_CJ_OP(c.j, x2, 0x400, 3f, x1, 32)
inst_9:
// imm_val == 512,
// opcode:c.j; immval:0x200
TEST_CJ_OP(c.j, x2, 0x200, 3f, x1, 36)
inst_10:
// imm_val == 1364,
// opcode:c.j; immval:0x554
TEST_CJ_OP(c.j, x2, 0x554, 3f, x1, 40)
inst_11:
// imm_val == -1366,
// opcode:c.j; immval:0x556
TEST_CJ_OP(c.j, x2, 0x556, 1b, x1, 44)
inst_12:
// imm_val == 256,
// opcode:c.j; immval:0x100
TEST_CJ_OP(c.j, x2, 0x100, 3f, x1, 48)
inst_13:
// imm_val == 128,
// opcode:c.j; immval:0x80
TEST_CJ_OP(c.j, x2, 0x80, 3f, x1, 52)
inst_14:
// imm_val == 64,
// opcode:c.j; immval:0x40
TEST_CJ_OP(c.j, x2, 0x40, 3f, x1, 56)
inst_15:
// imm_val == 32,
// opcode:c.j; immval:0x20
TEST_CJ_OP(c.j, x2, 0x20, 3f, x1, 60)
inst_16:
// imm_val == 16,
// opcode:c.j; immval:0x10
TEST_CJ_OP(c.j, x2, 0x10, 3f, x1, 64)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x1_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x1_1:
.fill 17*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
RVMODEL_DATA_END

160
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cjal-01.S
View File

@ -1,160 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Wed Aug 4 06:39:00 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.jal instruction of the RISC-V C extension for the cjal covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32EC")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*RV32.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",cjal)
RVTEST_SIGBASE( x2,signature_x2_1)
inst_0:
// imm_val < 0,
// opcode:c.jal; immval:0x10
TEST_CJAL_OP(c.jal, x3, 0x10, 1b, x2, 0)
inst_1:
// imm_val == -1026,
// opcode:c.jal; immval:0x402
TEST_CJAL_OP(c.jal, x3, 0x402, 1b, x2, 4)
inst_2:
// imm_val == -514,
// opcode:c.jal; immval:0x202
TEST_CJAL_OP(c.jal, x3, 0x202, 1b, x2, 8)
inst_3:
// imm_val == -258,
// opcode:c.jal; immval:0x102
TEST_CJAL_OP(c.jal, x3, 0x102, 1b, x2, 12)
inst_4:
// imm_val == -130,
// opcode:c.jal; immval:0x82
TEST_CJAL_OP(c.jal, x3, 0x82, 1b, x2, 16)
inst_5:
// imm_val == -66,
// opcode:c.jal; immval:0x42
TEST_CJAL_OP(c.jal, x3, 0x42, 1b, x2, 20)
inst_6:
// imm_val == -34,
// opcode:c.jal; immval:0x22
TEST_CJAL_OP(c.jal, x3, 0x22, 1b, x2, 24)
inst_7:
// imm_val == -18,
// opcode:c.jal; immval:0x12
TEST_CJAL_OP(c.jal, x3, 0x12, 1b, x2, 28)
inst_8:
// imm_val == -10,
// opcode:c.jal; immval:0xa
TEST_CJAL_OP(c.jal, x3, 0xa, 1b, x2, 32)
inst_9:
// imm_val == 1024, imm_val > 0
// opcode:c.jal; immval:0x400
TEST_CJAL_OP(c.jal, x3, 0x400, 3f, x2, 36)
inst_10:
// imm_val == 512,
// opcode:c.jal; immval:0x200
TEST_CJAL_OP(c.jal, x3, 0x200, 3f, x2, 40)
inst_11:
// imm_val == 1364,
// opcode:c.jal; immval:0x554
TEST_CJAL_OP(c.jal, x3, 0x554, 3f, x2, 44)
inst_12:
// imm_val == -1366,
// opcode:c.jal; immval:0x556
TEST_CJAL_OP(c.jal, x3, 0x556, 1b, x2, 48)
inst_13:
// imm_val == 256,
// opcode:c.jal; immval:0x100
TEST_CJAL_OP(c.jal, x3, 0x100, 3f, x2, 52)
inst_14:
// imm_val == 128,
// opcode:c.jal; immval:0x80
TEST_CJAL_OP(c.jal, x3, 0x80, 3f, x2, 56)
inst_15:
// imm_val == 64,
// opcode:c.jal; immval:0x40
TEST_CJAL_OP(c.jal, x3, 0x40, 3f, x2, 60)
inst_16:
// imm_val == 32,
// opcode:c.jal; immval:0x20
TEST_CJAL_OP(c.jal, x3, 0x20, 3f, x2, 64)
inst_17:
// imm_val == 16,
// opcode:c.jal; immval:0x10
TEST_CJAL_OP(c.jal, x3, 0x10, 3f, x2, 68)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x2_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x2_1:
.fill 18*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
RVMODEL_DATA_END

150
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cjalr-01.S
View File

@ -1,150 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Wed Aug 4 06:39:00 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.jalr instruction of the RISC-V C extension for the cjalr covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32EC")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",cjalr)
RVTEST_SIGBASE( x10,signature_x10_1)
inst_0:
// rs1==x6,
// opcode:c.jalr; op1:x6
TEST_CJALR_OP(x11, x6, x10, 0)
inst_1:
// rs1==x4,
// opcode:c.jalr; op1:x4
TEST_CJALR_OP(x11, x4, x10, 4)
inst_2:
// rs1==x3,
// opcode:c.jalr; op1:x3
TEST_CJALR_OP(x11, x3, x10, 8)
inst_3:
// rs1==x1,
// opcode:c.jalr; op1:x1
TEST_CJALR_OP(x11, x1, x10, 12)
inst_4:
// rs1==x12,
// opcode:c.jalr; op1:x12
TEST_CJALR_OP(x11, x12, x10, 16)
inst_5:
// rs1==x2,
// opcode:c.jalr; op1:x2
TEST_CJALR_OP(x11, x2, x10, 20)
inst_6:
// rs1==x8,
// opcode:c.jalr; op1:x8
TEST_CJALR_OP(x11, x8, x10, 24)
inst_7:
// rs1==x7,
// opcode:c.jalr; op1:x7
TEST_CJALR_OP(x11, x7, x10, 28)
inst_8:
// rs1==x15,
// opcode:c.jalr; op1:x15
TEST_CJALR_OP(x11, x15, x10, 32)
inst_9:
// rs1==x5,
// opcode:c.jalr; op1:x5
TEST_CJALR_OP(x11, x5, x10, 36)
inst_10:
// rs1==x9,
// opcode:c.jalr; op1:x9
TEST_CJALR_OP(x11, x9, x10, 40)
inst_11:
// rs1==x14,
// opcode:c.jalr; op1:x14
TEST_CJALR_OP(x3, x14, x10, 44)
RVTEST_SIGBASE( x2,signature_x2_0)
inst_12:
// rs1==x11,
// opcode:c.jalr; op1:x11
TEST_CJALR_OP(x3, x11, x2, 0)
inst_13:
// rs1==x13,
// opcode:c.jalr; op1:x13
TEST_CJALR_OP(x3, x13, x2, 4)
inst_14:
// rs1==x10,
// opcode:c.jalr; op1:x10
TEST_CJALR_OP(x3, x10, x2, 8)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x10_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x10_1:
.fill 12*(XLEN/32),4,0xdeadbeef
signature_x2_0:
.fill 3*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
RVMODEL_DATA_END

150
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cjr-01.S
View File

@ -1,150 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Wed Aug 4 06:39:00 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.jr instruction of the RISC-V C extension for the cjr covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32EC")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",cjr)
RVTEST_SIGBASE( x1,signature_x1_1)
inst_0:
// rs1==x6,
// opcode: c.jr; op1:x6
TEST_CJR_OP(x7, x6, x1, 0)
inst_1:
// rs1==x15,
// opcode: c.jr; op1:x15
TEST_CJR_OP(x7, x15, x1, 4)
inst_2:
// rs1==x14,
// opcode: c.jr; op1:x14
TEST_CJR_OP(x7, x14, x1, 8)
inst_3:
// rs1==x13,
// opcode: c.jr; op1:x13
TEST_CJR_OP(x7, x13, x1, 12)
inst_4:
// rs1==x3,
// opcode: c.jr; op1:x3
TEST_CJR_OP(x7, x3, x1, 16)
inst_5:
// rs1==x8,
// opcode: c.jr; op1:x8
TEST_CJR_OP(x7, x8, x1, 20)
inst_6:
// rs1==x2,
// opcode: c.jr; op1:x2
TEST_CJR_OP(x7, x2, x1, 24)
inst_7:
// rs1==x4,
// opcode: c.jr; op1:x4
TEST_CJR_OP(x7, x4, x1, 28)
inst_8:
// rs1==x12,
// opcode: c.jr; op1:x12
TEST_CJR_OP(x7, x12, x1, 32)
inst_9:
// rs1==x5,
// opcode: c.jr; op1:x5
TEST_CJR_OP(x7, x5, x1, 36)
inst_10:
// rs1==x7,
// opcode: c.jr; op1:x7
TEST_CJR_OP(x3, x7, x1, 40)
RVTEST_SIGBASE( x2,signature_x2_0)
inst_11:
// rs1==x9,
// opcode: c.jr; op1:x9
TEST_CJR_OP(x3, x9, x2, 0)
inst_12:
// rs1==x1,
// opcode: c.jr; op1:x1
TEST_CJR_OP(x3, x1, x2, 4)
inst_13:
// rs1==x11,
// opcode: c.jr; op1:x11
TEST_CJR_OP(x3, x11, x2, 8)
inst_14:
// rs1==x10,
// opcode: c.jr; op1:x10
TEST_CJR_OP(x3, x10, x2, 12)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x1_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x1_1:
.fill 11*(XLEN/32),4,0xdeadbeef
signature_x2_0:
.fill 4*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
RVMODEL_DATA_END

160
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cli-01.S
View File

@ -1,160 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Wed Aug 4 06:39:00 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.li instruction of the RISC-V C extension for the cli covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32EC")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",cli)
RVTEST_SIGBASE( x4,signature_x4_1)
inst_0:
// rd==x15, imm_val == (-2**(6-1)), imm_val == -32
// opcode:c.li; dest:x15; immval:-0x20
TEST_CASE(x7, x15, -0x20, x4, 0, c.li x15, -0x20;)
inst_1:
// rd==x8, imm_val == 31, imm_val == (2**(6-1)-1)
// opcode:c.li; dest:x8; immval:0x1f
TEST_CASE(x7, x8, 0x1f, x4, 4, c.li x8, 0x1f;)
inst_2:
// rd==x13, imm_val == -17,
// opcode:c.li; dest:x13; immval:-0x11
TEST_CASE(x7, x13, -0x11, x4, 8, c.li x13, -0x11;)
inst_3:
// rd==x6, imm_val == -9,
// opcode:c.li; dest:x6; immval:-0x9
TEST_CASE(x7, x6, -0x9, x4, 12, c.li x6, -0x9;)
inst_4:
// rd==x2, imm_val == -5,
// opcode:c.li; dest:x2; immval:-0x5
TEST_CASE(x7, x2, -0x5, x4, 16, c.li x2, -0x5;)
inst_5:
// rd==x12, imm_val == -3,
// opcode:c.li; dest:x12; immval:-0x3
TEST_CASE(x7, x12, -0x3, x4, 20, c.li x12, -0x3;)
inst_6:
// rd==x1, imm_val == -2,
// opcode:c.li; dest:x1; immval:-0x2
TEST_CASE(x7, x1, -0x2, x4, 24, c.li x1, -0x2;)
inst_7:
// rd==x14, imm_val == 16,
// opcode:c.li; dest:x14; immval:0x10
TEST_CASE(x7, x14, 0x10, x4, 28, c.li x14, 0x10;)
inst_8:
// rd==x3, imm_val == 0,
// opcode:c.li; dest:x3; immval:0x0
TEST_CASE(x7, x3, 0x0, x4, 32, c.li x3, 0x0;)
inst_9:
// rd==x5, imm_val == 8,
// opcode:c.li; dest:x5; immval:0x8
TEST_CASE(x7, x5, 0x8, x4, 36, c.li x5, 0x8;)
inst_10:
// rd==x10, imm_val == 4,
// opcode:c.li; dest:x10; immval:0x4
TEST_CASE(x7, x10, 0x4, x4, 40, c.li x10, 0x4;)
inst_11:
// rd==x0, imm_val == 2,
// opcode:c.li; dest:x0; immval:0x2
TEST_CASE(x2, x0, 0, x4, 44, c.li x0, 0x2;)
inst_12:
// rd==x11, imm_val == 1,
// opcode:c.li; dest:x11; immval:0x1
TEST_CASE(x2, x11, 0x1, x4, 48, c.li x11, 0x1;)
RVTEST_SIGBASE( x1,signature_x1_0)
inst_13:
// rd==x7, imm_val == -22,
// opcode:c.li; dest:x7; immval:-0x16
TEST_CASE(x2, x7, -0x16, x1, 0, c.li x7, -0x16;)
inst_14:
// rd==x4, imm_val == 21,
// opcode:c.li; dest:x4; immval:0x15
TEST_CASE(x2, x4, 0x15, x1, 4, c.li x4, 0x15;)
inst_15:
// rd==x9,
// opcode:c.li; dest:x9; immval:0x0
TEST_CASE(x2, x9, 0x0, x1, 8, c.li x9, 0x0;)
inst_16:
// imm_val == 2,
// opcode:c.li; dest:x10; immval:0x2
TEST_CASE(x2, x10, 0x2, x1, 12, c.li x10, 0x2;)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x4_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x4_1:
.fill 13*(XLEN/32),4,0xdeadbeef
signature_x1_0:
.fill 4*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
RVMODEL_DATA_END

150
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/clui-01.S
View File

@ -1,150 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Wed Aug 4 06:39:00 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.lui instruction of the RISC-V C extension for the clui covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32EC")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",clui)
RVTEST_SIGBASE( x2,signature_x2_1)
inst_0:
// rd==x8, rs1_val < 0 and imm_val < 32 and imm_val !=0 , imm_val == 4
// opcode:c.lui; op1:x8; dest:x8 op1val:-0x1000001; immval:0x4
TEST_CI_OP( c.lui, x8, 0x4000, -0x1000001, 0x4, x2, 0, x5)
inst_1:
// rd==x10, imm_val == 31,
// opcode:c.lui; op1:x10; dest:x10 op1val:-0x4; immval:0x1f
TEST_CI_OP( c.lui, x10, 0x1f000, -0x4, 0x1f, x2, 4, x5)
inst_2:
// rd==x6, imm_val == 47, rs1_val > 0 and imm_val > 32
// opcode:c.lui; op1:x6; dest:x6 op1val:0x4000; immval:0xfffef
TEST_CI_OP( c.lui, x6, -0x11000, 0x4000, 0xfffef, x2, 8, x5)
inst_3:
// rd==x9, imm_val == 55, rs1_val < 0 and imm_val > 32
// opcode:c.lui; op1:x9; dest:x9 op1val:-0x3; immval:0xffff7
TEST_CI_OP( c.lui, x9, -0x9000, -0x3, 0xffff7, x2, 12, x5)
inst_4:
// rd==x15, imm_val == 59,
// opcode:c.lui; op1:x15; dest:x15 op1val:0x4; immval:0xffffb
TEST_CI_OP( c.lui, x15, -0x5000, 0x4, 0xffffb, x2, 16, x5)
inst_5:
// rd==x1, imm_val == 61,
// opcode:c.lui; op1:x1; dest:x1 op1val:-0x20000001; immval:0xffffd
TEST_CI_OP( c.lui, x1, -0x3000, -0x20000001, 0xffffd, x2, 20, x5)
inst_6:
// rd==x0, imm_val == 62,
// opcode:c.lui; op1:x0; dest:x0 op1val:-0x20000001; immval:0xffffe
TEST_CI_OP( c.lui, x0, 0, -0x20000001, 0xffffe, x2, 24, x5)
inst_7:
// rd==x7, imm_val == 32,
// opcode:c.lui; op1:x7; dest:x7 op1val:0x4000; immval:0xfffe0
TEST_CI_OP( c.lui, x7, -0x20000, 0x4000, 0xfffe0, x2, 28, x5)
inst_8:
// rd==x3, rs1_val > 0 and imm_val < 32 and imm_val !=0 ,
// opcode:c.lui; op1:x3; dest:x3 op1val:0x10; immval:0xc
TEST_CI_OP( c.lui, x3, 0xc000, 0x10, 0xc, x2, 32, x5)
inst_9:
// rd==x4, imm_val == 16,
// opcode:c.lui; op1:x4; dest:x4 op1val:0x7fffffff; immval:0x10
TEST_CI_OP( c.lui, x4, 0x10000, 0x7fffffff, 0x10, x2, 36, x5)
inst_10:
// rd==x11, imm_val == 8,
// opcode:c.lui; op1:x11; dest:x11 op1val:-0x20001; immval:0x8
TEST_CI_OP( c.lui, x11, 0x8000, -0x20001, 0x8, x2, 40, x5)
inst_11:
// rd==x12, imm_val == 2,
// opcode:c.lui; op1:x12; dest:x12 op1val:0x200000; immval:0x2
TEST_CI_OP( c.lui, x12, 0x2000, 0x200000, 0x2, x2, 44, x5)
inst_12:
// rd==x13, imm_val == 1,
// opcode:c.lui; op1:x13; dest:x13 op1val:-0x2001; immval:0x1
TEST_CI_OP( c.lui, x13, 0x1000, -0x2001, 0x1, x2, 48, x3)
RVTEST_SIGBASE( x1,signature_x1_0)
inst_13:
// rd==x14, imm_val == 42,
// opcode:c.lui; op1:x14; dest:x14 op1val:0x400000; immval:0xfffea
TEST_CI_OP( c.lui, x14, -0x16000, 0x400000, 0xfffea, x1, 0, x3)
inst_14:
// rd==x5, imm_val == 21,
// opcode:c.lui; op1:x5; dest:x5 op1val:-0x10001; immval:0x15
TEST_CI_OP( c.lui, x5, 0x15000, -0x10001, 0x15, x1, 4, x3)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x2_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x2_1:
.fill 13*(XLEN/32),4,0xdeadbeef
signature_x1_0:
.fill 2*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
RVMODEL_DATA_END

135
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/clw-01.S
View File

@ -1,135 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Wed Aug 4 06:39:00 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.lw instruction of the RISC-V C extension for the clw covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32EC")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",clw)
RVTEST_SIGBASE( x1,signature_x1_1)
inst_0:
// rs1 == rd, rd==x8, rs1==x8, imm_val == 0,
// opcode: c.lw; op1:x8; dest:x8; immval:0x0
TEST_LOAD(x1,x2,0,x8,x8,0x0,0,c.lw,0)
inst_1:
// rs1 != rd, rd==x14, rs1==x12, imm_val == 60, imm_val > 0
// opcode: c.lw; op1:x12; dest:x14; immval:0x3c
TEST_LOAD(x1,x2,0,x12,x14,0x3c,4,c.lw,0)
inst_2:
// rd==x15, rs1==x11, imm_val == 92,
// opcode: c.lw; op1:x11; dest:x15; immval:0x5c
TEST_LOAD(x1,x2,0,x11,x15,0x5c,8,c.lw,0)
inst_3:
// rd==x10, rs1==x15, imm_val == 108,
// opcode: c.lw; op1:x15; dest:x10; immval:0x6c
TEST_LOAD(x1,x2,0,x15,x10,0x6c,12,c.lw,0)
inst_4:
// rd==x13, rs1==x14, imm_val == 116,
// opcode: c.lw; op1:x14; dest:x13; immval:0x74
TEST_LOAD(x1,x2,0,x14,x13,0x74,16,c.lw,0)
inst_5:
// rd==x11, rs1==x13, imm_val == 120,
// opcode: c.lw; op1:x13; dest:x11; immval:0x78
TEST_LOAD(x1,x2,0,x13,x11,0x78,20,c.lw,0)
inst_6:
// rd==x12, rs1==x10, imm_val == 64,
// opcode: c.lw; op1:x10; dest:x12; immval:0x40
TEST_LOAD(x1,x2,0,x10,x12,0x40,24,c.lw,0)
inst_7:
// rd==x9, imm_val == 32,
// opcode: c.lw; op1:x10; dest:x9; immval:0x20
TEST_LOAD(x1,x2,0,x10,x9,0x20,28,c.lw,0)
inst_8:
// rs1==x9, imm_val == 16,
// opcode: c.lw; op1:x9; dest:x8; immval:0x10
TEST_LOAD(x1,x2,0,x9,x8,0x10,32,c.lw,0)
inst_9:
// imm_val == 8,
// opcode: c.lw; op1:x11; dest:x10; immval:0x8
TEST_LOAD(x1,x2,0,x11,x10,0x8,36,c.lw,0)
inst_10:
// imm_val == 4,
// opcode: c.lw; op1:x11; dest:x10; immval:0x4
TEST_LOAD(x1,x2,0,x11,x10,0x4,40,c.lw,0)
inst_11:
// imm_val == 40,
// opcode: c.lw; op1:x11; dest:x10; immval:0x28
TEST_LOAD(x1,x2,0,x11,x10,0x28,44,c.lw,0)
inst_12:
// imm_val == 84,
// opcode: c.lw; op1:x11; dest:x10; immval:0x54
TEST_LOAD(x1,x2,0,x11,x10,0x54,48,c.lw,0)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x1_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x1_1:
.fill 13*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
RVMODEL_DATA_END

150
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/clwsp-01.S
View File

@ -1,150 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Wed Aug 4 06:39:00 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.lwsp instruction of the RISC-V C extension for the clwsp covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32EC")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",clwsp)
RVTEST_SIGBASE( x5,signature_x5_1)
inst_0:
// rd==x2, imm_val == 0,
// opcode: c.lwsp; op1:x2; dest:x2; immval:0x0
TEST_LOAD(x5,x7,0,x2,x2,0x0,0,c.lwsp,0)
inst_1:
// rd==x11, imm_val == 124, imm_val > 0
// opcode: c.lwsp; op1:x2; dest:x11; immval:0x7c
TEST_LOAD(x5,x7,0,x2,x11,0x7c,4,c.lwsp,0)
inst_2:
// rd==x3, imm_val == 188,
// opcode: c.lwsp; op1:x2; dest:x3; immval:0xbc
TEST_LOAD(x5,x7,0,x2,x3,0xbc,8,c.lwsp,0)
inst_3:
// rd==x6, imm_val == 220,
// opcode: c.lwsp; op1:x2; dest:x6; immval:0xdc
TEST_LOAD(x5,x7,0,x2,x6,0xdc,12,c.lwsp,0)
inst_4:
// rd==x9, imm_val == 236,
// opcode: c.lwsp; op1:x2; dest:x9; immval:0xec
TEST_LOAD(x5,x7,0,x2,x9,0xec,16,c.lwsp,0)
inst_5:
// rd==x1, imm_val == 244,
// opcode: c.lwsp; op1:x2; dest:x1; immval:0xf4
TEST_LOAD(x5,x7,0,x2,x1,0xf4,20,c.lwsp,0)
inst_6:
// rd==x4, imm_val == 248,
// opcode: c.lwsp; op1:x2; dest:x4; immval:0xf8
TEST_LOAD(x5,x7,0,x2,x4,0xf8,24,c.lwsp,0)
inst_7:
// rd==x8, imm_val == 128,
// opcode: c.lwsp; op1:x2; dest:x8; immval:0x80
TEST_LOAD(x5,x7,0,x2,x8,0x80,28,c.lwsp,0)
inst_8:
// rd==x15, imm_val == 64,
// opcode: c.lwsp; op1:x2; dest:x15; immval:0x40
TEST_LOAD(x5,x7,0,x2,x15,0x40,32,c.lwsp,0)
inst_9:
// rd==x12, imm_val == 32,
// opcode: c.lwsp; op1:x2; dest:x12; immval:0x20
TEST_LOAD(x5,x7,0,x2,x12,0x20,36,c.lwsp,0)
inst_10:
// rd==x10, imm_val == 16,
// opcode: c.lwsp; op1:x2; dest:x10; immval:0x10
TEST_LOAD(x5,x7,0,x2,x10,0x10,40,c.lwsp,0)
inst_11:
// rd==x14, imm_val == 8,
// opcode: c.lwsp; op1:x2; dest:x14; immval:0x8
TEST_LOAD(x5,x3,0,x2,x14,0x8,44,c.lwsp,0)
RVTEST_SIGBASE( x1,signature_x1_0)
inst_12:
// rd==x13, imm_val == 4,
// opcode: c.lwsp; op1:x2; dest:x13; immval:0x4
TEST_LOAD(x1,x3,0,x2,x13,0x4,0,c.lwsp,0)
inst_13:
// rd==x5, imm_val == 168,
// opcode: c.lwsp; op1:x2; dest:x5; immval:0xa8
TEST_LOAD(x1,x3,0,x2,x5,0xa8,4,c.lwsp,0)
inst_14:
// rd==x7, imm_val == 84,
// opcode: c.lwsp; op1:x2; dest:x7; immval:0x54
TEST_LOAD(x1,x3,0,x2,x7,0x54,8,c.lwsp,0)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x5_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x5_1:
.fill 12*(XLEN/32),4,0xdeadbeef
signature_x1_0:
.fill 3*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
RVMODEL_DATA_END

500
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cmv-01.S
View File

@ -1,500 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Wed Aug 4 06:39:00 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.mv instruction of the RISC-V C extension for the cmv covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32EC")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",cmv)
RVTEST_SIGBASE( x4,signature_x4_1)
inst_0:
// rs2 == rd and rs2 != 0, rd==x13, rs2==x13, rs2_val == (-2**(xlen-1)), rs2_val == -2147483648
// opcode: c.mv; op2:x13; dest:x13; op2val:-0x80000000
TEST_CMV_OP( c.mv, x13, x13, -0x80000000, -0x80000000, x4, 0, x10)
inst_1:
// rs2 != rd and rs2 != 0, rd==x3, rs2==x14, rs2_val == 2147483647, rs2_val == (2**(xlen-1)-1)
// opcode: c.mv; op2:x14; dest:x3; op2val:0x7fffffff
TEST_CMV_OP( c.mv, x3, x14, 0x7fffffff, 0x7fffffff, x4, 4, x10)
inst_2:
// rd==x15, rs2==x5, rs2_val == -1073741825,
// opcode: c.mv; op2:x5; dest:x15; op2val:-0x40000001
TEST_CMV_OP( c.mv, x15, x5, -0x40000001, -0x40000001, x4, 8, x10)
inst_3:
// rd==x6, rs2==x2, rs2_val == -536870913,
// opcode: c.mv; op2:x2; dest:x6; op2val:-0x20000001
TEST_CMV_OP( c.mv, x6, x2, -0x20000001, -0x20000001, x4, 12, x10)
inst_4:
// rd==x9, rs2==x7, rs2_val == -268435457,
// opcode: c.mv; op2:x7; dest:x9; op2val:-0x10000001
TEST_CMV_OP( c.mv, x9, x7, -0x10000001, -0x10000001, x4, 16, x10)
inst_5:
// rd==x2, rs2==x11, rs2_val == -134217729,
// opcode: c.mv; op2:x11; dest:x2; op2val:-0x8000001
TEST_CMV_OP( c.mv, x2, x11, -0x8000001, -0x8000001, x4, 20, x10)
inst_6:
// rd==x5, rs2==x15, rs2_val == -67108865,
// opcode: c.mv; op2:x15; dest:x5; op2val:-0x4000001
TEST_CMV_OP( c.mv, x5, x15, -0x4000001, -0x4000001, x4, 24, x10)
inst_7:
// rd==x11, rs2==x9, rs2_val == -33554433,
// opcode: c.mv; op2:x9; dest:x11; op2val:-0x2000001
TEST_CMV_OP( c.mv, x11, x9, -0x2000001, -0x2000001, x4, 28, x10)
inst_8:
// rd==x1, rs2==x8, rs2_val == -16777217,
// opcode: c.mv; op2:x8; dest:x1; op2val:-0x1000001
TEST_CMV_OP( c.mv, x1, x8, -0x1000001, -0x1000001, x4, 32, x10)
RVTEST_SIGBASE( x2,signature_x2_0)
inst_9:
// rd==x7, rs2==x6, rs2_val == -8388609,
// opcode: c.mv; op2:x6; dest:x7; op2val:-0x800001
TEST_CMV_OP( c.mv, x7, x6, -0x800001, -0x800001, x2, 0, x5)
inst_10:
// rd==x12, rs2==x1, rs2_val == -4194305,
// opcode: c.mv; op2:x1; dest:x12; op2val:-0x400001
TEST_CMV_OP( c.mv, x12, x1, -0x400001, -0x400001, x2, 4, x5)
inst_11:
// rd==x14, rs2==x4, rs2_val == -2097153,
// opcode: c.mv; op2:x4; dest:x14; op2val:-0x200001
TEST_CMV_OP( c.mv, x14, x4, -0x200001, -0x200001, x2, 8, x5)
inst_12:
// rd==x10, rs2==x12, rs2_val == -1048577,
// opcode: c.mv; op2:x12; dest:x10; op2val:-0x100001
TEST_CMV_OP( c.mv, x10, x12, -0x100001, -0x100001, x2, 12, x5)
inst_13:
// rd==x8, rs2==x3, rs2_val == -524289,
// opcode: c.mv; op2:x3; dest:x8; op2val:-0x80001
TEST_CMV_OP( c.mv, x8, x3, -0x80001, -0x80001, x2, 16, x5)
inst_14:
// rd==x0, rs2==x10, rs2_val == -262145,
// opcode: c.mv; op2:x10; dest:x0; op2val:-0x40001
TEST_CMV_OP( c.mv, x0, x10, 0, -0x40001, x2, 20, x5)
inst_15:
// rd==x4, rs2_val == -131073,
// opcode: c.mv; op2:x12; dest:x4; op2val:-0x20001
TEST_CMV_OP( c.mv, x4, x12, -0x20001, -0x20001, x2, 24, x5)
inst_16:
// rs2_val == -65537,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0x10001
TEST_CMV_OP( c.mv, x10, x11, -0x10001, -0x10001, x2, 28, x5)
inst_17:
// rs2_val == -32769,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0x8001
TEST_CMV_OP( c.mv, x10, x11, -0x8001, -0x8001, x2, 32, x5)
inst_18:
// rs2_val == -16385,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0x4001
TEST_CMV_OP( c.mv, x10, x11, -0x4001, -0x4001, x2, 36, x5)
inst_19:
// rs2_val == -8193,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0x2001
TEST_CMV_OP( c.mv, x10, x11, -0x2001, -0x2001, x2, 40, x5)
inst_20:
// rs2_val == -4097,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0x1001
TEST_CMV_OP( c.mv, x10, x11, -0x1001, -0x1001, x2, 44, x5)
inst_21:
// rs2_val == -2049,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0x801
TEST_CMV_OP( c.mv, x10, x11, -0x801, -0x801, x2, 48, x5)
inst_22:
// rs2_val == -1025,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0x401
TEST_CMV_OP( c.mv, x10, x11, -0x401, -0x401, x2, 52, x5)
inst_23:
// rs2_val == -513,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0x201
TEST_CMV_OP( c.mv, x10, x11, -0x201, -0x201, x2, 56, x5)
inst_24:
// rs2_val == -257,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0x101
TEST_CMV_OP( c.mv, x10, x11, -0x101, -0x101, x2, 60, x5)
inst_25:
// rs2_val == -129,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0x81
TEST_CMV_OP( c.mv, x10, x11, -0x81, -0x81, x2, 64, x5)
inst_26:
// rs2_val == -65,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0x41
TEST_CMV_OP( c.mv, x10, x11, -0x41, -0x41, x2, 68, x5)
inst_27:
// rs2_val == -33,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0x21
TEST_CMV_OP( c.mv, x10, x11, -0x21, -0x21, x2, 72, x5)
inst_28:
// rs2_val == -17,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0x11
TEST_CMV_OP( c.mv, x10, x11, -0x11, -0x11, x2, 76, x5)
inst_29:
// rs2_val == -9,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0x9
TEST_CMV_OP( c.mv, x10, x11, -0x9, -0x9, x2, 80, x5)
inst_30:
// rs2_val == -5,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0x5
TEST_CMV_OP( c.mv, x10, x11, -0x5, -0x5, x2, 84, x5)
inst_31:
// rs2_val == -3,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0x3
TEST_CMV_OP( c.mv, x10, x11, -0x3, -0x3, x2, 88, x5)
inst_32:
// rs2_val == -2,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0x2
TEST_CMV_OP( c.mv, x10, x11, -0x2, -0x2, x2, 92, x5)
inst_33:
// rs2_val == 1073741824,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x40000000
TEST_CMV_OP( c.mv, x10, x11, 0x40000000, 0x40000000, x2, 96, x5)
inst_34:
// rs2_val == 536870912,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x20000000
TEST_CMV_OP( c.mv, x10, x11, 0x20000000, 0x20000000, x2, 100, x5)
inst_35:
// rs2_val == 268435456,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x10000000
TEST_CMV_OP( c.mv, x10, x11, 0x10000000, 0x10000000, x2, 104, x5)
inst_36:
// rs2_val == 134217728,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x8000000
TEST_CMV_OP( c.mv, x10, x11, 0x8000000, 0x8000000, x2, 108, x5)
inst_37:
// rs2_val == 67108864,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x4000000
TEST_CMV_OP( c.mv, x10, x11, 0x4000000, 0x4000000, x2, 112, x5)
inst_38:
// rs2_val == 33554432,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x2000000
TEST_CMV_OP( c.mv, x10, x11, 0x2000000, 0x2000000, x2, 116, x5)
inst_39:
// rs2_val == 16777216,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x1000000
TEST_CMV_OP( c.mv, x10, x11, 0x1000000, 0x1000000, x2, 120, x5)
inst_40:
// rs2_val == 8388608,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x800000
TEST_CMV_OP( c.mv, x10, x11, 0x800000, 0x800000, x2, 124, x5)
inst_41:
// rs2_val == 4194304,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x400000
TEST_CMV_OP( c.mv, x10, x11, 0x400000, 0x400000, x2, 128, x5)
inst_42:
// rs2_val == 2097152,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x200000
TEST_CMV_OP( c.mv, x10, x11, 0x200000, 0x200000, x2, 132, x5)
inst_43:
// rs2_val == 1048576,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x100000
TEST_CMV_OP( c.mv, x10, x11, 0x100000, 0x100000, x2, 136, x5)
inst_44:
// rs2_val == 524288,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x80000
TEST_CMV_OP( c.mv, x10, x11, 0x80000, 0x80000, x2, 140, x5)
inst_45:
// rs2_val == 262144,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x40000
TEST_CMV_OP( c.mv, x10, x11, 0x40000, 0x40000, x2, 144, x5)
inst_46:
// rs2_val == 131072,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x20000
TEST_CMV_OP( c.mv, x10, x11, 0x20000, 0x20000, x2, 148, x5)
inst_47:
// rs2_val == 65536,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x10000
TEST_CMV_OP( c.mv, x10, x11, 0x10000, 0x10000, x2, 152, x5)
inst_48:
// rs2_val == 32768,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x8000
TEST_CMV_OP( c.mv, x10, x11, 0x8000, 0x8000, x2, 156, x5)
inst_49:
// rs2_val == 16384,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x4000
TEST_CMV_OP( c.mv, x10, x11, 0x4000, 0x4000, x2, 160, x5)
inst_50:
// rs2_val == 8192,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x2000
TEST_CMV_OP( c.mv, x10, x11, 0x2000, 0x2000, x2, 164, x5)
inst_51:
// rs2_val == 4096,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x1000
TEST_CMV_OP( c.mv, x10, x11, 0x1000, 0x1000, x2, 168, x5)
inst_52:
// rs2_val == 2048,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x800
TEST_CMV_OP( c.mv, x10, x11, 0x800, 0x800, x2, 172, x5)
inst_53:
// rs2_val == 1024,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x400
TEST_CMV_OP( c.mv, x10, x11, 0x400, 0x400, x2, 176, x5)
inst_54:
// rs2_val == 512,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x200
TEST_CMV_OP( c.mv, x10, x11, 0x200, 0x200, x2, 180, x5)
inst_55:
// rs2_val == 256,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x100
TEST_CMV_OP( c.mv, x10, x11, 0x100, 0x100, x2, 184, x5)
inst_56:
// rs2_val == 128,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x80
TEST_CMV_OP( c.mv, x10, x11, 0x80, 0x80, x2, 188, x5)
inst_57:
// rs2_val == 64,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x40
TEST_CMV_OP( c.mv, x10, x11, 0x40, 0x40, x2, 192, x5)
inst_58:
// rs2_val == 1,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x1
TEST_CMV_OP( c.mv, x10, x11, 0x1, 0x1, x2, 196, x5)
inst_59:
// rs2_val==46341,
// opcode: c.mv; op2:x11; dest:x10; op2val:0xb505
TEST_CMV_OP( c.mv, x10, x11, 0xb505, 0xb505, x2, 200, x5)
inst_60:
// rs2_val==-46339,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0xb503
TEST_CMV_OP( c.mv, x10, x11, -0xb503, -0xb503, x2, 204, x5)
inst_61:
// rs2_val==1717986919,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x66666667
TEST_CMV_OP( c.mv, x10, x11, 0x66666667, 0x66666667, x2, 208, x5)
inst_62:
// rs2_val==858993460,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x33333334
TEST_CMV_OP( c.mv, x10, x11, 0x33333334, 0x33333334, x2, 212, x5)
inst_63:
// rs2_val==6,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x6
TEST_CMV_OP( c.mv, x10, x11, 0x6, 0x6, x2, 216, x5)
inst_64:
// rs2_val==-1431655765,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0x55555555
TEST_CMV_OP( c.mv, x10, x11, -0x55555555, -0x55555555, x2, 220, x5)
inst_65:
// rs2_val==1431655766,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x55555556
TEST_CMV_OP( c.mv, x10, x11, 0x55555556, 0x55555556, x2, 224, x5)
inst_66:
// rs2_val==4, rs2_val == 4
// opcode: c.mv; op2:x11; dest:x10; op2val:0x4
TEST_CMV_OP( c.mv, x10, x11, 0x4, 0x4, x2, 228, x5)
inst_67:
// rs2_val==46339,
// opcode: c.mv; op2:x11; dest:x10; op2val:0xb503
TEST_CMV_OP( c.mv, x10, x11, 0xb503, 0xb503, x2, 232, x5)
inst_68:
// rs2_val==0, rs2_val == 0
// opcode: c.mv; op2:x11; dest:x10; op2val:0x0
TEST_CMV_OP( c.mv, x10, x11, 0x0, 0x0, x2, 236, x5)
inst_69:
// rs2_val==1717986917,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x66666665
TEST_CMV_OP( c.mv, x10, x11, 0x66666665, 0x66666665, x2, 240, x5)
inst_70:
// rs2_val==858993458,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x33333332
TEST_CMV_OP( c.mv, x10, x11, 0x33333332, 0x33333332, x2, 244, x5)
inst_71:
// rs2_val==1431655764,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x55555554
TEST_CMV_OP( c.mv, x10, x11, 0x55555554, 0x55555554, x2, 248, x5)
inst_72:
// rs2_val==2, rs2_val == 2
// opcode: c.mv; op2:x11; dest:x10; op2val:0x2
TEST_CMV_OP( c.mv, x10, x11, 0x2, 0x2, x2, 252, x5)
inst_73:
// rs2_val==46340,
// opcode: c.mv; op2:x11; dest:x10; op2val:0xb504
TEST_CMV_OP( c.mv, x10, x11, 0xb504, 0xb504, x2, 256, x5)
inst_74:
// rs2_val==-46340,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0xb504
TEST_CMV_OP( c.mv, x10, x11, -0xb504, -0xb504, x2, 260, x5)
inst_75:
// rs2_val==1717986918,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x66666666
TEST_CMV_OP( c.mv, x10, x11, 0x66666666, 0x66666666, x2, 264, x5)
inst_76:
// rs2_val==858993459,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x33333333
TEST_CMV_OP( c.mv, x10, x11, 0x33333333, 0x33333333, x2, 268, x5)
inst_77:
// rs2_val==5,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x5
TEST_CMV_OP( c.mv, x10, x11, 0x5, 0x5, x2, 272, x5)
inst_78:
// rs2_val==-1431655766, rs2_val == -1431655766
// opcode: c.mv; op2:x11; dest:x10; op2val:-0x55555556
TEST_CMV_OP( c.mv, x10, x11, -0x55555556, -0x55555556, x2, 276, x5)
inst_79:
// rs2_val==1431655765, rs2_val == 1431655765
// opcode: c.mv; op2:x11; dest:x10; op2val:0x55555555
TEST_CMV_OP( c.mv, x10, x11, 0x55555555, 0x55555555, x2, 280, x5)
inst_80:
// rs2_val == 32,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x20
TEST_CMV_OP( c.mv, x10, x11, 0x20, 0x20, x2, 284, x5)
inst_81:
// rs2_val == 16,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x10
TEST_CMV_OP( c.mv, x10, x11, 0x10, 0x10, x2, 288, x5)
inst_82:
// rs2_val == 8,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x8
TEST_CMV_OP( c.mv, x10, x11, 0x8, 0x8, x2, 292, x5)
inst_83:
// rs2_val==3,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x3
TEST_CMV_OP( c.mv, x10, x11, 0x3, 0x3, x2, 296, x5)
inst_84:
// rs2_val == -262145,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0x40001
TEST_CMV_OP( c.mv, x10, x11, -0x40001, -0x40001, x2, 300, x5)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x4_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x4_1:
.fill 9*(XLEN/32),4,0xdeadbeef
signature_x2_0:
.fill 76*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
RVMODEL_DATA_END

140
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cnop-01.S
View File

@ -1,140 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Wed Aug 4 06:39:00 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.nop instruction of the RISC-V C extension for the cnop covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32EC")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",cnop)
RVTEST_SIGBASE( x1,signature_x1_1)
inst_0:
// imm_val == 21,
// opcode:c.nop; immval:0x15
TEST_CNOP_OP(c.nop, x2, 0x15, x1, 0)
inst_1:
// imm_val == 31,
// opcode:c.nop; immval:0x1f
TEST_CNOP_OP(c.nop, x2, 0x1f, x1, 4)
inst_2:
// imm_val == -17,
// opcode:c.nop; immval:-0x11
TEST_CNOP_OP(c.nop, x2, -0x11, x1, 8)
inst_3:
// imm_val == -9,
// opcode:c.nop; immval:-0x9
TEST_CNOP_OP(c.nop, x2, -0x9, x1, 12)
inst_4:
// imm_val == -5,
// opcode:c.nop; immval:-0x5
TEST_CNOP_OP(c.nop, x2, -0x5, x1, 16)
inst_5:
// imm_val == -3,
// opcode:c.nop; immval:-0x3
TEST_CNOP_OP(c.nop, x2, -0x3, x1, 20)
inst_6:
// imm_val == -2,
// opcode:c.nop; immval:-0x2
TEST_CNOP_OP(c.nop, x2, -0x2, x1, 24)
inst_7:
// imm_val == -32,
// opcode:c.nop; immval:-0x20
TEST_CNOP_OP(c.nop, x2, -0x20, x1, 28)
inst_8:
// imm_val == 16,
// opcode:c.nop; immval:0x10
TEST_CNOP_OP(c.nop, x2, 0x10, x1, 32)
inst_9:
// imm_val == 8,
// opcode:c.nop; immval:0x8
TEST_CNOP_OP(c.nop, x2, 0x8, x1, 36)
inst_10:
// imm_val == 4,
// opcode:c.nop; immval:0x4
TEST_CNOP_OP(c.nop, x2, 0x4, x1, 40)
inst_11:
// imm_val == 2,
// opcode:c.nop; immval:0x2
TEST_CNOP_OP(c.nop, x2, 0x2, x1, 44)
inst_12:
// imm_val == 1,
// opcode:c.nop; immval:0x1
TEST_CNOP_OP(c.nop, x2, 0x1, x1, 48)
inst_13:
// imm_val == -22,
// opcode:c.nop; immval:-0x16
TEST_CNOP_OP(c.nop, x2, -0x16, x1, 52)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x1_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x1_1:
.fill 14*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
RVMODEL_DATA_END

2985
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cor-01.S
View File

File diff suppressed because it is too large Load Diff

500
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cslli-01.S
View File

@ -1,500 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Wed Aug 4 06:39:00 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.slli instruction of the RISC-V C extension for the cslli covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32EC")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",cslli)
RVTEST_SIGBASE( x1,signature_x1_1)
inst_0:
// rd==x11, rs1_val < 0 and imm_val < xlen, rs1_val == -65537, imm_val == 29
// opcode:c.slli; op1:x11; dest:x11 op1val:-0x10001; immval:0x1d
TEST_CI_OP( c.slli, x11, 0xe0000000, -0x10001, 0x1d, x1, 0, x2)
inst_1:
// rd==x8, rs1_val == 2147483647, rs1_val > 0 and imm_val < xlen, rs1_val == (2**(xlen-1)-1) and imm_val != 0 and imm_val < xlen
// opcode:c.slli; op1:x8; dest:x8 op1val:0x7fffffff; immval:0xb
TEST_CI_OP( c.slli, x8, 0xfffff800, 0x7fffffff, 0xb, x1, 4, x2)
inst_2:
// rd==x9, rs1_val == -1073741825,
// opcode:c.slli; op1:x9; dest:x9 op1val:-0x40000001; immval:0xc
TEST_CI_OP( c.slli, x9, 0xfffff000, -0x40000001, 0xc, x1, 8, x2)
inst_3:
// rd==x12, rs1_val == -536870913,
// opcode:c.slli; op1:x12; dest:x12 op1val:-0x20000001; immval:0x7
TEST_CI_OP( c.slli, x12, 0xffffff80, -0x20000001, 0x7, x1, 12, x2)
inst_4:
// rd==x14, rs1_val == -268435457,
// opcode:c.slli; op1:x14; dest:x14 op1val:-0x10000001; immval:0x3
TEST_CI_OP( c.slli, x14, 0x7ffffff8, -0x10000001, 0x3, x1, 16, x2)
inst_5:
// rd==x10, rs1_val == -134217729,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x8000001; immval:0x1f
TEST_CI_OP( c.slli, x10, 0x80000000, -0x8000001, 0x1f, x1, 20, x2)
inst_6:
// rd==x13, rs1_val == -67108865,
// opcode:c.slli; op1:x13; dest:x13 op1val:-0x4000001; immval:0x13
TEST_CI_OP( c.slli, x13, 0xfff80000, -0x4000001, 0x13, x1, 24, x2)
inst_7:
// rd==x15, rs1_val == -33554433, imm_val == 10
// opcode:c.slli; op1:x15; dest:x15 op1val:-0x2000001; immval:0xa
TEST_CI_OP( c.slli, x15, 0xfffffc00, -0x2000001, 0xa, x1, 28, x2)
inst_8:
// rs1_val == -16777217,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x1000001; immval:0x5
TEST_CI_OP( c.slli, x10, 0xdfffffe0, -0x1000001, 0x5, x1, 32, x2)
inst_9:
// rs1_val == -8388609,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x800001; immval:0x1f
TEST_CI_OP( c.slli, x10, 0x80000000, -0x800001, 0x1f, x1, 36, x2)
inst_10:
// rs1_val == -4194305,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x400001; immval:0x13
TEST_CI_OP( c.slli, x10, 0xfff80000, -0x400001, 0x13, x1, 40, x2)
inst_11:
// rs1_val == -2097153,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x200001; immval:0x11
TEST_CI_OP( c.slli, x10, 0xfffe0000, -0x200001, 0x11, x1, 44, x2)
inst_12:
// rs1_val == -1048577,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x100001; immval:0x9
TEST_CI_OP( c.slli, x10, 0xdffffe00, -0x100001, 0x9, x1, 48, x2)
inst_13:
// rs1_val == -524289, imm_val == 21
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x80001; immval:0x15
TEST_CI_OP( c.slli, x10, 0xffe00000, -0x80001, 0x15, x1, 52, x2)
inst_14:
// rs1_val == -262145, imm_val == 27
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x40001; immval:0x1b
TEST_CI_OP( c.slli, x10, 0xf8000000, -0x40001, 0x1b, x1, 56, x2)
inst_15:
// rs1_val == -131073, imm_val == 2
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x20001; immval:0x2
TEST_CI_OP( c.slli, x10, 0xfff7fffc, -0x20001, 0x2, x1, 60, x2)
inst_16:
// rs1_val == -32769,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x8001; immval:0x1f
TEST_CI_OP( c.slli, x10, 0x80000000, -0x8001, 0x1f, x1, 64, x2)
inst_17:
// rs1_val == -16385,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x4001; immval:0xd
TEST_CI_OP( c.slli, x10, 0xf7ffe000, -0x4001, 0xd, x1, 68, x2)
inst_18:
// rs1_val == -8193,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x2001; immval:0x1d
TEST_CI_OP( c.slli, x10, 0xe0000000, -0x2001, 0x1d, x1, 72, x2)
inst_19:
// rs1_val == -4097,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x1001; immval:0x1b
TEST_CI_OP( c.slli, x10, 0xf8000000, -0x1001, 0x1b, x1, 76, x2)
inst_20:
// rs1_val == -2049, imm_val == 15
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x801; immval:0xf
TEST_CI_OP( c.slli, x10, 0xfbff8000, -0x801, 0xf, x1, 80, x2)
inst_21:
// rs1_val == -1025,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x401; immval:0x1f
TEST_CI_OP( c.slli, x10, 0x80000000, -0x401, 0x1f, x1, 84, x2)
inst_22:
// rs1_val == -513,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x201; immval:0x5
TEST_CI_OP( c.slli, x10, 0xffffbfe0, -0x201, 0x5, x1, 88, x2)
inst_23:
// rs1_val == -257,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x101; immval:0x1f
TEST_CI_OP( c.slli, x10, 0x80000000, -0x101, 0x1f, x1, 92, x2)
inst_24:
// rs1_val == -129, imm_val == 30
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x81; immval:0x1e
TEST_CI_OP( c.slli, x10, 0xc0000000, -0x81, 0x1e, x1, 96, x2)
inst_25:
// rs1_val == -65,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x41; immval:0x3
TEST_CI_OP( c.slli, x10, 0xfffffdf8, -0x41, 0x3, x1, 100, x2)
inst_26:
// rs1_val == -33, imm_val == 23
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x21; immval:0x17
TEST_CI_OP( c.slli, x10, 0xef800000, -0x21, 0x17, x1, 104, x2)
inst_27:
// rs1_val == -17, imm_val == 1
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x11; immval:0x1
TEST_CI_OP( c.slli, x10, 0xffffffde, -0x11, 0x1, x1, 108, x2)
inst_28:
// rs1_val == -9,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x9; immval:0x1d
TEST_CI_OP( c.slli, x10, 0xe0000000, -0x9, 0x1d, x1, 112, x2)
inst_29:
// rs1_val == -5,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x5; immval:0x17
TEST_CI_OP( c.slli, x10, 0xfd800000, -0x5, 0x17, x1, 116, x2)
inst_30:
// rs1_val == -3,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x3; immval:0x1b
TEST_CI_OP( c.slli, x10, 0xe8000000, -0x3, 0x1b, x1, 120, x2)
inst_31:
// rs1_val == -2,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x2; immval:0x1e
TEST_CI_OP( c.slli, x10, 0x80000000, -0x2, 0x1e, x1, 124, x2)
inst_32:
// rs1_val == -2147483648, rs1_val == (-2**(xlen-1)) and imm_val != 0 and imm_val < xlen
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x80000000; immval:0x1d
TEST_CI_OP( c.slli, x10, 0x0, -0x80000000, 0x1d, x1, 128, x2)
inst_33:
// rs1_val == 1073741824,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x40000000; immval:0x1b
TEST_CI_OP( c.slli, x10, 0x0, 0x40000000, 0x1b, x1, 132, x2)
inst_34:
// rs1_val == 536870912,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x20000000; immval:0x13
TEST_CI_OP( c.slli, x10, 0x0, 0x20000000, 0x13, x1, 136, x2)
inst_35:
// rs1_val == 268435456,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x10000000; immval:0x1e
TEST_CI_OP( c.slli, x10, 0x0, 0x10000000, 0x1e, x1, 140, x2)
inst_36:
// rs1_val == 134217728,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x8000000; immval:0x9
TEST_CI_OP( c.slli, x10, 0x0, 0x8000000, 0x9, x1, 144, x2)
inst_37:
// rs1_val == 67108864,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x4000000; immval:0x2
TEST_CI_OP( c.slli, x10, 0x10000000, 0x4000000, 0x2, x1, 148, x2)
inst_38:
// rs1_val == 33554432,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x2000000; immval:0x5
TEST_CI_OP( c.slli, x10, 0x40000000, 0x2000000, 0x5, x1, 152, x2)
inst_39:
// rs1_val == 16777216,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x1000000; immval:0x5
TEST_CI_OP( c.slli, x10, 0x20000000, 0x1000000, 0x5, x1, 156, x2)
inst_40:
// rs1_val == 8388608,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x800000; immval:0x6
TEST_CI_OP( c.slli, x10, 0x20000000, 0x800000, 0x6, x1, 160, x2)
inst_41:
// rs1_val == 4194304,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x400000; immval:0xe
TEST_CI_OP( c.slli, x10, 0x0, 0x400000, 0xe, x1, 164, x2)
inst_42:
// rs1_val == 2097152,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x200000; immval:0x7
TEST_CI_OP( c.slli, x10, 0x10000000, 0x200000, 0x7, x1, 168, x2)
inst_43:
// rs1_val == 1048576,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x100000; immval:0x1b
TEST_CI_OP( c.slli, x10, 0x0, 0x100000, 0x1b, x1, 172, x2)
inst_44:
// rs1_val == 524288,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x80000; immval:0x13
TEST_CI_OP( c.slli, x10, 0x0, 0x80000, 0x13, x1, 176, x2)
inst_45:
// rs1_val == 262144,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x40000; immval:0x9
TEST_CI_OP( c.slli, x10, 0x8000000, 0x40000, 0x9, x1, 180, x2)
inst_46:
// rs1_val == 131072,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x20000; immval:0x12
TEST_CI_OP( c.slli, x10, 0x0, 0x20000, 0x12, x1, 184, x2)
inst_47:
// rs1_val == 65536,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x10000; immval:0xb
TEST_CI_OP( c.slli, x10, 0x8000000, 0x10000, 0xb, x1, 188, x2)
inst_48:
// rs1_val == 32768,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x8000; immval:0x1
TEST_CI_OP( c.slli, x10, 0x10000, 0x8000, 0x1, x1, 192, x2)
inst_49:
// rs1_val == 16384,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x4000; immval:0x1e
TEST_CI_OP( c.slli, x10, 0x0, 0x4000, 0x1e, x1, 196, x2)
inst_50:
// rs1_val == 8192,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x2000; immval:0x1
TEST_CI_OP( c.slli, x10, 0x4000, 0x2000, 0x1, x1, 200, x2)
inst_51:
// rs1_val == 4096,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x1000; immval:0x9
TEST_CI_OP( c.slli, x10, 0x200000, 0x1000, 0x9, x1, 204, x2)
inst_52:
// rs1_val == 2048,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x800; immval:0x11
TEST_CI_OP( c.slli, x10, 0x10000000, 0x800, 0x11, x1, 208, x2)
inst_53:
// rs1_val == 1024,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x400; immval:0x1d
TEST_CI_OP( c.slli, x10, 0x0, 0x400, 0x1d, x1, 212, x2)
inst_54:
// rs1_val == 512,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x200; immval:0xd
TEST_CI_OP( c.slli, x10, 0x400000, 0x200, 0xd, x1, 216, x2)
inst_55:
// rs1_val == 256,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x100; immval:0x12
TEST_CI_OP( c.slli, x10, 0x4000000, 0x100, 0x12, x1, 220, x2)
inst_56:
// rs1_val == 128,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x80; immval:0x6
TEST_CI_OP( c.slli, x10, 0x2000, 0x80, 0x6, x1, 224, x2)
inst_57:
// rs1_val == 64,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x40; immval:0x9
TEST_CI_OP( c.slli, x10, 0x8000, 0x40, 0x9, x1, 228, x2)
inst_58:
// rs1_val == 32,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x20; immval:0x1b
TEST_CI_OP( c.slli, x10, 0x0, 0x20, 0x1b, x1, 232, x2)
inst_59:
// rs1_val == 16, rs1_val == imm_val and imm_val != 0 and imm_val < xlen, imm_val == 16
// opcode:c.slli; op1:x10; dest:x10 op1val:0x10; immval:0x10
TEST_CI_OP( c.slli, x10, 0x100000, 0x10, 0x10, x1, 236, x2)
inst_60:
// rs1_val == 8,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x8; immval:0x13
TEST_CI_OP( c.slli, x10, 0x400000, 0x8, 0x13, x1, 240, x2)
inst_61:
// rs1_val == 4, rs1_val==4
// opcode:c.slli; op1:x10; dest:x10 op1val:0x4; immval:0x15
TEST_CI_OP( c.slli, x10, 0x800000, 0x4, 0x15, x1, 244, x2)
inst_62:
// rs1_val == 2, rs1_val==2
// opcode:c.slli; op1:x10; dest:x10 op1val:0x2; immval:0x1b
TEST_CI_OP( c.slli, x10, 0x10000000, 0x2, 0x1b, x1, 248, x2)
inst_63:
// rs1_val == 1, rs1_val == 1 and imm_val != 0 and imm_val < xlen
// opcode:c.slli; op1:x10; dest:x10 op1val:0x1; immval:0x13
TEST_CI_OP( c.slli, x10, 0x80000, 0x1, 0x13, x1, 252, x2)
inst_64:
// imm_val == 8,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x400000; immval:0x8
TEST_CI_OP( c.slli, x10, 0x40000000, 0x400000, 0x8, x1, 256, x2)
inst_65:
// imm_val == 4,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x8001; immval:0x4
TEST_CI_OP( c.slli, x10, 0xfff7fff0, -0x8001, 0x4, x1, 260, x2)
inst_66:
// rs1_val==46341,
// opcode:c.slli; op1:x10; dest:x10 op1val:0xb505; immval:0xf
TEST_CI_OP( c.slli, x10, 0x5a828000, 0xb505, 0xf, x1, 264, x2)
inst_67:
// rs1_val==-46339,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0xb503; immval:0xa
TEST_CI_OP( c.slli, x10, 0xfd2bf400, -0xb503, 0xa, x1, 268, x2)
inst_68:
// rs1_val==1717986919,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x66666667; immval:0x1e
TEST_CI_OP( c.slli, x10, 0xc0000000, 0x66666667, 0x1e, x1, 272, x2)
inst_69:
// rs1_val==858993460,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x33333334; immval:0x4
TEST_CI_OP( c.slli, x10, 0x33333340, 0x33333334, 0x4, x1, 276, x2)
inst_70:
// rs1_val==6,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x6; immval:0x3
TEST_CI_OP( c.slli, x10, 0x30, 0x6, 0x3, x1, 280, x2)
inst_71:
// rs1_val==-1431655765,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x55555555; immval:0x17
TEST_CI_OP( c.slli, x10, 0x55800000, -0x55555555, 0x17, x1, 284, x2)
inst_72:
// rs1_val==1431655766,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x55555556; immval:0x8
TEST_CI_OP( c.slli, x10, 0x55555600, 0x55555556, 0x8, x1, 288, x2)
inst_73:
// rs1_val==46339,
// opcode:c.slli; op1:x10; dest:x10 op1val:0xb503; immval:0x1b
TEST_CI_OP( c.slli, x10, 0x18000000, 0xb503, 0x1b, x1, 292, x2)
inst_74:
// rs1_val==3,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x3; immval:0x1b
TEST_CI_OP( c.slli, x10, 0x18000000, 0x3, 0x1b, x1, 296, x2)
inst_75:
// rs1_val == -1431655766, rs1_val==-1431655766
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x55555556; immval:0x3
TEST_CI_OP( c.slli, x10, 0x55555550, -0x55555556, 0x3, x1, 300, x2)
inst_76:
// rs1_val == 1431655765, rs1_val==1431655765
// opcode:c.slli; op1:x10; dest:x10 op1val:0x55555555; immval:0x4
TEST_CI_OP( c.slli, x10, 0x55555550, 0x55555555, 0x4, x1, 304, x2)
inst_77:
// rs1_val == 0 and imm_val != 0 and imm_val < xlen, rs1_val==0
// opcode:c.slli; op1:x10; dest:x10 op1val:0x0; immval:0x15
TEST_CI_OP( c.slli, x10, 0x0, 0x0, 0x15, x1, 308, x2)
inst_78:
// rs1_val==1717986917,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x66666665; immval:0x5
TEST_CI_OP( c.slli, x10, 0xcccccca0, 0x66666665, 0x5, x1, 312, x2)
inst_79:
// rs1_val==858993458,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x33333332; immval:0x10
TEST_CI_OP( c.slli, x10, 0x33320000, 0x33333332, 0x10, x1, 316, x2)
inst_80:
// rs1_val==1431655764,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x55555554; immval:0x17
TEST_CI_OP( c.slli, x10, 0xaa000000, 0x55555554, 0x17, x1, 320, x2)
inst_81:
// rs1_val==46340,
// opcode:c.slli; op1:x10; dest:x10 op1val:0xb504; immval:0x6
TEST_CI_OP( c.slli, x10, 0x2d4100, 0xb504, 0x6, x1, 324, x2)
inst_82:
// rs1_val==-46340,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0xb504; immval:0xa
TEST_CI_OP( c.slli, x10, 0xfd2bf000, -0xb504, 0xa, x1, 328, x2)
inst_83:
// rs1_val==1717986918,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x66666666; immval:0x12
TEST_CI_OP( c.slli, x10, 0x99980000, 0x66666666, 0x12, x1, 332, x2)
inst_84:
// rs1_val==858993459,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x33333333; immval:0x1
TEST_CI_OP( c.slli, x10, 0x66666666, 0x33333333, 0x1, x1, 336, x2)
inst_85:
// rs1_val==5,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x5; immval:0x4
TEST_CI_OP( c.slli, x10, 0x50, 0x5, 0x4, x1, 340, x2)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x1_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x1_1:
.fill 86*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
RVMODEL_DATA_END

495
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/csrai-01.S
View File

@ -1,495 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Wed Aug 4 06:39:00 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.srai instruction of the RISC-V C extension for the csrai covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32EC")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",csrai)
RVTEST_SIGBASE( x1,signature_x1_1)
inst_0:
// rs1==x10, rs1_val < 0 and imm_val < xlen, rs1_val == -1431655766, rs1_val==-1431655766
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x55555556; immval:0xe
TEST_CI_OP( c.srai, x10, 0xfffeaaaa, -0x55555556, 0xe, x1, 0, x2)
inst_1:
// rs1==x9, rs1_val == 2147483647, rs1_val > 0 and imm_val < xlen, rs1_val == (2**(xlen-1)-1) and imm_val != 0 and imm_val < xlen
// opcode:c.srai; op1:x9; dest:x9 op1val:0x7fffffff; immval:0x9
TEST_CI_OP( c.srai, x9, 0x3fffff, 0x7fffffff, 0x9, x1, 4, x2)
inst_2:
// rs1==x11, rs1_val == -1073741825,
// opcode:c.srai; op1:x11; dest:x11 op1val:-0x40000001; immval:0x5
TEST_CI_OP( c.srai, x11, 0xfdffffff, -0x40000001, 0x5, x1, 8, x2)
inst_3:
// rs1==x12, rs1_val == -536870913, imm_val == 4
// opcode:c.srai; op1:x12; dest:x12 op1val:-0x20000001; immval:0x4
TEST_CI_OP( c.srai, x12, 0xfdffffff, -0x20000001, 0x4, x1, 12, x2)
inst_4:
// rs1==x14, rs1_val == -268435457, imm_val == 21
// opcode:c.srai; op1:x14; dest:x14 op1val:-0x10000001; immval:0x15
TEST_CI_OP( c.srai, x14, 0xffffff7f, -0x10000001, 0x15, x1, 16, x2)
inst_5:
// rs1==x8, rs1_val == -134217729,
// opcode:c.srai; op1:x8; dest:x8 op1val:-0x8000001; immval:0x13
TEST_CI_OP( c.srai, x8, 0xfffffeff, -0x8000001, 0x13, x1, 20, x2)
inst_6:
// rs1==x13, rs1_val == -67108865,
// opcode:c.srai; op1:x13; dest:x13 op1val:-0x4000001; immval:0xc
TEST_CI_OP( c.srai, x13, 0xffffbfff, -0x4000001, 0xc, x1, 24, x2)
inst_7:
// rs1==x15, rs1_val == -33554433, imm_val == 29
// opcode:c.srai; op1:x15; dest:x15 op1val:-0x2000001; immval:0x1d
TEST_CI_OP( c.srai, x15, 0xffffffff, -0x2000001, 0x1d, x1, 28, x2)
inst_8:
// rs1_val == -16777217,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x1000001; immval:0xd
TEST_CI_OP( c.srai, x10, 0xfffff7ff, -0x1000001, 0xd, x1, 32, x2)
inst_9:
// rs1_val == -8388609,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x800001; immval:0x3
TEST_CI_OP( c.srai, x10, 0xffefffff, -0x800001, 0x3, x1, 36, x2)
inst_10:
// rs1_val == -4194305, imm_val == 10
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x400001; immval:0xa
TEST_CI_OP( c.srai, x10, 0xffffefff, -0x400001, 0xa, x1, 40, x2)
inst_11:
// rs1_val == -2097153,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x200001; immval:0xd
TEST_CI_OP( c.srai, x10, 0xfffffeff, -0x200001, 0xd, x1, 44, x2)
inst_12:
// rs1_val == -1048577,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x100001; immval:0xd
TEST_CI_OP( c.srai, x10, 0xffffff7f, -0x100001, 0xd, x1, 48, x2)
inst_13:
// rs1_val == -524289,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x80001; immval:0x5
TEST_CI_OP( c.srai, x10, 0xffffbfff, -0x80001, 0x5, x1, 52, x2)
inst_14:
// rs1_val == -262145,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x40001; immval:0x4
TEST_CI_OP( c.srai, x10, 0xffffbfff, -0x40001, 0x4, x1, 56, x2)
inst_15:
// rs1_val == -131073,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x20001; immval:0x1d
TEST_CI_OP( c.srai, x10, 0xffffffff, -0x20001, 0x1d, x1, 60, x2)
inst_16:
// rs1_val == -65537,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x10001; immval:0x15
TEST_CI_OP( c.srai, x10, 0xffffffff, -0x10001, 0x15, x1, 64, x2)
inst_17:
// rs1_val == -32769, imm_val == 2
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x8001; immval:0x2
TEST_CI_OP( c.srai, x10, 0xffffdfff, -0x8001, 0x2, x1, 68, x2)
inst_18:
// rs1_val == -16385,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x4001; immval:0x7
TEST_CI_OP( c.srai, x10, 0xffffff7f, -0x4001, 0x7, x1, 72, x2)
inst_19:
// rs1_val == -8193,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x2001; immval:0x12
TEST_CI_OP( c.srai, x10, 0xffffffff, -0x2001, 0x12, x1, 76, x2)
inst_20:
// rs1_val == -4097,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x1001; immval:0x6
TEST_CI_OP( c.srai, x10, 0xffffffbf, -0x1001, 0x6, x1, 80, x2)
inst_21:
// rs1_val == -2049,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x801; immval:0x13
TEST_CI_OP( c.srai, x10, 0xffffffff, -0x801, 0x13, x1, 84, x2)
inst_22:
// rs1_val == -1025,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x401; immval:0x3
TEST_CI_OP( c.srai, x10, 0xffffff7f, -0x401, 0x3, x1, 88, x2)
inst_23:
// rs1_val == -513, imm_val == 15
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x201; immval:0xf
TEST_CI_OP( c.srai, x10, 0xffffffff, -0x201, 0xf, x1, 92, x2)
inst_24:
// rs1_val == -257,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x101; immval:0x7
TEST_CI_OP( c.srai, x10, 0xfffffffd, -0x101, 0x7, x1, 96, x2)
inst_25:
// rs1_val == -129,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x81; immval:0xa
TEST_CI_OP( c.srai, x10, 0xffffffff, -0x81, 0xa, x1, 100, x2)
inst_26:
// rs1_val == -65, imm_val == 23
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x41; immval:0x17
TEST_CI_OP( c.srai, x10, 0xffffffff, -0x41, 0x17, x1, 104, x2)
inst_27:
// rs1_val == -33, imm_val == 30
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x21; immval:0x1e
TEST_CI_OP( c.srai, x10, 0xffffffff, -0x21, 0x1e, x1, 108, x2)
inst_28:
// rs1_val == -17,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x11; immval:0x1e
TEST_CI_OP( c.srai, x10, 0xffffffff, -0x11, 0x1e, x1, 112, x2)
inst_29:
// rs1_val == -9,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x9; immval:0x7
TEST_CI_OP( c.srai, x10, 0xffffffff, -0x9, 0x7, x1, 116, x2)
inst_30:
// rs1_val == -5,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x5; immval:0x9
TEST_CI_OP( c.srai, x10, 0xffffffff, -0x5, 0x9, x1, 120, x2)
inst_31:
// rs1_val == -3,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x3; immval:0x13
TEST_CI_OP( c.srai, x10, 0xffffffff, -0x3, 0x13, x1, 124, x2)
inst_32:
// rs1_val == -2,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x2; immval:0x17
TEST_CI_OP( c.srai, x10, 0xffffffff, -0x2, 0x17, x1, 128, x2)
inst_33:
// imm_val == 27, rs1_val == 32
// opcode:c.srai; op1:x10; dest:x10 op1val:0x20; immval:0x1b
TEST_CI_OP( c.srai, x10, 0x0, 0x20, 0x1b, x1, 132, x2)
inst_34:
// rs1_val == -2147483648, rs1_val == (-2**(xlen-1)) and imm_val != 0 and imm_val < xlen
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x80000000; immval:0x12
TEST_CI_OP( c.srai, x10, 0xffffe000, -0x80000000, 0x12, x1, 136, x2)
inst_35:
// rs1_val == 1073741824,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x40000000; immval:0x11
TEST_CI_OP( c.srai, x10, 0x2000, 0x40000000, 0x11, x1, 140, x2)
inst_36:
// rs1_val == 536870912,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x20000000; immval:0x1b
TEST_CI_OP( c.srai, x10, 0x4, 0x20000000, 0x1b, x1, 144, x2)
inst_37:
// rs1_val == 268435456,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x10000000; immval:0x15
TEST_CI_OP( c.srai, x10, 0x80, 0x10000000, 0x15, x1, 148, x2)
inst_38:
// rs1_val == 134217728,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x8000000; immval:0x12
TEST_CI_OP( c.srai, x10, 0x200, 0x8000000, 0x12, x1, 152, x2)
inst_39:
// rs1_val == 67108864,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x4000000; immval:0x15
TEST_CI_OP( c.srai, x10, 0x20, 0x4000000, 0x15, x1, 156, x2)
inst_40:
// rs1_val == 33554432,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x2000000; immval:0x4
TEST_CI_OP( c.srai, x10, 0x200000, 0x2000000, 0x4, x1, 160, x2)
inst_41:
// rs1_val == 16777216,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x1000000; immval:0x1e
TEST_CI_OP( c.srai, x10, 0x0, 0x1000000, 0x1e, x1, 164, x2)
inst_42:
// rs1_val == 8388608,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x800000; immval:0x1e
TEST_CI_OP( c.srai, x10, 0x0, 0x800000, 0x1e, x1, 168, x2)
inst_43:
// rs1_val == 4194304,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x400000; immval:0xd
TEST_CI_OP( c.srai, x10, 0x200, 0x400000, 0xd, x1, 172, x2)
inst_44:
// rs1_val == 2097152,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x200000; immval:0xd
TEST_CI_OP( c.srai, x10, 0x100, 0x200000, 0xd, x1, 176, x2)
inst_45:
// rs1_val == 1048576,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x100000; immval:0x13
TEST_CI_OP( c.srai, x10, 0x2, 0x100000, 0x13, x1, 180, x2)
inst_46:
// rs1_val == 524288,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x80000; immval:0x9
TEST_CI_OP( c.srai, x10, 0x400, 0x80000, 0x9, x1, 184, x2)
inst_47:
// rs1_val == 262144,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x40000; immval:0x13
TEST_CI_OP( c.srai, x10, 0x0, 0x40000, 0x13, x1, 188, x2)
inst_48:
// rs1_val == 131072,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x20000; immval:0x4
TEST_CI_OP( c.srai, x10, 0x2000, 0x20000, 0x4, x1, 192, x2)
inst_49:
// rs1_val == 65536, imm_val == 8
// opcode:c.srai; op1:x10; dest:x10 op1val:0x10000; immval:0x8
TEST_CI_OP( c.srai, x10, 0x100, 0x10000, 0x8, x1, 196, x2)
inst_50:
// rs1_val == 32768,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x8000; immval:0x5
TEST_CI_OP( c.srai, x10, 0x400, 0x8000, 0x5, x1, 200, x2)
inst_51:
// rs1_val == 16384,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x4000; immval:0x17
TEST_CI_OP( c.srai, x10, 0x0, 0x4000, 0x17, x1, 204, x2)
inst_52:
// rs1_val == 8192,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x2000; immval:0x5
TEST_CI_OP( c.srai, x10, 0x100, 0x2000, 0x5, x1, 208, x2)
inst_53:
// rs1_val == 4096,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x1000; immval:0x17
TEST_CI_OP( c.srai, x10, 0x0, 0x1000, 0x17, x1, 212, x2)
inst_54:
// rs1_val == 2048,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x800; immval:0xa
TEST_CI_OP( c.srai, x10, 0x2, 0x800, 0xa, x1, 216, x2)
inst_55:
// rs1_val == 1024,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x400; immval:0x1e
TEST_CI_OP( c.srai, x10, 0x0, 0x400, 0x1e, x1, 220, x2)
inst_56:
// rs1_val == 512,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x200; immval:0xb
TEST_CI_OP( c.srai, x10, 0x0, 0x200, 0xb, x1, 224, x2)
inst_57:
// rs1_val == 256,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x100; immval:0x1f
TEST_CI_OP( c.srai, x10, 0x0, 0x100, 0x1f, x1, 228, x2)
inst_58:
// rs1_val == 128,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x80; immval:0x3
TEST_CI_OP( c.srai, x10, 0x10, 0x80, 0x3, x1, 232, x2)
inst_59:
// rs1_val == 64,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x40; immval:0x1b
TEST_CI_OP( c.srai, x10, 0x0, 0x40, 0x1b, x1, 236, x2)
inst_60:
// rs1_val == 16,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x10; immval:0x6
TEST_CI_OP( c.srai, x10, 0x0, 0x10, 0x6, x1, 240, x2)
inst_61:
// rs1_val == 8,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x8; immval:0x11
TEST_CI_OP( c.srai, x10, 0x0, 0x8, 0x11, x1, 244, x2)
inst_62:
// rs1_val == 4, rs1_val==4
// opcode:c.srai; op1:x10; dest:x10 op1val:0x4; immval:0x13
TEST_CI_OP( c.srai, x10, 0x0, 0x4, 0x13, x1, 248, x2)
inst_63:
// rs1_val == 2, rs1_val==2
// opcode:c.srai; op1:x10; dest:x10 op1val:0x2; immval:0x4
TEST_CI_OP( c.srai, x10, 0x0, 0x2, 0x4, x1, 252, x2)
inst_64:
// rs1_val == 1, rs1_val == 1 and imm_val != 0 and imm_val < xlen
// opcode:c.srai; op1:x10; dest:x10 op1val:0x1; immval:0x1f
TEST_CI_OP( c.srai, x10, 0x0, 0x1, 0x1f, x1, 256, x2)
inst_65:
// imm_val == 16,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x801; immval:0x10
TEST_CI_OP( c.srai, x10, 0xffffffff, -0x801, 0x10, x1, 260, x2)
inst_66:
// imm_val == 1, rs1_val == 1431655765, rs1_val==1431655765
// opcode:c.srai; op1:x10; dest:x10 op1val:0x55555555; immval:0x1
TEST_CI_OP( c.srai, x10, 0x2aaaaaaa, 0x55555555, 0x1, x1, 264, x2)
inst_67:
// rs1_val==46341,
// opcode:c.srai; op1:x10; dest:x10 op1val:0xb505; immval:0xd
TEST_CI_OP( c.srai, x10, 0x5, 0xb505, 0xd, x1, 268, x2)
inst_68:
// rs1_val==-46339,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0xb503; immval:0x5
TEST_CI_OP( c.srai, x10, 0xfffffa57, -0xb503, 0x5, x1, 272, x2)
inst_69:
// rs1_val==1717986919,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x66666667; immval:0x15
TEST_CI_OP( c.srai, x10, 0x333, 0x66666667, 0x15, x1, 276, x2)
inst_70:
// rs1_val==858993460,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x33333334; immval:0x17
TEST_CI_OP( c.srai, x10, 0x66, 0x33333334, 0x17, x1, 280, x2)
inst_71:
// rs1_val==6,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x6; immval:0x3
TEST_CI_OP( c.srai, x10, 0x0, 0x6, 0x3, x1, 284, x2)
inst_72:
// rs1_val==3, rs1_val == imm_val and imm_val != 0 and imm_val < xlen
// opcode:c.srai; op1:x10; dest:x10 op1val:0x3; immval:0x3
TEST_CI_OP( c.srai, x10, 0x0, 0x3, 0x3, x1, 288, x2)
inst_73:
// rs1_val == 0 and imm_val != 0 and imm_val < xlen, rs1_val==0
// opcode:c.srai; op1:x10; dest:x10 op1val:0x0; immval:0x12
TEST_CI_OP( c.srai, x10, 0x0, 0x0, 0x12, x1, 292, x2)
inst_74:
// rs1_val==-1431655765,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x55555555; immval:0x6
TEST_CI_OP( c.srai, x10, 0xfeaaaaaa, -0x55555555, 0x6, x1, 296, x2)
inst_75:
// rs1_val==1431655766,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x55555556; immval:0x11
TEST_CI_OP( c.srai, x10, 0x2aaa, 0x55555556, 0x11, x1, 300, x2)
inst_76:
// rs1_val==46339,
// opcode:c.srai; op1:x10; dest:x10 op1val:0xb503; immval:0xe
TEST_CI_OP( c.srai, x10, 0x2, 0xb503, 0xe, x1, 304, x2)
inst_77:
// rs1_val==1717986917,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x66666665; immval:0x5
TEST_CI_OP( c.srai, x10, 0x3333333, 0x66666665, 0x5, x1, 308, x2)
inst_78:
// rs1_val==858993458,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x33333332; immval:0x8
TEST_CI_OP( c.srai, x10, 0x333333, 0x33333332, 0x8, x1, 312, x2)
inst_79:
// rs1_val==1431655764,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x55555554; immval:0x8
TEST_CI_OP( c.srai, x10, 0x555555, 0x55555554, 0x8, x1, 316, x2)
inst_80:
// rs1_val==46340,
// opcode:c.srai; op1:x10; dest:x10 op1val:0xb504; immval:0x1f
TEST_CI_OP( c.srai, x10, 0x0, 0xb504, 0x1f, x1, 320, x2)
inst_81:
// rs1_val==-46340,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0xb504; immval:0x8
TEST_CI_OP( c.srai, x10, 0xffffff4a, -0xb504, 0x8, x1, 324, x2)
inst_82:
// rs1_val==1717986918,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x66666666; immval:0xd
TEST_CI_OP( c.srai, x10, 0x33333, 0x66666666, 0xd, x1, 328, x2)
inst_83:
// rs1_val==858993459,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x33333333; immval:0x17
TEST_CI_OP( c.srai, x10, 0x66, 0x33333333, 0x17, x1, 332, x2)
inst_84:
// rs1_val==5,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x5; immval:0x1
TEST_CI_OP( c.srai, x10, 0x2, 0x5, 0x1, x1, 336, x2)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x1_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x1_1:
.fill 85*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
RVMODEL_DATA_END

505
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/csrli-01.S
View File

@ -1,505 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Wed Aug 4 06:39:00 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.srli instruction of the RISC-V C extension for the csrli covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32EC")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",csrli)
RVTEST_SIGBASE( x1,signature_x1_1)
inst_0:
// rs1==x15, rs1_val < 0 and imm_val < xlen, rs1_val == -2
// opcode:c.srli; op1:x15; dest:x15 op1val:-0x2; immval:0xe
TEST_CI_OP( c.srli, x15, 0x3ffff, -0x2, 0xe, x1, 0, x2)
inst_1:
// rs1==x8, rs1_val == 2147483647, rs1_val > 0 and imm_val < xlen, rs1_val == (2**(xlen-1)-1) and imm_val != 0 and imm_val < xlen
// opcode:c.srli; op1:x8; dest:x8 op1val:0x7fffffff; immval:0x7
TEST_CI_OP( c.srli, x8, 0xffffff, 0x7fffffff, 0x7, x1, 4, x2)
inst_2:
// rs1==x11, rs1_val == -1073741825, imm_val == 15
// opcode:c.srli; op1:x11; dest:x11 op1val:-0x40000001; immval:0xf
TEST_CI_OP( c.srli, x11, 0x17fff, -0x40000001, 0xf, x1, 8, x2)
inst_3:
// rs1==x10, rs1_val == -536870913,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x20000001; immval:0xb
TEST_CI_OP( c.srli, x10, 0x1bffff, -0x20000001, 0xb, x1, 12, x2)
inst_4:
// rs1==x9, rs1_val == -268435457,
// opcode:c.srli; op1:x9; dest:x9 op1val:-0x10000001; immval:0xc
TEST_CI_OP( c.srli, x9, 0xeffff, -0x10000001, 0xc, x1, 16, x2)
inst_5:
// rs1==x13, rs1_val == -134217729, imm_val == 4
// opcode:c.srli; op1:x13; dest:x13 op1val:-0x8000001; immval:0x4
TEST_CI_OP( c.srli, x13, 0xf7fffff, -0x8000001, 0x4, x1, 20, x2)
inst_6:
// rs1==x12, rs1_val == -67108865,
// opcode:c.srli; op1:x12; dest:x12 op1val:-0x4000001; immval:0x3
TEST_CI_OP( c.srli, x12, 0x1f7fffff, -0x4000001, 0x3, x1, 24, x2)
inst_7:
// rs1==x14, rs1_val == -33554433,
// opcode:c.srli; op1:x14; dest:x14 op1val:-0x2000001; immval:0x11
TEST_CI_OP( c.srli, x14, 0x7eff, -0x2000001, 0x11, x1, 28, x2)
inst_8:
// rs1_val == -16777217,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x1000001; immval:0x6
TEST_CI_OP( c.srli, x10, 0x3fbffff, -0x1000001, 0x6, x1, 32, x2)
inst_9:
// rs1_val == -8388609,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x800001; immval:0xf
TEST_CI_OP( c.srli, x10, 0x1feff, -0x800001, 0xf, x1, 36, x2)
inst_10:
// rs1_val == -4194305, imm_val == 21
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x400001; immval:0x15
TEST_CI_OP( c.srli, x10, 0x7fd, -0x400001, 0x15, x1, 40, x2)
inst_11:
// rs1_val == -2097153,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x200001; immval:0x3
TEST_CI_OP( c.srli, x10, 0x1ffbffff, -0x200001, 0x3, x1, 44, x2)
inst_12:
// rs1_val == -1048577, imm_val == 2
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x100001; immval:0x2
TEST_CI_OP( c.srli, x10, 0x3ffbffff, -0x100001, 0x2, x1, 48, x2)
inst_13:
// rs1_val == -524289, imm_val == 16
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x80001; immval:0x10
TEST_CI_OP( c.srli, x10, 0xfff7, -0x80001, 0x10, x1, 52, x2)
inst_14:
// rs1_val == -262145,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x40001; immval:0x6
TEST_CI_OP( c.srli, x10, 0x3ffefff, -0x40001, 0x6, x1, 56, x2)
inst_15:
// rs1_val == -131073,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x20001; immval:0x10
TEST_CI_OP( c.srli, x10, 0xfffd, -0x20001, 0x10, x1, 60, x2)
inst_16:
// rs1_val == -65537,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x10001; immval:0x9
TEST_CI_OP( c.srli, x10, 0x7fff7f, -0x10001, 0x9, x1, 64, x2)
inst_17:
// rs1_val == -32769,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x8001; immval:0x9
TEST_CI_OP( c.srli, x10, 0x7fffbf, -0x8001, 0x9, x1, 68, x2)
inst_18:
// rs1_val == -16385,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x4001; immval:0xc
TEST_CI_OP( c.srli, x10, 0xffffb, -0x4001, 0xc, x1, 72, x2)
inst_19:
// rs1_val == -8193,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x2001; immval:0xe
TEST_CI_OP( c.srli, x10, 0x3ffff, -0x2001, 0xe, x1, 76, x2)
inst_20:
// rs1_val == -4097,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x1001; immval:0x5
TEST_CI_OP( c.srli, x10, 0x7ffff7f, -0x1001, 0x5, x1, 80, x2)
inst_21:
// rs1_val == -2049,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x801; immval:0x15
TEST_CI_OP( c.srli, x10, 0x7ff, -0x801, 0x15, x1, 84, x2)
inst_22:
// rs1_val == -1025, imm_val == 29
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x401; immval:0x1d
TEST_CI_OP( c.srli, x10, 0x7, -0x401, 0x1d, x1, 88, x2)
inst_23:
// rs1_val == -513,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x201; immval:0xc
TEST_CI_OP( c.srli, x10, 0xfffff, -0x201, 0xc, x1, 92, x2)
inst_24:
// rs1_val == -257,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x101; immval:0xc
TEST_CI_OP( c.srli, x10, 0xfffff, -0x101, 0xc, x1, 96, x2)
inst_25:
// rs1_val == -129,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x81; immval:0x7
TEST_CI_OP( c.srli, x10, 0x1fffffe, -0x81, 0x7, x1, 100, x2)
inst_26:
// rs1_val == -65,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x41; immval:0x1d
TEST_CI_OP( c.srli, x10, 0x7, -0x41, 0x1d, x1, 104, x2)
inst_27:
// rs1_val == -33,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x21; immval:0xf
TEST_CI_OP( c.srli, x10, 0x1ffff, -0x21, 0xf, x1, 108, x2)
inst_28:
// rs1_val == -17,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x11; immval:0xc
TEST_CI_OP( c.srli, x10, 0xfffff, -0x11, 0xc, x1, 112, x2)
inst_29:
// rs1_val == -9,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x9; immval:0x7
TEST_CI_OP( c.srli, x10, 0x1ffffff, -0x9, 0x7, x1, 116, x2)
inst_30:
// rs1_val == -5, imm_val == 30
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x5; immval:0x1e
TEST_CI_OP( c.srli, x10, 0x3, -0x5, 0x1e, x1, 120, x2)
inst_31:
// rs1_val == -3,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x3; immval:0xb
TEST_CI_OP( c.srli, x10, 0x1fffff, -0x3, 0xb, x1, 124, x2)
inst_32:
// imm_val == 23, rs1_val==5
// opcode:c.srli; op1:x10; dest:x10 op1val:0x5; immval:0x17
TEST_CI_OP( c.srli, x10, 0x0, 0x5, 0x17, x1, 128, x2)
inst_33:
// imm_val == 27,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x81; immval:0x1b
TEST_CI_OP( c.srli, x10, 0x1f, -0x81, 0x1b, x1, 132, x2)
inst_34:
// rs1_val == -2147483648, rs1_val == (-2**(xlen-1)) and imm_val != 0 and imm_val < xlen
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x80000000; immval:0x9
TEST_CI_OP( c.srli, x10, 0x400000, -0x80000000, 0x9, x1, 136, x2)
inst_35:
// rs1_val == 1073741824,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x40000000; immval:0x7
TEST_CI_OP( c.srli, x10, 0x800000, 0x40000000, 0x7, x1, 140, x2)
inst_36:
// rs1_val == 536870912,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x20000000; immval:0x6
TEST_CI_OP( c.srli, x10, 0x800000, 0x20000000, 0x6, x1, 144, x2)
inst_37:
// rs1_val == 268435456,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x10000000; immval:0x9
TEST_CI_OP( c.srli, x10, 0x80000, 0x10000000, 0x9, x1, 148, x2)
inst_38:
// rs1_val == 134217728,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x8000000; immval:0x1e
TEST_CI_OP( c.srli, x10, 0x0, 0x8000000, 0x1e, x1, 152, x2)
inst_39:
// rs1_val == 67108864,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x4000000; immval:0x11
TEST_CI_OP( c.srli, x10, 0x200, 0x4000000, 0x11, x1, 156, x2)
inst_40:
// rs1_val == 33554432,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x2000000; immval:0x15
TEST_CI_OP( c.srli, x10, 0x10, 0x2000000, 0x15, x1, 160, x2)
inst_41:
// rs1_val == 16777216,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x1000000; immval:0x10
TEST_CI_OP( c.srli, x10, 0x100, 0x1000000, 0x10, x1, 164, x2)
inst_42:
// rs1_val == 8388608,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x800000; immval:0x1d
TEST_CI_OP( c.srli, x10, 0x0, 0x800000, 0x1d, x1, 168, x2)
inst_43:
// rs1_val == 4194304,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x400000; immval:0xc
TEST_CI_OP( c.srli, x10, 0x400, 0x400000, 0xc, x1, 172, x2)
inst_44:
// rs1_val == 2097152,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x200000; immval:0xc
TEST_CI_OP( c.srli, x10, 0x200, 0x200000, 0xc, x1, 176, x2)
inst_45:
// rs1_val == 1048576,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x100000; immval:0x17
TEST_CI_OP( c.srli, x10, 0x0, 0x100000, 0x17, x1, 180, x2)
inst_46:
// rs1_val == 524288,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x80000; immval:0x1f
TEST_CI_OP( c.srli, x10, 0x0, 0x80000, 0x1f, x1, 184, x2)
inst_47:
// rs1_val == 262144,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x40000; immval:0x13
TEST_CI_OP( c.srli, x10, 0x0, 0x40000, 0x13, x1, 188, x2)
inst_48:
// rs1_val == 131072,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x20000; immval:0x1f
TEST_CI_OP( c.srli, x10, 0x0, 0x20000, 0x1f, x1, 192, x2)
inst_49:
// rs1_val == 65536, imm_val == 8
// opcode:c.srli; op1:x10; dest:x10 op1val:0x10000; immval:0x8
TEST_CI_OP( c.srli, x10, 0x100, 0x10000, 0x8, x1, 196, x2)
inst_50:
// rs1_val == 32768,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x8000; immval:0x1d
TEST_CI_OP( c.srli, x10, 0x0, 0x8000, 0x1d, x1, 200, x2)
inst_51:
// rs1_val == 16384,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x4000; immval:0x3
TEST_CI_OP( c.srli, x10, 0x800, 0x4000, 0x3, x1, 204, x2)
inst_52:
// rs1_val == 8192,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x2000; immval:0x1d
TEST_CI_OP( c.srli, x10, 0x0, 0x2000, 0x1d, x1, 208, x2)
inst_53:
// rs1_val == 4096,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x1000; immval:0x17
TEST_CI_OP( c.srli, x10, 0x0, 0x1000, 0x17, x1, 212, x2)
inst_54:
// rs1_val == 2048,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x800; immval:0x7
TEST_CI_OP( c.srli, x10, 0x10, 0x800, 0x7, x1, 216, x2)
inst_55:
// rs1_val == 1024,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x400; immval:0x10
TEST_CI_OP( c.srli, x10, 0x0, 0x400, 0x10, x1, 220, x2)
inst_56:
// rs1_val == 512,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x200; immval:0x1d
TEST_CI_OP( c.srli, x10, 0x0, 0x200, 0x1d, x1, 224, x2)
inst_57:
// rs1_val == 256, imm_val == 1
// opcode:c.srli; op1:x10; dest:x10 op1val:0x100; immval:0x1
TEST_CI_OP( c.srli, x10, 0x80, 0x100, 0x1, x1, 228, x2)
inst_58:
// rs1_val == 128,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x80; immval:0x7
TEST_CI_OP( c.srli, x10, 0x1, 0x80, 0x7, x1, 232, x2)
inst_59:
// rs1_val == 64,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x40; immval:0xd
TEST_CI_OP( c.srli, x10, 0x0, 0x40, 0xd, x1, 236, x2)
inst_60:
// rs1_val == 32,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x20; immval:0x1e
TEST_CI_OP( c.srli, x10, 0x0, 0x20, 0x1e, x1, 240, x2)
inst_61:
// rs1_val == 16,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x10; immval:0x11
TEST_CI_OP( c.srli, x10, 0x0, 0x10, 0x11, x1, 244, x2)
inst_62:
// rs1_val == 8,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x8; immval:0x1b
TEST_CI_OP( c.srli, x10, 0x0, 0x8, 0x1b, x1, 248, x2)
inst_63:
// rs1_val == 4, rs1_val==4
// opcode:c.srli; op1:x10; dest:x10 op1val:0x4; immval:0x11
TEST_CI_OP( c.srli, x10, 0x0, 0x4, 0x11, x1, 252, x2)
inst_64:
// rs1_val == 2, rs1_val==2
// opcode:c.srli; op1:x10; dest:x10 op1val:0x2; immval:0x15
TEST_CI_OP( c.srli, x10, 0x0, 0x2, 0x15, x1, 256, x2)
inst_65:
// rs1_val == 1, rs1_val == 1 and imm_val != 0 and imm_val < xlen
// opcode:c.srli; op1:x10; dest:x10 op1val:0x1; immval:0x12
TEST_CI_OP( c.srli, x10, 0x0, 0x1, 0x12, x1, 260, x2)
inst_66:
// rs1_val==46341,
// opcode:c.srli; op1:x10; dest:x10 op1val:0xb505; immval:0x10
TEST_CI_OP( c.srli, x10, 0x0, 0xb505, 0x10, x1, 264, x2)
inst_67:
// rs1_val==-46339,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0xb503; immval:0x15
TEST_CI_OP( c.srli, x10, 0x7ff, -0xb503, 0x15, x1, 268, x2)
inst_68:
// rs1_val==1717986919,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x66666667; immval:0x9
TEST_CI_OP( c.srli, x10, 0x333333, 0x66666667, 0x9, x1, 272, x2)
inst_69:
// rs1_val==858993460,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x33333334; immval:0xf
TEST_CI_OP( c.srli, x10, 0x6666, 0x33333334, 0xf, x1, 276, x2)
inst_70:
// rs1_val==6,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x6; immval:0x10
TEST_CI_OP( c.srli, x10, 0x0, 0x6, 0x10, x1, 280, x2)
inst_71:
// rs1_val==-1431655765,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x55555555; immval:0x5
TEST_CI_OP( c.srli, x10, 0x5555555, -0x55555555, 0x5, x1, 284, x2)
inst_72:
// rs1_val==1431655766,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x55555556; immval:0xf
TEST_CI_OP( c.srli, x10, 0xaaaa, 0x55555556, 0xf, x1, 288, x2)
inst_73:
// rs1_val==46339,
// opcode:c.srli; op1:x10; dest:x10 op1val:0xb503; immval:0x2
TEST_CI_OP( c.srli, x10, 0x2d40, 0xb503, 0x2, x1, 292, x2)
inst_74:
// rs1_val==0, rs1_val == 0 and imm_val != 0 and imm_val < xlen
// opcode:c.srli; op1:x10; dest:x10 op1val:0x0; immval:0xf
TEST_CI_OP( c.srli, x10, 0x0, 0x0, 0xf, x1, 296, x2)
inst_75:
// rs1_val==3,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x3; immval:0x6
TEST_CI_OP( c.srli, x10, 0x0, 0x3, 0x6, x1, 300, x2)
inst_76:
// rs1_val == -1431655766, rs1_val==-1431655766
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x55555556; immval:0x2
TEST_CI_OP( c.srli, x10, 0x2aaaaaaa, -0x55555556, 0x2, x1, 304, x2)
inst_77:
// rs1_val == 1431655765, rs1_val==1431655765
// opcode:c.srli; op1:x10; dest:x10 op1val:0x55555555; immval:0xb
TEST_CI_OP( c.srli, x10, 0xaaaaa, 0x55555555, 0xb, x1, 308, x2)
inst_78:
// imm_val == 10,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x0; immval:0xa
TEST_CI_OP( c.srli, x10, 0x0, 0x0, 0xa, x1, 312, x2)
inst_79:
// rs1_val == imm_val and imm_val != 0 and imm_val < xlen,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x4; immval:0x4
TEST_CI_OP( c.srli, x10, 0x0, 0x4, 0x4, x1, 316, x2)
inst_80:
// rs1_val==1717986917,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x66666665; immval:0xe
TEST_CI_OP( c.srli, x10, 0x19999, 0x66666665, 0xe, x1, 320, x2)
inst_81:
// rs1_val==858993458,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x33333332; immval:0x6
TEST_CI_OP( c.srli, x10, 0xcccccc, 0x33333332, 0x6, x1, 324, x2)
inst_82:
// rs1_val==1431655764,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x55555554; immval:0x3
TEST_CI_OP( c.srli, x10, 0xaaaaaaa, 0x55555554, 0x3, x1, 328, x2)
inst_83:
// rs1_val==46340,
// opcode:c.srli; op1:x10; dest:x10 op1val:0xb504; immval:0x11
TEST_CI_OP( c.srli, x10, 0x0, 0xb504, 0x11, x1, 332, x2)
inst_84:
// rs1_val==-46340,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0xb504; immval:0x5
TEST_CI_OP( c.srli, x10, 0x7fffa57, -0xb504, 0x5, x1, 336, x2)
inst_85:
// rs1_val==1717986918,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x66666666; immval:0x3
TEST_CI_OP( c.srli, x10, 0xccccccc, 0x66666666, 0x3, x1, 340, x2)
inst_86:
// rs1_val==858993459,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x33333333; immval:0x1f
TEST_CI_OP( c.srli, x10, 0x0, 0x33333333, 0x1f, x1, 344, x2)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x1_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x1_1:
.fill 87*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
RVMODEL_DATA_END

2980
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/csub-01.S
View File

File diff suppressed because it is too large Load Diff

410
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/csw-01.S
View File

@ -1,410 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Wed Aug 4 06:39:00 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.sw instruction of the RISC-V C extension for the csw covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32EC")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",csw)
RVTEST_SIGBASE( x1,signature_x1_1)
inst_0:
// rs1 != rs2, rs1==x15, rs2==x14, imm_val == 0, rs2_val == -16385
// opcode:c.sw; op1:x15; op2:x14; op2val:-0x4001; immval:0x0
TEST_STORE(x1,x2,0,x15,x14,-0x4001,0x0,0,c.sw,0)
inst_1:
// rs1==x11, rs2==x10, rs2_val == 2147483647, rs2_val == (2**(xlen-1)-1), imm_val > 0
// opcode:c.sw; op1:x11; op2:x10; op2val:0x7fffffff; immval:0x14
TEST_STORE(x1,x2,0,x11,x10,0x7fffffff,0x14,4,c.sw,0)
inst_2:
// rs1==x13, rs2==x8, rs2_val == -1073741825,
// opcode:c.sw; op1:x13; op2:x8; op2val:-0x40000001; immval:0x14
TEST_STORE(x1,x2,0,x13,x8,-0x40000001,0x14,8,c.sw,0)
inst_3:
// rs1==x9, rs2==x13, rs2_val == -536870913,
// opcode:c.sw; op1:x9; op2:x13; op2val:-0x20000001; immval:0x24
TEST_STORE(x1,x2,0,x9,x13,-0x20000001,0x24,12,c.sw,0)
inst_4:
// rs1==x10, rs2==x12, rs2_val == -268435457, imm_val == 32
// opcode:c.sw; op1:x10; op2:x12; op2val:-0x10000001; immval:0x20
TEST_STORE(x1,x2,0,x10,x12,-0x10000001,0x20,16,c.sw,0)
inst_5:
// rs1==x14, rs2==x15, rs2_val == -134217729,
// opcode:c.sw; op1:x14; op2:x15; op2val:-0x8000001; immval:0x4c
TEST_STORE(x1,x2,0,x14,x15,-0x8000001,0x4c,20,c.sw,0)
inst_6:
// rs1==x8, rs2==x9, rs2_val == -67108865,
// opcode:c.sw; op1:x8; op2:x9; op2val:-0x4000001; immval:0x48
TEST_STORE(x1,x2,0,x8,x9,-0x4000001,0x48,24,c.sw,0)
inst_7:
// rs1==x12, rs2==x11, rs2_val == -33554433, imm_val == 84
// opcode:c.sw; op1:x12; op2:x11; op2val:-0x2000001; immval:0x54
TEST_STORE(x1,x2,0,x12,x11,-0x2000001,0x54,28,c.sw,0)
inst_8:
// rs2_val == -16777217,
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x1000001; immval:0x7c
TEST_STORE(x1,x2,0,x10,x11,-0x1000001,0x7c,32,c.sw,0)
inst_9:
// rs2_val == -8388609, imm_val == 4
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x800001; immval:0x4
TEST_STORE(x1,x2,0,x10,x11,-0x800001,0x4,36,c.sw,0)
inst_10:
// rs2_val == -4194305, imm_val == 60
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x400001; immval:0x3c
TEST_STORE(x1,x2,0,x10,x11,-0x400001,0x3c,40,c.sw,0)
inst_11:
// rs2_val == -2097153,
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x200001; immval:0x30
TEST_STORE(x1,x2,0,x10,x11,-0x200001,0x30,44,c.sw,0)
inst_12:
// rs2_val == -1048577,
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x100001; immval:0x7c
TEST_STORE(x1,x2,0,x10,x11,-0x100001,0x7c,48,c.sw,0)
inst_13:
// rs2_val == -524289,
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x80001; immval:0x18
TEST_STORE(x1,x2,0,x10,x11,-0x80001,0x18,52,c.sw,0)
inst_14:
// rs2_val == -262145, imm_val == 40
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x40001; immval:0x28
TEST_STORE(x1,x2,0,x10,x11,-0x40001,0x28,56,c.sw,0)
inst_15:
// rs2_val == -131073,
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x20001; immval:0x7c
TEST_STORE(x1,x2,0,x10,x11,-0x20001,0x7c,60,c.sw,0)
inst_16:
// rs2_val == -65537,
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x10001; immval:0x14
TEST_STORE(x1,x2,0,x10,x11,-0x10001,0x14,64,c.sw,0)
inst_17:
// rs2_val == -32769, imm_val == 64
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x8001; immval:0x40
TEST_STORE(x1,x2,0,x10,x11,-0x8001,0x40,68,c.sw,0)
inst_18:
// rs2_val == -8193,
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x2001; immval:0x0
TEST_STORE(x1,x2,0,x10,x11,-0x2001,0x0,72,c.sw,0)
inst_19:
// rs2_val == -4097,
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x1001; immval:0x48
TEST_STORE(x1,x2,0,x10,x11,-0x1001,0x48,76,c.sw,0)
inst_20:
// rs2_val == -2049,
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x801; immval:0x24
TEST_STORE(x1,x2,0,x10,x11,-0x801,0x24,80,c.sw,0)
inst_21:
// rs2_val == -1025,
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x401; immval:0x28
TEST_STORE(x1,x2,0,x10,x11,-0x401,0x28,84,c.sw,0)
inst_22:
// rs2_val == -513, imm_val == 120
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x201; immval:0x78
TEST_STORE(x1,x2,0,x10,x11,-0x201,0x78,88,c.sw,0)
inst_23:
// rs2_val == -257,
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x101; immval:0x24
TEST_STORE(x1,x2,0,x10,x11,-0x101,0x24,92,c.sw,0)
inst_24:
// rs2_val == -129,
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x81; immval:0x4c
TEST_STORE(x1,x2,0,x10,x11,-0x81,0x4c,96,c.sw,0)
inst_25:
// rs2_val == -65,
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x41; immval:0x14
TEST_STORE(x1,x2,0,x10,x11,-0x41,0x14,100,c.sw,0)
inst_26:
// rs2_val == -33,
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x21; immval:0x28
TEST_STORE(x1,x2,0,x10,x11,-0x21,0x28,104,c.sw,0)
inst_27:
// rs2_val == -17,
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x11; immval:0x34
TEST_STORE(x1,x2,0,x10,x11,-0x11,0x34,108,c.sw,0)
inst_28:
// rs2_val == -9,
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x9; immval:0x28
TEST_STORE(x1,x2,0,x10,x11,-0x9,0x28,112,c.sw,0)
inst_29:
// rs2_val == -5,
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x5; immval:0xc
TEST_STORE(x1,x2,0,x10,x11,-0x5,0xc,116,c.sw,0)
inst_30:
// rs2_val == -3, imm_val == 108
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x3; immval:0x6c
TEST_STORE(x1,x2,0,x10,x11,-0x3,0x6c,120,c.sw,0)
inst_31:
// rs2_val == -2, imm_val == 92
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x2; immval:0x5c
TEST_STORE(x1,x2,0,x10,x11,-0x2,0x5c,124,c.sw,0)
inst_32:
// imm_val == 116, rs2_val == 32768
// opcode:c.sw; op1:x10; op2:x11; op2val:0x8000; immval:0x74
TEST_STORE(x1,x2,0,x10,x11,0x8000,0x74,128,c.sw,0)
inst_33:
// rs2_val == -2147483648, rs2_val == (-2**(xlen-1))
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x80000000; immval:0x7c
TEST_STORE(x1,x2,0,x10,x11,-0x80000000,0x7c,132,c.sw,0)
inst_34:
// rs2_val == 1073741824,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x40000000; immval:0x38
TEST_STORE(x1,x2,0,x10,x11,0x40000000,0x38,136,c.sw,0)
inst_35:
// rs2_val == 536870912,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x20000000; immval:0x7c
TEST_STORE(x1,x2,0,x10,x11,0x20000000,0x7c,140,c.sw,0)
inst_36:
// rs2_val == 268435456,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x10000000; immval:0x1c
TEST_STORE(x1,x2,0,x10,x11,0x10000000,0x1c,144,c.sw,0)
inst_37:
// rs2_val == 134217728,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x8000000; immval:0x5c
TEST_STORE(x1,x2,0,x10,x11,0x8000000,0x5c,148,c.sw,0)
inst_38:
// rs2_val == 32,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x20; immval:0x2c
TEST_STORE(x1,x2,0,x10,x11,0x20,0x2c,152,c.sw,0)
inst_39:
// rs2_val == 16,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x10; immval:0x30
TEST_STORE(x1,x2,0,x10,x11,0x10,0x30,156,c.sw,0)
inst_40:
// rs2_val == 8,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x8; immval:0x24
TEST_STORE(x1,x2,0,x10,x11,0x8,0x24,160,c.sw,0)
inst_41:
// rs2_val == 4,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x4; immval:0x7c
TEST_STORE(x1,x2,0,x10,x11,0x4,0x7c,164,c.sw,0)
inst_42:
// rs2_val == 2,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x2; immval:0x34
TEST_STORE(x1,x2,0,x10,x11,0x2,0x34,168,c.sw,0)
inst_43:
// rs2_val == 1,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x1; immval:0x54
TEST_STORE(x1,x2,0,x10,x11,0x1,0x54,172,c.sw,0)
inst_44:
// imm_val == 16,
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x100001; immval:0x10
TEST_STORE(x1,x2,0,x10,x11,-0x100001,0x10,176,c.sw,0)
inst_45:
// imm_val == 8, rs2_val == 524288
// opcode:c.sw; op1:x10; op2:x11; op2val:0x80000; immval:0x8
TEST_STORE(x1,x2,0,x10,x11,0x80000,0x8,180,c.sw,0)
inst_46:
// rs2_val == -1431655766,
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x55555556; immval:0x3c
TEST_STORE(x1,x2,0,x10,x11,-0x55555556,0x3c,184,c.sw,0)
inst_47:
// rs2_val == 1431655765,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x55555555; immval:0x10
TEST_STORE(x1,x2,0,x10,x11,0x55555555,0x10,188,c.sw,0)
inst_48:
// rs2_val == 0,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x0; immval:0x38
TEST_STORE(x1,x2,0,x10,x11,0x0,0x38,192,c.sw,0)
inst_49:
// rs2_val == 67108864,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x4000000; immval:0xc
TEST_STORE(x1,x2,0,x10,x11,0x4000000,0xc,196,c.sw,0)
inst_50:
// rs2_val == 33554432,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x2000000; immval:0x3c
TEST_STORE(x1,x2,0,x10,x11,0x2000000,0x3c,200,c.sw,0)
inst_51:
// rs2_val == 16777216,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x1000000; immval:0x20
TEST_STORE(x1,x2,0,x10,x11,0x1000000,0x20,204,c.sw,0)
inst_52:
// rs2_val == 8388608,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x800000; immval:0x10
TEST_STORE(x1,x2,0,x10,x11,0x800000,0x10,208,c.sw,0)
inst_53:
// rs2_val == 4194304,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x400000; immval:0x0
TEST_STORE(x1,x2,0,x10,x11,0x400000,0x0,212,c.sw,0)
inst_54:
// rs2_val == 2097152,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x200000; immval:0x24
TEST_STORE(x1,x2,0,x10,x11,0x200000,0x24,216,c.sw,0)
inst_55:
// rs2_val == 1048576,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x100000; immval:0x34
TEST_STORE(x1,x2,0,x10,x11,0x100000,0x34,220,c.sw,0)
inst_56:
// rs2_val == 262144,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x40000; immval:0x14
TEST_STORE(x1,x2,0,x10,x11,0x40000,0x14,224,c.sw,0)
inst_57:
// rs2_val == 131072,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x20000; immval:0x20
TEST_STORE(x1,x2,0,x10,x11,0x20000,0x20,228,c.sw,0)
inst_58:
// rs2_val == 65536,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x10000; immval:0x44
TEST_STORE(x1,x2,0,x10,x11,0x10000,0x44,232,c.sw,0)
inst_59:
// rs2_val == 16384,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x4000; immval:0x20
TEST_STORE(x1,x2,0,x10,x11,0x4000,0x20,236,c.sw,0)
inst_60:
// rs2_val == 8192,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x2000; immval:0x78
TEST_STORE(x1,x2,0,x10,x11,0x2000,0x78,240,c.sw,0)
inst_61:
// rs2_val == 4096,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x1000; immval:0x7c
TEST_STORE(x1,x2,0,x10,x11,0x1000,0x7c,244,c.sw,0)
inst_62:
// rs2_val == 2048,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x800; immval:0x6c
TEST_STORE(x1,x2,0,x10,x11,0x800,0x6c,248,c.sw,0)
inst_63:
// rs2_val == 1024,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x400; immval:0x4c
TEST_STORE(x1,x2,0,x10,x11,0x400,0x4c,252,c.sw,0)
inst_64:
// rs2_val == 512,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x200; immval:0x5c
TEST_STORE(x1,x2,0,x10,x11,0x200,0x5c,256,c.sw,0)
inst_65:
// rs2_val == 256,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x100; immval:0x28
TEST_STORE(x1,x2,0,x10,x11,0x100,0x28,260,c.sw,0)
inst_66:
// rs2_val == 128,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x80; immval:0x78
TEST_STORE(x1,x2,0,x10,x11,0x80,0x78,264,c.sw,0)
inst_67:
// rs2_val == 64,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x40; immval:0x3c
TEST_STORE(x1,x2,0,x10,x11,0x40,0x3c,268,c.sw,0)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x1_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x1_1:
.fill 68*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
RVMODEL_DATA_END

425
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cswsp-01.S
View File

@ -1,425 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Mon Sep 13 07:01:20 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32ec.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.swsp instruction of the RISC-V C extension for the cswsp covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32EC")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",cswsp)
RVTEST_SIGBASE( x8,signature_x8_1)
inst_0:
// rs2==x12, imm_val == 0,
// opcode:c.swsp; op1:x2; op2:x12; op2val:0x3; immval:0x0
TEST_STORE(x8,x9,0,x2,x12,0x3,0x0,0,c.swsp,0)
inst_1:
// rs2==x1, rs2_val == 2147483647, imm_val > 0, rs2_val == (2**(xlen-1)-1), imm_val == 236
// opcode:c.swsp; op1:x2; op2:x1; op2val:0x7fffffff; immval:0xec
TEST_STORE(x8,x9,0,x2,x1,0x7fffffff,0xec,4,c.swsp,0)
inst_2:
// rs2==x7, rs2_val == -1073741825,
// opcode:c.swsp; op1:x2; op2:x7; op2val:-0x40000001; immval:0x48
TEST_STORE(x8,x9,0,x2,x7,-0x40000001,0x48,8,c.swsp,0)
inst_3:
// rs2==x13, rs2_val == -536870913,
// opcode:c.swsp; op1:x2; op2:x13; op2val:-0x20000001; immval:0x48
TEST_STORE(x8,x9,0,x2,x13,-0x20000001,0x48,12,c.swsp,0)
inst_4:
// rs2==x2, rs2_val == -268435457, imm_val == 8
// opcode:c.swsp; op1:x2; op2:x2; op2val:-0x10000001; immval:0x8
TEST_STORE(x8,x9,0,x2,x2,-0x10000001,0x8,16,c.swsp,0)
inst_5:
// rs2==x4, rs2_val == -134217729,
// opcode:c.swsp; op1:x2; op2:x4; op2val:-0x8000001; immval:0x28
TEST_STORE(x8,x9,0,x2,x4,-0x8000001,0x28,20,c.swsp,0)
inst_6:
// rs2==x10, rs2_val == -67108865,
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x4000001; immval:0x4c
TEST_STORE(x8,x9,0,x2,x10,-0x4000001,0x4c,24,c.swsp,0)
inst_7:
// rs2==x15, rs2_val == -33554433,
// opcode:c.swsp; op1:x2; op2:x15; op2val:-0x2000001; immval:0x18
TEST_STORE(x8,x9,0,x2,x15,-0x2000001,0x18,28,c.swsp,0)
inst_8:
// rs2==x5, rs2_val == -16777217, imm_val == 244
// opcode:c.swsp; op1:x2; op2:x5; op2val:-0x1000001; immval:0xf4
TEST_STORE(x8,x9,0,x2,x5,-0x1000001,0xf4,32,c.swsp,0)
inst_9:
// rs2==x3, rs2_val == -8388609,
// opcode:c.swsp; op1:x2; op2:x3; op2val:-0x800001; immval:0x4c
TEST_STORE(x8,x9,0,x2,x3,-0x800001,0x4c,36,c.swsp,0)
inst_10:
// rs2==x6, rs2_val == -4194305,
// opcode:c.swsp; op1:x2; op2:x6; op2val:-0x400001; immval:0x30
TEST_STORE(x8,x9,0,x2,x6,-0x400001,0x30,40,c.swsp,0)
inst_11:
// rs2==x9, rs2_val == -2097153, imm_val == 128
// opcode:c.swsp; op1:x2; op2:x9; op2val:-0x200001; immval:0x80
TEST_STORE(x8,x3,0,x2,x9,-0x200001,0x80,44,c.swsp,0)
RVTEST_SIGBASE( x1,signature_x1_0)
inst_12:
// rs2==x11, rs2_val == -1048577, imm_val == 124
// opcode:c.swsp; op1:x2; op2:x11; op2val:-0x100001; immval:0x7c
TEST_STORE(x1,x3,0,x2,x11,-0x100001,0x7c,0,c.swsp,0)
inst_13:
// rs2==x14, rs2_val == -524289,
// opcode:c.swsp; op1:x2; op2:x14; op2val:-0x80001; immval:0x34
TEST_STORE(x1,x3,0,x2,x14,-0x80001,0x34,4,c.swsp,0)
inst_14:
// rs2==x8, rs2_val == -262145, imm_val == 168
// opcode:c.swsp; op1:x2; op2:x8; op2val:-0x40001; immval:0xa8
TEST_STORE(x1,x3,0,x2,x8,-0x40001,0xa8,8,c.swsp,0)
inst_15:
// rs2_val == -131073,
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x20001; immval:0xf4
TEST_STORE(x1,x3,0,x2,x10,-0x20001,0xf4,12,c.swsp,0)
inst_16:
// rs2_val == -65537,
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x10001; immval:0x3c
TEST_STORE(x1,x3,0,x2,x10,-0x10001,0x3c,16,c.swsp,0)
inst_17:
// rs2_val == -32769,
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x8001; immval:0x1c
TEST_STORE(x1,x3,0,x2,x10,-0x8001,0x1c,20,c.swsp,0)
inst_18:
// rs2_val == -16385, imm_val == 4
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x4001; immval:0x4
TEST_STORE(x1,x3,0,x2,x10,-0x4001,0x4,24,c.swsp,0)
inst_19:
// rs2_val == -8193,
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x2001; immval:0xa8
TEST_STORE(x1,x3,0,x2,x10,-0x2001,0xa8,28,c.swsp,0)
inst_20:
// rs2_val == -4097, imm_val == 248
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x1001; immval:0xf8
TEST_STORE(x1,x3,0,x2,x10,-0x1001,0xf8,32,c.swsp,0)
inst_21:
// rs2_val == -2049, imm_val == 64
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x801; immval:0x40
TEST_STORE(x1,x3,0,x2,x10,-0x801,0x40,36,c.swsp,0)
inst_22:
// rs2_val == -1025,
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x401; immval:0xc
TEST_STORE(x1,x3,0,x2,x10,-0x401,0xc,40,c.swsp,0)
inst_23:
// rs2_val == -513,
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x201; immval:0x38
TEST_STORE(x1,x3,0,x2,x10,-0x201,0x38,44,c.swsp,0)
inst_24:
// rs2_val == -257, imm_val == 220
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x101; immval:0xdc
TEST_STORE(x1,x3,0,x2,x10,-0x101,0xdc,48,c.swsp,0)
inst_25:
// rs2_val == -129, imm_val == 32
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x81; immval:0x20
TEST_STORE(x1,x3,0,x2,x10,-0x81,0x20,52,c.swsp,0)
inst_26:
// rs2_val == -65,
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x41; immval:0x34
TEST_STORE(x1,x3,0,x2,x10,-0x41,0x34,56,c.swsp,0)
inst_27:
// rs2_val == -33,
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x21; immval:0xf8
TEST_STORE(x1,x3,0,x2,x10,-0x21,0xf8,60,c.swsp,0)
inst_28:
// rs2_val == -17,
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x11; immval:0x4c
TEST_STORE(x1,x3,0,x2,x10,-0x11,0x4c,64,c.swsp,0)
inst_29:
// rs2_val == -9,
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x9; immval:0x30
TEST_STORE(x1,x3,0,x2,x10,-0x9,0x30,68,c.swsp,0)
inst_30:
// rs2_val == -5,
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x5; immval:0x3c
TEST_STORE(x1,x3,0,x2,x10,-0x5,0x3c,72,c.swsp,0)
inst_31:
// rs2_val == -3,
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x3; immval:0x80
TEST_STORE(x1,x3,0,x2,x10,-0x3,0x80,76,c.swsp,0)
inst_32:
// rs2_val == -2,
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x2; immval:0x24
TEST_STORE(x1,x3,0,x2,x10,-0x2,0x24,80,c.swsp,0)
inst_33:
// imm_val == 188,
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x8001; immval:0xbc
TEST_STORE(x1,x3,0,x2,x10,-0x8001,0xbc,84,c.swsp,0)
inst_34:
// rs2_val == -2147483648, rs2_val == (-2**(xlen-1))
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x80000000; immval:0x20
TEST_STORE(x1,x3,0,x2,x10,-0x80000000,0x20,88,c.swsp,0)
inst_35:
// rs2_val == 1073741824,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x40000000; immval:0x38
TEST_STORE(x1,x3,0,x2,x10,0x40000000,0x38,92,c.swsp,0)
inst_36:
// rs2_val == 536870912,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x20000000; immval:0x7c
TEST_STORE(x1,x3,0,x2,x10,0x20000000,0x7c,96,c.swsp,0)
inst_37:
// rs2_val == 268435456,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x10000000; immval:0xfc
TEST_STORE(x1,x3,0,x2,x10,0x10000000,0xfc,100,c.swsp,0)
inst_38:
// rs2_val == 134217728,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x8000000; immval:0x48
TEST_STORE(x1,x3,0,x2,x10,0x8000000,0x48,104,c.swsp,0)
inst_39:
// rs2_val == 67108864, imm_val == 84
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x4000000; immval:0x54
TEST_STORE(x1,x3,0,x2,x10,0x4000000,0x54,108,c.swsp,0)
inst_40:
// rs2_val == 64, imm_val == 16
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x40; immval:0x10
TEST_STORE(x1,x3,0,x2,x10,0x40,0x10,112,c.swsp,0)
inst_41:
// rs2_val == 32,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x20; immval:0x14
TEST_STORE(x1,x3,0,x2,x10,0x20,0x14,116,c.swsp,0)
inst_42:
// rs2_val == 16,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x10; immval:0x4c
TEST_STORE(x1,x3,0,x2,x10,0x10,0x4c,120,c.swsp,0)
inst_43:
// rs2_val == 8,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x8; immval:0x4c
TEST_STORE(x1,x3,0,x2,x10,0x8,0x4c,124,c.swsp,0)
inst_44:
// rs2_val == 4,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x4; immval:0xf8
TEST_STORE(x1,x3,0,x2,x10,0x4,0xf8,128,c.swsp,0)
inst_45:
// rs2_val == 2,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x2; immval:0x2c
TEST_STORE(x1,x3,0,x2,x10,0x2,0x2c,132,c.swsp,0)
inst_46:
// rs2_val == 1,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x1; immval:0xbc
TEST_STORE(x1,x3,0,x2,x10,0x1,0xbc,136,c.swsp,0)
inst_47:
// rs2_val == -1431655766,
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x55555556; immval:0xdc
TEST_STORE(x1,x3,0,x2,x10,-0x55555556,0xdc,140,c.swsp,0)
inst_48:
// rs2_val == 1431655765,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x55555555; immval:0x4c
TEST_STORE(x1,x3,0,x2,x10,0x55555555,0x4c,144,c.swsp,0)
inst_49:
// rs2_val == 0,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x0; immval:0x40
TEST_STORE(x1,x3,0,x2,x10,0x0,0x40,148,c.swsp,0)
inst_50:
// rs2_val == 33554432,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x2000000; immval:0x4
TEST_STORE(x1,x3,0,x2,x10,0x2000000,0x4,152,c.swsp,0)
inst_51:
// rs2_val == 16777216,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x1000000; immval:0x7c
TEST_STORE(x1,x3,0,x2,x10,0x1000000,0x7c,156,c.swsp,0)
inst_52:
// rs2_val == 8388608,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x800000; immval:0x18
TEST_STORE(x1,x3,0,x2,x10,0x800000,0x18,160,c.swsp,0)
inst_53:
// rs2_val == 4194304,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x400000; immval:0x40
TEST_STORE(x1,x3,0,x2,x10,0x400000,0x40,164,c.swsp,0)
inst_54:
// rs2_val == 2097152,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x200000; immval:0x54
TEST_STORE(x1,x3,0,x2,x10,0x200000,0x54,168,c.swsp,0)
inst_55:
// rs2_val == 1048576,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x100000; immval:0x34
TEST_STORE(x1,x3,0,x2,x10,0x100000,0x34,172,c.swsp,0)
inst_56:
// rs2_val == 524288,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x80000; immval:0x20
TEST_STORE(x1,x3,0,x2,x10,0x80000,0x20,176,c.swsp,0)
inst_57:
// rs2_val == 262144,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x40000; immval:0x44
TEST_STORE(x1,x3,0,x2,x10,0x40000,0x44,180,c.swsp,0)
inst_58:
// rs2_val == 131072,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x20000; immval:0xa8
TEST_STORE(x1,x3,0,x2,x10,0x20000,0xa8,184,c.swsp,0)
inst_59:
// rs2_val == 65536,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x10000; immval:0x3c
TEST_STORE(x1,x3,0,x2,x10,0x10000,0x3c,188,c.swsp,0)
inst_60:
// rs2_val == 32768,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x8000; immval:0x34
TEST_STORE(x1,x3,0,x2,x10,0x8000,0x34,192,c.swsp,0)
inst_61:
// rs2_val == 16384,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x4000; immval:0xc
TEST_STORE(x1,x3,0,x2,x10,0x4000,0xc,196,c.swsp,0)
inst_62:
// rs2_val == 8192,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x2000; immval:0x4
TEST_STORE(x1,x3,0,x2,x10,0x2000,0x4,200,c.swsp,0)
inst_63:
// rs2_val == 4096,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x1000; immval:0x30
TEST_STORE(x1,x3,0,x2,x10,0x1000,0x30,204,c.swsp,0)
inst_64:
// rs2_val == 2048,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x800; immval:0x38
TEST_STORE(x1,x3,0,x2,x10,0x800,0x38,208,c.swsp,0)
inst_65:
// rs2_val == 1024,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x400; immval:0x10
TEST_STORE(x1,x3,0,x2,x10,0x400,0x10,212,c.swsp,0)
inst_66:
// rs2_val == 512,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x200; immval:0x3c
TEST_STORE(x1,x3,0,x2,x10,0x200,0x3c,216,c.swsp,0)
inst_67:
// rs2_val == 256,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x100; immval:0x1c
TEST_STORE(x1,x3,0,x2,x10,0x100,0x1c,220,c.swsp,0)
inst_68:
// rs2_val == 128,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x80; immval:0xf8
TEST_STORE(x1,x3,0,x2,x10,0x80,0xf8,224,c.swsp,0)
inst_69:
// rs2_val == -268435457, imm_val == 8
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x10000001; immval:0x8
TEST_STORE(x1,x3,0,x2,x10,-0x10000001,0x8,228,c.swsp,0)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x8_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x8_1:
.fill 12*(XLEN/32),4,0xdeadbeef
signature_x1_0:
.fill 58*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
RVMODEL_DATA_END

2975
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cxor-01.S
View File

File diff suppressed because it is too large Load Diff

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/Makefile
View File

@ -1,3 +0,0 @@
include ../../Makefile.include
$(eval $(call compile_template,-march=rv32em -mabi=ilp32e -DXLEN=$(XLEN)))

43
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/Makefrag
View File

@ -1,43 +0,0 @@
# RISC-V Architecture Test RV32EM Makefrag
#
# Copyright (c) 2018, Imperas Software Ltd.
# Copyright (c) 2020, InCore Semiconductors. Pvt. Ltd.
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
# * Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# * Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# * Neither the name of the Imperas Software Ltd. nor the
# names of its contributors may be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY
# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Description: Makefrag for RV32EM architectural tests
rv32em_sc_tests = \
div-01 \
divu-01 \
mul-01 \
mulh-01 \
mulhsu-01 \
mulhu-01 \
rem-01 \
remu-01
rv32em_tests = $(addsuffix .elf, $(rv32em_sc_tests))
target_tests += $(rv32em_tests)

2990
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/src/div-01.S
View File

File diff suppressed because it is too large Load Diff

3730
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/src/divu-01.S
View File

File diff suppressed because it is too large Load Diff

3010
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/src/mul-01.S
View File

File diff suppressed because it is too large Load Diff

3040
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/src/mulh-01.S
View File

File diff suppressed because it is too large Load Diff

3355
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/src/mulhsu-01.S
View File

File diff suppressed because it is too large Load Diff

3700
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/src/mulhu-01.S
View File

File diff suppressed because it is too large Load Diff

3015
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/src/rem-01.S
View File

File diff suppressed because it is too large Load Diff

3715
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/src/remu-01.S
View File

File diff suppressed because it is too large Load Diff