Rose Thompson 5d4a89b27c Fixed bug in the btb branch logging. ... We were only logging branch instructions not all control flow instructions which dramatically skewed the results for sim_bp.		2023-11-15 14:51:47 -06:00
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common	Fixed bug in the btb branch logging.	2023-11-15 14:51:47 -06:00
fp	Removed pipelined level of hierarchy	2023-02-02 14:14:11 -08:00
sdc	Towards removing the FPGA config file.	2023-11-13 17:20:26 -06:00
testbench-fp.sv	Testbench fixes to add SPI and make string pp static in testbench.fp to solve compiler issue	2023-11-04 20:36:05 -07:00
testbench-imperas.sv	Fixed the imperas testbench to be compatible with the config changes.	2023-11-14 12:57:44 -06:00
testbench-linux-imperas.sv	Patched up linux imperas testbench.	2023-11-14 14:20:13 -06:00
testbench-linux.sv	Testbench fixes to add SPI and make string pp static in testbench.fp to solve compiler issue	2023-11-04 20:36:05 -07:00
testbench-xcelium.sv	Testbench fixes to add SPI and make string pp static in testbench.fp to solve compiler issue	2023-11-04 20:36:05 -07:00
testbench.sv	Commented out the arch64priv misaligned load/store tests since we added Zicclsm to the rv64gc config.	2023-11-13 14:12:27 -06:00
tests-fp.vh	Update testbench-fp to run TestFloat for all FP operations	2023-04-11 22:16:20 -05:00
tests.vh	Commented out the arch64priv misaligned load/store tests since we added Zicclsm to the rv64gc config.	2023-11-13 14:12:27 -06:00
wallywrapper.sv	Verilator improvements	2023-11-04 03:21:07 -07:00