mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-02 17:55:19 +00:00
Major cleanup of testbench.
This commit is contained in:
Ross Thompson
parent
87fb9a3e16
commit
af046d4772
@ -87,8 +87,6 @@ module testbench;
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logic Validate;
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logic SelectTest;
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// check assertions for a legal configuration
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riscvassertions #(P) riscvassertions();
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// pick tests based on modes supported
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initial begin
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@ -204,89 +202,52 @@ module testbench;
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if (TestBenchReset) CurrState <= #1 STATE_TESTBENCH_RESET;
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else CurrState <= #1 NextState;
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// fsm next state logic
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always_comb begin
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reset_ext = 0;
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ResetMem = 0;
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LoadMem = 0;
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ResetCntEn = 0;
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ResetCntRst = 0;
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Validate = 0;
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SelectTest = 0;
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// riscof tests have a different signature, tests[0] == "1" refers to RiscvArchTests
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// and tests[0] == "2" refers to WallyRiscvArchTests
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riscofTest = tests[0] == "1" | tests[0] == "2";
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pathname = tvpaths[tests[0].atoi()];
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case(CurrState)
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STATE_TESTBENCH_RESET: begin
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NextState = STATE_INIT_TEST;
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reset_ext = 1;
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end
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STATE_INIT_TEST: begin
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NextState = STATE_RESET_MEMORIES;
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ResetCntRst = 1;
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SelectTest = 1;
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reset_ext = 1;
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end
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STATE_RESET_MEMORIES: begin
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NextState = STATE_RESET_MEMORIES2;
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reset_ext = 1;
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if (TEST == "coremark") ResetMem = 1; // this initialization is very expensive, only do it for coremark.
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end
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STATE_RESET_MEMORIES2: begin // Give the reset enough time to ensure the bus is reset before loading the memories.
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NextState = STATE_LOAD_MEMORIES;
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reset_ext = 1;
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// this initialization is very expensive, only do it for coremark.
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if (TEST == "coremark") ResetMem = 1;
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end
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STATE_LOAD_MEMORIES: begin
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NextState = STATE_RESET_TEST;
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reset_ext = 1;
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LoadMem = 1;
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end
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STATE_RESET_TEST: begin
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reset_ext = 1;
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ResetCntEn = 1;
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if(ResetCount < ResetThreshold) begin
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NextState = STATE_RESET_TEST;
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end else begin
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NextState = STATE_RUN_TEST;
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end
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end
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STATE_RUN_TEST:
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if(DCacheFlushStart) begin
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NextState = STATE_CHECK_TEST;
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end else begin
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NextState = STATE_RUN_TEST;
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end
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STATE_CHECK_TEST: begin
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if (DCacheFlushDone) begin
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NextState = STATE_VALIDATE;
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end else begin
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NextState = STATE_CHECK_TEST_WAIT;
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end
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end
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STATE_CHECK_TEST_WAIT: begin
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if(DCacheFlushDone) begin
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NextState = STATE_VALIDATE;
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end else begin
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NextState = STATE_CHECK_TEST_WAIT;
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end
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end
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STATE_VALIDATE: begin
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NextState = STATE_INIT_TEST;
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Validate = '1;
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end
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STATE_INCR_TEST: begin
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NextState = STATE_INIT_TEST;
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end
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default: NextState = STATE_TESTBENCH_RESET;
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STATE_TESTBENCH_RESET: NextState = STATE_INIT_TEST;
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STATE_INIT_TEST: NextState = STATE_RESET_MEMORIES;
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STATE_RESET_MEMORIES: NextState = STATE_RESET_MEMORIES2;
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STATE_RESET_MEMORIES2: NextState = STATE_LOAD_MEMORIES; // Give the reset enough time to ensure the bus is reset before loading the memories.
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STATE_LOAD_MEMORIES: NextState = STATE_RESET_TEST;
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STATE_RESET_TEST: if(ResetCount < ResetThreshold) NextState = STATE_RESET_TEST;
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else NextState = STATE_RUN_TEST;
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STATE_RUN_TEST: if(DCacheFlushStart) NextState = STATE_CHECK_TEST;
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else NextState = STATE_RUN_TEST;
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STATE_CHECK_TEST: if (DCacheFlushDone) NextState = STATE_VALIDATE;
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else NextState = STATE_CHECK_TEST_WAIT;
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STATE_CHECK_TEST_WAIT: if(DCacheFlushDone) NextState = STATE_VALIDATE;
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else NextState = STATE_CHECK_TEST_WAIT;
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STATE_VALIDATE: NextState = STATE_INIT_TEST;
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STATE_INCR_TEST: NextState = STATE_INIT_TEST;
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default: NextState = STATE_TESTBENCH_RESET;
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endcase
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end // always_comb
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// fsm output control logic
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assign reset_ext = CurrState == STATE_TESTBENCH_RESET | CurrState == STATE_INIT_TEST |
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CurrState == STATE_RESET_MEMORIES | CurrState == STATE_RESET_MEMORIES2 |
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CurrState == STATE_LOAD_MEMORIES | CurrState ==STATE_RESET_TEST;
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// this initialization is very expensive, only do it for coremark.
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assign ResetMem = (CurrState == STATE_RESET_MEMORIES | CurrState == STATE_RESET_MEMORIES2) & TEST == "coremark";
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assign LoadMem = CurrState == STATE_LOAD_MEMORIES;
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assign ResetCntRst = CurrState == STATE_INIT_TEST;
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assign ResetCntEn = CurrState == STATE_RESET_TEST;
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assign Validate = CurrState == STATE_VALIDATE;
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assign SelectTest = CurrState == STATE_INIT_TEST;
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// fsm reset counter
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counter #(3) RstCounter(clk, ResetCntRst, ResetCntEn, ResetCount);
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////////////////////////////////////////////////////////////////////////////////
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// Find the test vector files and populate the PC to function label converter
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////////////////////////////////////////////////////////////////////////////////
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assign begin_signature_addr = ProgramAddrLabelArray["begin_signature"];
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always @(posedge clk) begin
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if(SelectTest) begin
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if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"};
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else memfilename = {pathname, tests[test], ".elf.memfile"};
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@ -305,14 +266,17 @@ module testbench;
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end
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end
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////////////////////////////////////////////////////////////////////////////////
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// Verify the test ran correctly by checking the memory against a known signature.
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////////////////////////////////////////////////////////////////////////////////
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if(TestBenchReset) test = 1;
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if (TEST == "coremark")
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if (dut.core.EcallFaultM) begin
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$display("Benchmark: coremark is done.");
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$stop;
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end
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if(Validate) begin
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if (TEST == "coremark")
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if (dut.core.EcallFaultM) begin
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$display("Benchmark: coremark is done.");
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$stop;
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end
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else if (TEST == "embench") begin
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if (TEST == "embench") begin
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// Writes contents of begin_signature to .sim.output file
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// this contains instret and cycles for start and end of test run, used by embench
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// python speed script to calculate embench speed score.
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@ -347,13 +311,10 @@ module testbench;
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end
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end
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counter #(3) RstCounter(clk, ResetCntRst, ResetCntEn, ResetCount);
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assign begin_signature_addr = ProgramAddrLabelArray["begin_signature"];
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////////////////////////////////////////////////////////////////////////////////
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// Some memories are not reset, but should be zeros or set to some initial value for simulation
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////////////////////////////////////////////////////////////////////////////////
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integer adrindex;
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always @(posedge clk) begin
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if (ResetMem) // program memory is sometimes reset
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@ -394,8 +355,11 @@ module testbench;
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$display("Read memfile %s", memfilename);
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end
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end
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////////////////////////////////////////////////////////////////////////////////
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// Actual hardware
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////////////////////////////////////////////////////////////////////////////////
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// instantiate device to be tested
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assign GPIOIN = 0;
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assign UARTSin = 1;
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@ -403,12 +367,10 @@ module testbench;
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if(P.EXT_MEM_SUPPORTED) begin
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ram_ahb #(.BASE(P.EXT_MEM_BASE), .RANGE(P.EXT_MEM_RANGE))
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ram (.HCLK, .HRESETn, .HADDR, .HWRITE, .HTRANS, .HWDATA, .HSELRam(HSELEXT),
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.HREADRam(HRDATAEXT), .HREADYRam(HREADYEXT), .HRESPRam(HRESPEXT), .HREADY,
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.HWSTRB);
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.HREADRam(HRDATAEXT), .HREADYRam(HREADYEXT), .HRESPRam(HRESPEXT), .HREADY, .HWSTRB);
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end else begin
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assign HREADYEXT = 1;
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assign HRESPEXT = 0;
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assign HRDATAEXT = 0;
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assign {HRESPEXT, HRDATAEXT} = '0;
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end
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if(P.FPGA) begin : sdcard
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@ -426,9 +388,29 @@ module testbench;
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end
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wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT,
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.HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
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.HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN,
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.UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK);
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.HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
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.HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN,
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.UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK);
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// generate clock to sequence tests
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always begin
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clk = 1; # 5; clk = 0; # 5;
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end
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////////////////////////////////////////////////////////////////////////////////
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// Support logic
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////////////////////////////////////////////////////////////////////////////////
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watchdog #(P.XLEN, 1000000) watchdog(.clk, .reset); // check if PCW is stuck
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riscvassertions #(P) riscvassertions(); // check assertions for a legal configuration
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loggers #(P, TEST, PrintHPMCounters, I_CACHE_ADDR_LOGGER, D_CACHE_ADDR_LOGGER, BPRED_LOGGER)
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loggers (clk, reset, DCacheFlushStart, DCacheFlushDone, memfilename);
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// track the current function or global label
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if (DEBUG == 1 | (PrintHPMCounters & P.ZICOUNTERS_SUPPORTED)) begin : FunctionName
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FunctionName #(P) FunctionName(.reset(reset_ext | TestBenchReset),
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.clk(clk), .ProgramAddrMapFile(ProgramAddrMapFile), .ProgramLabelMapFile(ProgramLabelMapFile));
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end
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// Track names of instructions
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string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
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@ -440,22 +422,6 @@ module testbench;
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dut.core.ifu.InstrM, InstrW,
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InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
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// generate clock to sequence tests
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always
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begin
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clk = 1; # 5; clk = 0; # 5;
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// if ($time % 100000 == 0) $display("Time is %0t", $time);
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end
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// track the current function or global label
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if (DEBUG == 1 | (PrintHPMCounters & P.ZICOUNTERS_SUPPORTED)) begin : FunctionName
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FunctionName #(P) FunctionName(.reset(reset_ext | TestBenchReset),
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.clk(clk),
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.ProgramAddrMapFile(ProgramAddrMapFile),
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.ProgramLabelMapFile(ProgramLabelMapFile));
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end
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// Termination condition
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// terminate on a specific ECALL after li x3,1 for old Imperas tests, *** remove this when old imperas tests are removed
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// or sw gp,-56(t0) for new Imperas tests
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@ -472,14 +438,7 @@ module testbench;
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((dut.core.ifu.InstrM == 32'h6f | dut.core.ifu.InstrM == 32'hfc32a423 | dut.core.ifu.InstrM == 32'hfc32a823) & dut.core.ieu.c.InstrValidM ) |
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((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"]) & InstrMName == "SW" );
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DCacheFlushFSM #(P) DCacheFlushFSM(.clk(clk),
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.reset(reset),
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.start(DCacheFlushStart),
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.done(DCacheFlushDone));
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watchdog #(P.XLEN, 1000000) watchdog(.clk, .reset);
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loggers #(P, TEST, PrintHPMCounters, I_CACHE_ADDR_LOGGER, D_CACHE_ADDR_LOGGER, BPRED_LOGGER)
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loggers (clk, reset, DCacheFlushStart, DCacheFlushDone, memfilename);
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DCacheFlushFSM #(P) DCacheFlushFSM(.clk(clk), .reset(reset), .start(DCacheFlushStart), .done(DCacheFlushDone));
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task automatic CheckSignature;
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// This task must be declared inside this module as it needs access to parameter P. There is
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