James E. Stine 79d7bb60ea Address Issue #541 where CVTINT or CMP in testfloat were not checked. The solution was to check inside the nested for loop. This was done to avoid issue related to the values changing between each cvtint or subsequent operation		2024-01-08 21:28:47 -06:00
..
common	Reverted logic to bit change.	2023-12-20 13:16:32 -06:00
fp	Removed pipelined level of hierarchy	2023-02-02 14:14:11 -08:00
sdc	Towards removing the FPGA config file.	2023-11-13 17:20:26 -06:00
testbench-fp.sv	Address Issue #541 where CVTINT or CMP in testfloat were not checked. The solution was to check inside the nested for loop. This was done to avoid issue related to the values changing between each cvtint or subsequent operation	2024-01-08 21:28:47 -06:00
testbench-imperas.sv	Propagated MIP-based tracer interrupts to testbench-linux-imperas	2023-12-21 11:47:49 -08:00
testbench-linux-imperas.sv	Propagated MIP-based tracer interrupts to testbench-linux-imperas	2023-12-21 11:47:49 -08:00
testbench-linux.sv	Testbench fixes to add SPI and make string pp static in testbench.fp to solve compiler issue	2023-11-04 20:36:05 -07:00
testbench-xcelium.sv	Testbench fixes to add SPI and make string pp static in testbench.fp to solve compiler issue	2023-11-04 20:36:05 -07:00
testbench.sv	Verilate running (slowly)	2024-01-07 21:30:33 -08:00
tests-fp.vh	Update testbench-fp to run TestFloat for all FP operations	2023-04-11 22:16:20 -05:00
tests.vh	Coverage improvements; remove incorrect logic checking NAPOT nonleaf PTE	2024-01-02 00:35:17 -08:00
wallywrapper.sv	Verilator improvements	2023-11-04 03:21:07 -07:00