Rose Thompson 70d0169019 All regression tests which matter are running!		2023-12-20 14:57:52 -06:00
..
common	Reverted logic to bit change.	2023-12-20 13:16:32 -06:00
fp	Removed pipelined level of hierarchy	2023-02-02 14:14:11 -08:00
sdc	Towards removing the FPGA config file.	2023-11-13 17:20:26 -06:00
testbench-fp.sv	Fix issue with running all and then going from one operand width to another. Issue is due to signals resolving between sizes. I did not catch it before because I did not run through the complete exhaustive tests. This time, went through all tests and tested all the data sizes.	2023-12-17 20:55:06 -06:00
testbench-imperas.sv	Added SPI support to Imperas testbenches	2023-12-07 09:44:31 -08:00
testbench-linux-imperas.sv	Added SPI support to Imperas testbenches	2023-12-07 09:44:31 -08:00
testbench-linux.sv	Testbench fixes to add SPI and make string pp static in testbench.fp to solve compiler issue	2023-11-04 20:36:05 -07:00
testbench-xcelium.sv	Testbench fixes to add SPI and make string pp static in testbench.fp to solve compiler issue	2023-11-04 20:36:05 -07:00
testbench.sv	All regression tests which matter are running!	2023-12-20 14:57:52 -06:00
tests-fp.vh	Update testbench-fp to run TestFloat for all FP operations	2023-04-11 22:16:20 -05:00
tests.vh	Commented out the arch64priv misaligned load/store tests since we added Zicclsm to the rv64gc config.	2023-11-13 14:12:27 -06:00
wallywrapper.sv	Verilator improvements	2023-11-04 03:21:07 -07:00