cvw/testbench
Alec Vercruysse cd803bfa44 Cover CacheWay edge case: CacheDataMem we=1 while ce=0.
This test basically triggers an i$ miss during a d$ (hit) store
operation. It requires some tricky timing (e.g. a flushD right
before the relevant store). I use a script to generate the test.
2023-04-19 01:34:01 -07:00
..
common Added SSTC support to imperas.ic and wallyTracer. Fixes many of the privileged tests 2023-03-31 10:54:03 -07:00
fp Removed pipelined level of hierarchy 2023-02-02 14:14:11 -08:00
sdc Removed pipelined level of hierarchy 2023-02-02 14:14:11 -08:00
testbench_imperas.sv fix break to simulation testbench 2023-04-06 14:45:41 +01:00
testbench-fp.sv Update testbench-fp to run TestFloat for all FP operations 2023-04-11 22:16:20 -05:00
testbench-linux-imperas.sv add support for Sstc 2023-04-04 17:20:00 +01:00
testbench-linux.sv Updated GPIO signal names to reflect book. 2023-03-24 18:55:43 -05:00
testbench.sv Finished up testbench reformatting 2023-04-13 19:18:26 -07:00
tests-fp.vh Update testbench-fp to run TestFloat for all FP operations 2023-04-11 22:16:20 -05:00
tests.vh Cover CacheWay edge case: CacheDataMem we=1 while ce=0. 2023-04-19 01:34:01 -07:00