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Updated tests with ending label.

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This commit is contained in:
Rose Thompson 2023-12-20 14:55:37 -06:00
parent b68dd74f89
commit 1b59182d59
128 changed files with 414 additions and 71 deletions
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102
testbench/testbench.sv
View File

@ -37,7 +37,7 @@ module testbench;
parameter DEBUG=0;
parameter TEST="none";
parameter PrintHPMCounters=0;
parameter BPRED_LOGGER=1;
parameter BPRED_LOGGER=0;
parameter I_CACHE_ADDR_LOGGER=0;
parameter D_CACHE_ADDR_LOGGER=0;
@ -190,7 +190,7 @@ module testbench;
logic CopyRAM;
string signame, memfilename, pathname;
integer begin_signature_addr;
integer begin_signature_addr, end_signature_addr, signature_size;
assign ResetThreshold = 3'd5;
@ -253,6 +253,8 @@ module testbench;
////////////////////////////////////////////////////////////////////////////////
logic [P.XLEN-1:0] testadr;
assign begin_signature_addr = ProgramAddrLabelArray["begin_signature"];
assign end_signature_addr = ProgramAddrLabelArray["sig_end_canary"];
assign signature_size = end_signature_addr - begin_signature_addr;
always @(posedge clk) begin
if(SelectTest) begin
if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"};
@ -321,70 +323,15 @@ module testbench;
end
////////////////////////////////////////////////////////////////////////////////
// Some memories are not reset, but should be zeros or set to some initial value for simulation
////////////////////////////////////////////////////////////////////////////////
/* -----\/----- EXCLUDED -----\/-----
integer adrindex;
always @(posedge clk) begin
if (ResetMem) // program memory is sometimes reset
if (P.UNCORE_RAM_SUPPORTED)
for (adrindex=0; adrindex<(P.UNCORE_RAM_RANGE>>1+(P.XLEN/32)); adrindex = adrindex+1)
dut.uncore.uncore.ram.ram.memory.RAM[adrindex] = '0;
if(reset) begin // branch predictor must always be reset
if (P.BPRED_SUPPORTED) begin
// local history only
if (P.BPRED_TYPE == `BP_LOCAL_AHEAD | P.BPRED_TYPE == `BP_LOCAL_REPAIR)
for(adrindex = 0; adrindex < 2**P.BPRED_NUM_LHR; adrindex++)
dut.core.ifu.bpred.bpred.Predictor.DirPredictor.BHT.mem[adrindex] = 0;
for(adrindex = 0; adrindex < 2**P.BTB_SIZE; adrindex++)
dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0;
for(adrindex = 0; adrindex < 2**P.BPRED_SIZE; adrindex++)
dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0;
end
end
end
-----/\----- EXCLUDED -----/\----- */
// still not working in this format
/* -----\/----- EXCLUDED -----\/-----
integer adrindex;
if (P.UNCORE_RAM_SUPPORTED) begin
always @(posedge clk) begin
if (ResetMem) // program memory is sometimes reset
for (adrindex=0; adrindex<(P.UNCORE_RAM_RANGE>>1+(P.XLEN/32)); adrindex = adrindex+1)
dut.uncore.uncore.ram.ram.memory.RAM[adrindex] = '0;
end
end
genvar adrindex2;
if (P.BPRED_SUPPORTED & (P.BPRED_TYPE == `BP_LOCAL_AHEAD | P.BPRED_TYPE == `BP_LOCAL_REPAIR)) begin
for(adrindex2 = 0; adrindex2 < 2**P.BPRED_NUM_LHR; adrindex2++)
always @(posedge clk) begin
dut.core.ifu.bpred.bpred.Predictor.DirPredictor.BHT.mem[adrindex2] = 0;
end
end
if (P.BPRED_SUPPORTED) begin
always @(posedge clk)
dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[0] = 0;
for(adrindex2 = 0; adrindex2 < 2**P.BTB_SIZE; adrindex2++)
always @(posedge clk) begin
dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex2] = 0;
end
for(adrindex2 = 0; adrindex2 < 2**P.BPRED_SIZE; adrindex2++)
always @(posedge clk) begin
dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex2] = 0;
end
end
-----/\----- EXCLUDED -----/\----- */
////////////////////////////////////////////////////////////////////////////////
// load memories with program image
////////////////////////////////////////////////////////////////////////////////
integer IndexTemp;
integer ShadowIndex;
integer LogXLEN;
integer StartIndex;
integer EndIndex;
integer BaseIndex;
if (P.SDC_SUPPORTED) begin
always @(posedge clk) begin
if (LoadMem) begin
@ -403,15 +350,20 @@ module testbench;
$readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
end
end
end else if (P.BUS_SUPPORTED) begin
end else if (P.BUS_SUPPORTED) begin : bus_supported
always @(posedge clk) begin
if (LoadMem) begin
$readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
end
if (CopyRAM) begin
for(IndexTemp = 0; IndexTemp < (P.UNCORE_RAM_RANGE)>>1+(P.XLEN/32); IndexTemp++) begin
//if(dut.uncore.uncore.ram.ram.memory.RAM[IndexTemp] === 'bx) break; // end copy early if at the end of the sig *** double check this will be valid for all tests.
testbench.DCacheFlushFSM.ShadowRAM[((P.UNCORE_RAM_BASE)>>1+(P.XLEN/32)) + IndexTemp] = dut.uncore.uncore.ram.ram.memory.RAM[IndexTemp];
LogXLEN = (1 + P.XLEN/32); // 2 for rv32 and 3 for rv64
StartIndex = begin_signature_addr >> LogXLEN;
EndIndex = (end_signature_addr >> LogXLEN) + 8;
BaseIndex = P.UNCORE_RAM_BASE >> LogXLEN;
$display("Copying from uncore RAM to shadow RAM. begin_signature_addr = %x, end_signature_addr = %x, StartIndex = %x, EndIndex = %x, BaseIndex = %x, LogXLEN = %x",
begin_signature_addr, end_signature_addr, StartIndex, EndIndex, BaseIndex, LogXLEN);
for(ShadowIndex = StartIndex; ShadowIndex <= EndIndex; ShadowIndex++) begin
testbench.DCacheFlushFSM.ShadowRAM[ShadowIndex] = dut.uncore.uncore.ram.ram.memory.RAM[ShadowIndex - BaseIndex];
end
end
end
@ -423,9 +375,14 @@ module testbench;
$display("Read memfile %s", memfilename);
end
if (CopyRAM) begin
for(IndexTemp = 0; IndexTemp < (P.DTIM_RANGE)>>1+(P.XLEN/32); IndexTemp++) begin
//if(dut.core.lsu.dtim.dtim.ram.RAM[IndexTemp] === 'bx) break; // end copy early if at the end of the sig *** double check this will be valid for all tests.
testbench.DCacheFlushFSM.ShadowRAM[((P.DTIM_BASE)>>1+(P.XLEN/32)) + IndexTemp] = dut.core.lsu.dtim.dtim.ram.RAM[IndexTemp];
LogXLEN = (1 + P.XLEN/32); // 2 for rv32 and 3 for rv64
StartIndex = begin_signature_addr >> LogXLEN;
EndIndex = (end_signature_addr >> LogXLEN) + 8;
BaseIndex = P.UNCORE_RAM_BASE >> LogXLEN;
$display("Copying from uncore RAM to shadow RAM. begin_signature_addr = %x, end_signature_addr = %x, StartIndex = %x, EndIndex = %x, BaseIndex = %x, LogXLEN = %x",
begin_signature_addr, end_signature_addr, StartIndex, EndIndex, BaseIndex, LogXLEN);
for(ShadowIndex = StartIndex; ShadowIndex <= EndIndex; ShadowIndex++) begin
testbench.DCacheFlushFSM.ShadowRAM[ShadowIndex] = dut.core.lsu.dtim.dtim.ram.RAM[ShadowIndex - BaseIndex];
end
end
end
@ -626,14 +583,15 @@ task automatic updateProgramAddrLabelArray;
inout integer ProgramAddrLabelArray [string];
// Gets the memory location of begin_signature
integer ProgramLabelMapFP, ProgramAddrMapFP;
ProgramLabelMapFP = $fopen(ProgramLabelMapFile, "r");
ProgramAddrMapFP = $fopen(ProgramAddrMapFile, "r");
if (ProgramLabelMapFP & ProgramAddrMapFP) begin // check we found both files
// *** RT: I'm a bit confused by the required initialization here.
ProgramAddrLabelArray["begin_signature"] = 0;
ProgramAddrLabelArray["tohost"] = 0;
ProgramAddrLabelArray["sig_end_canary"] = 0;
while (!$feof(ProgramLabelMapFP)) begin
string label, adrstr;
integer returncode;
@ -642,6 +600,10 @@ task automatic updateProgramAddrLabelArray;
if (ProgramAddrLabelArray.exists(label)) ProgramAddrLabelArray[label] = adrstr.atohex();
end
end
if(ProgramAddrLabelArray["begin"] == 0) $display("Couldn't find begin_signature in %s", ProgramLabelMapFile);
if(ProgramAddrLabelArray["sig_end_canary"] == 0) $display("Couldn't find sig_end_canary in %s", ProgramLabelMapFile);
$fclose(ProgramLabelMapFP);
$fclose(ProgramAddrMapFP);
/* verilator lint_on WIDTHTRUNC */

4
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D/src/WALLY-fld-01.S
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@ -76,6 +76,10 @@ gpr_save:
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END
// ../../wally-riscv-arch-test/riscv-test-suite/rv32i_m/D/src/WALLY-fld.S
// David_Harris@hmc.edu & Katherine Parry

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-add-01.S
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@ -2997,5 +2997,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-addi-01.S
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@ -2887,5 +2887,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-and-01.S
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@ -3022,5 +3022,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-andi-01.S
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@ -2847,5 +2847,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-auipc-01.S
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@ -387,5 +387,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-beq-01.S
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@ -3027,5 +3027,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-bge-01.S
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@ -3012,5 +3012,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-bgeu-01.S
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@ -3717,5 +3717,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-blt-01.S
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@ -3007,5 +3007,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-bltu-01.S
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@ -3712,5 +3712,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-bne-01.S
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@ -3007,5 +3007,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-jal-01.S
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@ -152,5 +152,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-jalr-01.S
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@ -212,5 +212,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lb-align-01.S
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@ -162,5 +162,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lbu-align-01.S
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@ -162,5 +162,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lh-align-01.S
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@ -152,5 +152,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lhu-align-01.S
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@ -157,5 +157,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lui-01.S
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@ -387,5 +387,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lw-align-01.S
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@ -157,5 +157,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-or-01.S
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@ -3032,5 +3032,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-ori-01.S
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@ -2862,5 +2862,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sb-align-01.S
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@ -462,5 +462,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sh-align-01.S
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@ -432,5 +432,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sll-01.S
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@ -517,5 +517,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-slli-01.S
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@ -522,5 +522,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-slt-01.S
View File

@ -2987,5 +2987,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-slti-01.S
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@ -2887,5 +2887,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sltiu-01.S
View File

@ -3562,5 +3562,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sltu-01.S
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@ -3692,5 +3692,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sra-01.S
View File

@ -527,5 +527,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-srai-01.S
View File

@ -512,5 +512,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-srl-01.S
View File

@ -522,5 +522,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-srli-01.S
View File

@ -517,5 +517,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sub-01.S
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@ -3002,5 +3002,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sw-align-01.S
View File

@ -412,5 +412,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-xor-01.S
View File

@ -2997,5 +2997,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-xori-01.S
View File

@ -2877,5 +2877,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-ADD.S
View File

@ -132,6 +132,9 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END
// ../wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-ADD.S

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SLT.S
View File

@ -133,6 +133,9 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END
// ../wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SLT.S

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SLTU.S
View File

@ -133,6 +133,9 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END
// ../wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SLTU.S

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SUB.S
View File

@ -133,6 +133,9 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END
// ../wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SUB.S

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-XOR.S
View File

@ -133,6 +133,9 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END
// ../wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-XOR.S

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h
View File

@ -1428,6 +1428,9 @@ RVMODEL_DATA_BEGIN
test_1_res:
.fill 1024, 4, 0xdeadbeef
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END
#ifdef rvtest_mtrap_routine

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-cbom-01.S
View File

@ -468,5 +468,8 @@ Destination3:
signature:
.fill 16, 4, 0x0bad0bad
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

4
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-cboz-01.S
View File

@ -372,6 +372,8 @@ Destination2:
.fill 16, 4, 0xdeadbeef
signature:
.fill 16, 4, 0x0bad0bad
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-lrsc-01.S
View File

@ -113,4 +113,7 @@ RVMODEL_DATA_BEGIN
# signature output
wally_signature:
.fill 6, 4, -1
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-periph-01.S
View File

@ -917,4 +917,7 @@ RVMODEL_DATA_BEGIN
# signature output
wally_signature:
.fill 0x200, 8, 0x00000000
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-ADD.S
View File

@ -133,6 +133,9 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END
// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-ADD.S

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLT.S
View File

@ -133,6 +133,9 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END
// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLT.S

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLTU.S
View File

@ -133,6 +133,9 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END
// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLTU.S

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SUB.S
View File

@ -133,6 +133,9 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END
// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SUB.S

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-XOR.S
View File

@ -133,6 +133,9 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END
// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-XOR.S

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64ds-01.S
View File

@ -360,5 +360,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64ds-rwp1.S
View File

@ -385,5 +385,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64dsm-01.S
View File

@ -360,5 +360,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64dsm-rwp1.S
View File

@ -385,5 +385,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64es-01.S
View File

@ -360,5 +360,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64es-rwp1.S
View File

@ -385,5 +385,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64esm-01.S
View File

@ -360,5 +360,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64esm-rwp1.S
View File

@ -385,5 +385,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64im-01.S
View File

@ -1275,5 +1275,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64im-rwp1.S
View File

@ -965,5 +965,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64im-rwp2.S
View File

@ -300,5 +300,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64ks1i-01.S
View File

@ -505,5 +505,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64ks2-01.S
View File

@ -1180,5 +1180,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/andn-01.S
View File

@ -2707,5 +2707,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/clmul-01.S
View File

@ -2707,5 +2707,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/clmulh-01.S
View File

@ -2712,5 +2712,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/orn-01.S
View File

@ -2712,5 +2712,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/pack-01.S
View File

@ -2702,5 +2702,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/packh-01.S
View File

@ -2707,5 +2707,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/packu-01.S
View File

@ -2692,5 +2692,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/packuw-01.S
View File

@ -2707,5 +2707,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/packw-01.S
View File

@ -2707,5 +2707,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rev.b-01.S
View File

@ -2157,5 +2157,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rev8-01.S
View File

@ -2157,5 +2157,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rev8.w-01.S
View File

@ -2157,5 +2157,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rol-01.S
View File

@ -2712,5 +2712,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rolw-01.S
View File

@ -2707,5 +2707,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/ror-01.S
View File

@ -2707,5 +2707,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rori-01.S
View File

@ -1527,5 +1527,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/roriw-01.S
View File

@ -1512,5 +1512,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rorw-01.S
View File

@ -2707,5 +2707,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sig0-01.S
View File

@ -1275,5 +1275,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sig0-rwp1.S
View File

@ -965,5 +965,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sig0-rwp2.S
View File

@ -300,5 +300,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sig1-01.S
View File

@ -1275,5 +1275,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sig1-rwp1.S
View File

@ -965,5 +965,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sig1-rwp2.S
View File

@ -300,5 +300,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sum0-01.S
View File

@ -1275,5 +1275,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sum0-rwp1.S
View File

@ -965,5 +965,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sum0-rwp2.S
View File

@ -300,5 +300,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sum1-01.S
View File

@ -1275,5 +1275,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sum1-rwp1.S
View File

@ -965,5 +965,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sum1-rwp2.S
View File

@ -300,5 +300,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sig0-01.S
View File

@ -1275,5 +1275,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sig0-rwp1.S
View File

@ -965,5 +965,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sig0-rwp2.S
View File

@ -300,5 +300,8 @@ gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
.int 0x0
rvtest_sig_end:
RVMODEL_DATA_END

Some files were not shown because too many files have changed in this diff Show More