Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Cleanup.

Browse Source 
Verilator still has issues with riscassertions.sv and the testbench
This commit is contained in:
Rose Thompson 2023-12-18 16:38:56 -06:00
parent b7b245fe2f
commit 0f7b6ada04
1 changed files with 6 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
testbench/common/functionName.sv
View File

@ -30,8 +30,8 @@ module FunctionName import cvw::*; #(parameter cvw_t P) (
input string ProgramLabelMapFile
);
logic [P.XLEN-1:0] ProgramAddrMapMemory [longint];
string ProgramLabelMapMemory [longint];
logic [P.XLEN-1:0] ProgramAddrMapMemory [logic [P.XLEN-1:0]];
string ProgramLabelMapMemory [logic [P.XLEN-1:0]];
string FunctionName;
@ -62,7 +62,7 @@ module FunctionName import cvw::*; #(parameter cvw_t P) (
task automatic bin_search_min;
input logic [P.XLEN-1:0] pc;
input logic [P.XLEN-1:0] length;
ref logic [P.XLEN-1:0] array [longint];
ref logic [P.XLEN-1:0] array [logic [P.XLEN-1:0]];
output logic [P.XLEN-1:0] minval;
output logic [P.XLEN-1:0] mid;
@ -109,9 +109,9 @@ module FunctionName import cvw::*; #(parameter cvw_t P) (
endtask // bin_search_min
integer ProgramAddrMapFP, ProgramLabelMapFP;
longint ProgramAddrMapLineCount;
longint ProgramLabelMapLineCount;
longint ProgramAddrMapLine;
logic [P.XLEN-1:0] ProgramAddrMapLineCount;
logic [P.XLEN-1:0] ProgramLabelMapLineCount;
logic [P.XLEN-1:0] ProgramAddrMapLine;
string ProgramLabelMapLine;
integer status;