mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-02 17:55:19 +00:00
Added ZCA/ZCF/ZCD/ZCB support. Doesn't break regression, but not tested. Need to get tests for Zcb. Draft tests are in riscv-arch-test but not yet committed there
This commit is contained in:
David Harris
parent
19a6bbb01b
commit
28752303be
@ -158,6 +158,12 @@ localparam ZBB_SUPPORTED = 0;
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localparam ZBC_SUPPORTED = 0;
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localparam ZBS_SUPPORTED = 0;
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// New compressed instructions
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localparam ZCB_SUPPORTED = 1;
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localparam ZCA_SUPPORTED = 0;
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localparam ZCF_SUPPORTED = 0;
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localparam ZCD_SUPPORTED = 0;
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// Memory synthesis configuration
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localparam USE_SRAM = 0;
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@ -171,6 +171,12 @@ localparam ZBB_SUPPORTED = 1;
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localparam ZBC_SUPPORTED = 1;
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localparam ZBS_SUPPORTED = 1;
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// New compressed instructions
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localparam ZCB_SUPPORTED = 1;
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localparam ZCA_SUPPORTED = 0;
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localparam ZCF_SUPPORTED = 0;
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localparam ZCD_SUPPORTED = 0;
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// Memory synthesis configuration
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localparam USE_SRAM = 0;
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@ -159,6 +159,12 @@ localparam ZBB_SUPPORTED = 0;
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localparam ZBC_SUPPORTED = 0;
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localparam ZBS_SUPPORTED = 0;
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// New compressed instructions
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localparam ZCB_SUPPORTED = 0;
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localparam ZCA_SUPPORTED = 0;
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localparam ZCF_SUPPORTED = 0;
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localparam ZCD_SUPPORTED = 0;
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// Memory synthesis configuration
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localparam USE_SRAM = 0;
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@ -171,6 +171,12 @@ localparam ZBB_SUPPORTED = 1;
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localparam ZBC_SUPPORTED = 1;
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localparam ZBS_SUPPORTED = 1;
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// New compressed instructions
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localparam ZCB_SUPPORTED = 1;
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localparam ZCA_SUPPORTED = 0;
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localparam ZCF_SUPPORTED = 0;
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localparam ZCD_SUPPORTED = 0;
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// Memory synthesis configuration
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localparam USE_SRAM = 0;
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@ -159,6 +159,12 @@ localparam ZBB_SUPPORTED = 0;
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localparam ZBC_SUPPORTED = 0;
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localparam ZBS_SUPPORTED = 0;
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// New compressed instructions
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localparam ZCB_SUPPORTED = 0;
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localparam ZCA_SUPPORTED = 0;
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localparam ZCF_SUPPORTED = 0;
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localparam ZCD_SUPPORTED = 0;
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// Memory synthesis configuration
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localparam USE_SRAM = 0;
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@ -158,6 +158,12 @@ localparam ZBB_SUPPORTED = 0;
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localparam ZBC_SUPPORTED = 0;
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localparam ZBS_SUPPORTED = 0;
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// New compressed instructions
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localparam ZCB_SUPPORTED = 0;
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localparam ZCA_SUPPORTED = 0;
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localparam ZCF_SUPPORTED = 0;
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localparam ZCD_SUPPORTED = 0;
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// Memory synthesis configuration
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localparam USE_SRAM = 0;
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@ -161,6 +161,12 @@ localparam ZBB_SUPPORTED = 0;
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localparam ZBC_SUPPORTED = 0;
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localparam ZBS_SUPPORTED = 0;
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// New compressed instructions
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localparam ZCB_SUPPORTED = 0;
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localparam ZCA_SUPPORTED = 0;
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localparam ZCF_SUPPORTED = 0;
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localparam ZCD_SUPPORTED = 0;
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// Memory synthesis configuration
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localparam USE_SRAM = 0;
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@ -164,6 +164,12 @@ localparam ZBB_SUPPORTED = 1;
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localparam ZBC_SUPPORTED = 1;
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localparam ZBS_SUPPORTED = 1;
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// New compressed instructions
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localparam ZCB_SUPPORTED = 1;
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localparam ZCA_SUPPORTED = 0;
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localparam ZCF_SUPPORTED = 0;
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localparam ZCD_SUPPORTED = 0;
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// Memory synthesis configuration
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localparam USE_SRAM = 0;
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@ -161,6 +161,12 @@ localparam ZBB_SUPPORTED = 0;
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localparam ZBC_SUPPORTED = 0;
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localparam ZBS_SUPPORTED = 0;
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// New compressed instructions
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localparam ZCB_SUPPORTED = 0;
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localparam ZCA_SUPPORTED = 0;
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localparam ZCF_SUPPORTED = 0;
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localparam ZCD_SUPPORTED = 0;
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// Memory synthesis configuration
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localparam USE_SRAM = 0;
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@ -96,6 +96,10 @@ localparam cvw_t P = '{
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ZBB_SUPPORTED : ZBB_SUPPORTED,
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ZBC_SUPPORTED : ZBC_SUPPORTED,
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ZBS_SUPPORTED : ZBS_SUPPORTED,
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ZCA_SUPPORTED : ZCA_SUPPORTED,
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ZCB_SUPPORTED : ZCB_SUPPORTED,
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ZCD_SUPPORTED : ZCD_SUPPORTED,
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ZCF_SUPPORTED : ZCF_SUPPORTED,
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USE_SRAM : USE_SRAM,
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M_MODE : M_MODE,
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S_MODE : S_MODE,
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@ -161,6 +161,12 @@ typedef struct packed {
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logic ZBC_SUPPORTED;
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logic ZBS_SUPPORTED;
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// compressed
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logic ZCA_SUPPORTED;
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logic ZCB_SUPPORTED;
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logic ZCD_SUPPORTED;
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logic ZCF_SUPPORTED;
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// Memory synthesis configuration
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logic USE_SRAM;
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@ -30,7 +30,7 @@
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////////////////////////////////////////////////////////////////////////////////////////////////
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module decompress #(parameter XLEN)(
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module decompress import cvw::*; #(parameter cvw_t P) (
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input logic [31:0] InstrRawD, // 32-bit instruction or raw compressed 16-bit instruction in bottom half
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output logic [31:0] InstrD, // Decompressed instruction
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output logic IllegalCompInstrD // Invalid decompressed instruction
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@ -88,20 +88,60 @@ module decompress #(parameter XLEN)(
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IllegalCompInstrD = 1;
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InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
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end
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5'b00001: InstrD = {immCLD, rs1p, 3'b011, rdp, 7'b0000111}; // c.fld
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5'b00001: if (P.C_SUPPORTED & P.D_SUPPORTED | P.ZCD_SUPPORTED)
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InstrD = {immCLD, rs1p, 3'b011, rdp, 7'b0000111}; // c.fld
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else begin // unsupported instruction
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IllegalCompInstrD = 1;
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InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
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end
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5'b00010: InstrD = {immCL, rs1p, 3'b010, rdp, 7'b0000011}; // c.lw
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5'b00011: if (XLEN==32)
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InstrD = {immCL, rs1p, 3'b010, rdp, 7'b0000111}; // c.flw
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5'b00011: if (P.XLEN==32)
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if (P.C_SUPPORTED & P.F_SUPPORTED | P.ZCF_SUPPORTED)
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InstrD = {immCL, rs1p, 3'b010, rdp, 7'b0000111}; // c.flw
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else begin
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IllegalCompInstrD = 1;
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InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
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end
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else
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InstrD = {immCLD, rs1p, 3'b011, rdp, 7'b0000011}; // c.ld;
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5'b00101: InstrD = {immCSD[11:5], rs2p, rs1p, 3'b011, immCSD[4:0], 7'b0100111}; // c.fsd
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5'b00100: if (P.ZCB_SUPPORTED)
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if (instr16[12:10] == 3'b000)
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InstrD = {10'b0, instr16[6:5], rs1p, 3'b100, rdp, 7'b0000011}; // c.lbu
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else if (instr16[12:10] == 3'b001) begin
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if (instr16[6])
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InstrD = {10'b0, instr16[5], 1'b0, rs1p, 3'b001, rdp, 7'b0000011}; // c.lh
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else
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InstrD = {10'b0, instr16[5], 1'b0, rs1p, 3'b101, rdp, 7'b0000011}; // c.lhu
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end else if (instr16[12:10] == 3'b010)
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InstrD = {7'b0, rs2p, rs1p, 3'b000, 3'b000, instr16[6:5], 7'b0000011}; // c.sb
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else if (instr16[12:10] == 3'b011 & instr16[6] == 1'b0)
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InstrD = {7'b0, rs2p, rs1p, 3'b001, 3'b000, instr16[5], 1'b0, 7'b0000011}; // c.sh
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else begin
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IllegalCompInstrD = 1;
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InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
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end
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else begin
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IllegalCompInstrD = 1;
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InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
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end
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5'b00101: if (P.C_SUPPORTED & P.D_SUPPORTED | P.ZCD_SUPPORTED)
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InstrD = {immCSD[11:5], rs2p, rs1p, 3'b011, immCSD[4:0], 7'b0100111}; // c.fsd
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else begin // unsupported instruction
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IllegalCompInstrD = 1;
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InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
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end
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5'b00110: InstrD = {immCS[11:5], rs2p, rs1p, 3'b010, immCS[4:0], 7'b0100011}; // c.sw
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5'b00111: if (XLEN==32)
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InstrD = {immCS[11:5], rs2p, rs1p, 3'b010, immCS[4:0], 7'b0100111}; // c.fsw
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5'b00111: if (P.XLEN==32)
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if (P.C_SUPPORTED & P.F_SUPPORTED | P.ZCF_SUPPORTED)
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InstrD = {immCS[11:5], rs2p, rs1p, 3'b010, immCS[4:0], 7'b0100111}; // c.fsw
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else begin
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IllegalCompInstrD = 1;
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InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
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end
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else
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InstrD = {immCSD[11:5], rs2p, rs1p, 3'b011, immCSD[4:0], 7'b0100011}; //c.sd
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5'b01000: InstrD = {immCI, rds1, 3'b000, rds1, 7'b0010011}; // c.addi
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5'b01001: if (XLEN==32)
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5'b01001: if (P.XLEN==32)
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InstrD = {immCJ, 5'b00001, 7'b1101111}; // c.jal
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else
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InstrD = {immCI, rds1, 3'b000, rds1, 7'b0011011}; // c.addiw
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@ -125,33 +165,51 @@ module decompress #(parameter XLEN)(
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InstrD = {7'b0000000, rs2p, rds1p, 3'b110, rds1p, 7'b0110011}; // c.or
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else // if (instr16[6:5] == 2'b11)
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InstrD = {7'b0000000, rs2p, rds1p, 3'b111, rds1p, 7'b0110011}; // c.and
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else if (XLEN > 32) //if (instr16[12:10] == 3'b111) full truth table no need to check [12:10]
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if (instr16[6:5] == 2'b00)
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else if (instr16[12:10] == 3'b111) begin
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if (instr16[6:5] == 2'b00 & P.XLEN > 32)
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InstrD = {7'b0100000, rs2p, rds1p, 3'b000, rds1p, 7'b0111011}; // c.subw
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else if (instr16[6:5] == 2'b01)
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else if (instr16[6:5] == 2'b01 & P.XLEN > 32)
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InstrD = {7'b0000000, rs2p, rds1p, 3'b000, rds1p, 7'b0111011}; // c.addw
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else if (instr16[6:2] == 5'b11000 & P.ZCB_SUPPORTED)
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InstrD = {12'b000011111111, rds1p, 3'b111, rds1p, 7'b0010011}; // c.zext.b = andi rd, rs1, 255
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else if (instr16[6:2] == 5'b10101 & P.ZCB_SUPPORTED)
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InstrD = {12'b011000000100, rds1p, 3'b001, rds1p, 7'b0010011}; // c.sext.b
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else if (instr16[6:2] == 5'b11010 & P.ZCB_SUPPORTED)
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InstrD = {7'b0000100, 5'b00000, rds1p, 3'b100, rds1p, 3'b011, P.XLEN > 32, 3'b011}; // c.zext.h
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else if (instr16[6:2] == 5'b11011 & P.ZCB_SUPPORTED)
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InstrD = {12'b011000000101, rds1p, 3'b001, rds1p, 7'b0010011}; // c.sext.h
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else if (instr16[6:2] == 5'b11101 & P.ZCB_SUPPORTED)
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InstrD = {12'b111111111111, rds1p, 3'b100, rds1p, 7'b0010011}; // c.not = xori
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else if (instr16[6:2] == 5'b11100 & P.ZCB_SUPPORTED & P.XLEN > 32)
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InstrD = {7'b0000100, 5'b00000, rds1p, 3'b000, rds1p, 7'b0111011}; // c.zext.w = add.uw rd, rs1, 0
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else if (instr16[6:5] == 2'b10 & P.ZCB_SUPPORTED)
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InstrD = {7'b0000001, rs2p, rds1p, 3'b000, rds1p, 7'b0110011}; // c.mul
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else begin // reserved
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IllegalCompInstrD = 1;
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InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
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end
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// coverage off
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// are excluding this branch from coverage because in rv64gc XLEN is always 64 and thus greater than 32 bits
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// This branch will only be taken if instr16[12:10] == 3'b111 and 'XLEN !> 32, because all other
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// possible values for instr16[12:10] are covered by branches above. XLEN !> 32
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// will never occur in rv64gc so this branch can not be covered
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else begin // illegal instruction
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end else begin // illegal instruction
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IllegalCompInstrD = 1;
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InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
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end
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// coverage on
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5'b01101: InstrD = {immCJ, 5'b00000, 7'b1101111}; // c.j
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5'b01110: InstrD = {immCB[11:5], 5'b00000, rs1p, 3'b000, immCB[4:0], 7'b1100011}; // c.beqz
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5'b01111: InstrD = {immCB[11:5], 5'b00000, rs1p, 3'b001, immCB[4:0], 7'b1100011}; // c.bnez
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5'b10000: InstrD = {6'b000000, immSH, rds1, 3'b001, rds1, 7'b0010011}; // c.slli
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5'b10001: InstrD = {immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000111}; // c.fldsp
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5'b10001: if (P.C_SUPPORTED & P.D_SUPPORTED | P.ZCD_SUPPORTED)
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InstrD = {immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000111}; // c.fldsp
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else begin // unsupported instruction
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IllegalCompInstrD = 1;
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InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
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end
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5'b10010: InstrD = {immCILSP, 5'b00010, 3'b010, rds1, 7'b0000011}; // c.lwsp
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5'b10011: if (XLEN == 32)
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InstrD = {immCILSP, 5'b00010, 3'b010, rds1, 7'b0000111}; // c.flwsp
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5'b10011: if (P.XLEN == 32)
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if (P.C_SUPPORTED & P.F_SUPPORTED | P.ZCF_SUPPORTED)
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InstrD = {immCILSP, 5'b00010, 3'b010, rds1, 7'b0000111}; // c.flwsp
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else begin
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IllegalCompInstrD = 1;
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InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
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end
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else
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InstrD = {immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000011}; // c.ldsp
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5'b10100: if (instr16[12] == 0)
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@ -167,10 +225,20 @@ module decompress #(parameter XLEN)(
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InstrD = {12'b0, rds1, 3'b000, 5'b00001, 7'b1100111}; // c.jalr
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else
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InstrD = {7'b0000000, rs2, rds1, 3'b000, rds1, 7'b0110011}; // c.add
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5'b10101: InstrD = {immCSSD[11:5], rs2, 5'b00010, 3'b011, immCSSD[4:0], 7'b0100111}; // c.fsdsp
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5'b10101: if (P.C_SUPPORTED & P.D_SUPPORTED | P.ZCD_SUPPORTED)
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InstrD = {immCSSD[11:5], rs2, 5'b00010, 3'b011, immCSSD[4:0], 7'b0100111}; // c.fsdsp
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else begin // unsupported instruction
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IllegalCompInstrD = 1;
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InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
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end
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5'b10110: InstrD = {immCSS[11:5], rs2, 5'b00010, 3'b010, immCSS[4:0], 7'b0100011}; // c.swsp
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5'b10111: if (XLEN==32)
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InstrD = {immCSS[11:5], rs2, 5'b00010, 3'b010, immCSS[4:0], 7'b0100111}; // c.fswsp
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5'b10111: if (P.XLEN==32)
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if (P.C_SUPPORTED & P.F_SUPPORTED | P.ZCF_SUPPORTED)
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InstrD = {immCSS[11:5], rs2, 5'b00010, 3'b010, immCSS[4:0], 7'b0100111}; // c.fswsp
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else begin
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IllegalCompInstrD = 1;
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InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
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end
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else
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InstrD = {immCSSD[11:5], rs2, 5'b00010, 3'b011, immCSSD[4:0], 7'b0100011}; // c.sdsp
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default: begin // illegal instruction
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@ -353,9 +353,9 @@ module ifu import cvw::*; #(parameter cvw_t P) (
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flopenrc #(P.XLEN) PCDReg(clk, reset, FlushD, ~StallD, PCF, PCD);
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// expand 16-bit compressed instructions to 32 bits
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if (P.C_SUPPORTED) begin
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if (P.C_SUPPORTED | P.ZCA_SUPPORTED) begin
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logic IllegalCompInstrD;
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decompress #(P.XLEN) decomp(.InstrRawD, .InstrD, .IllegalCompInstrD);
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decompress #(P) decomp(.InstrRawD, .InstrD, .IllegalCompInstrD);
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assign IllegalIEUInstrD = IllegalBaseInstrD | IllegalCompInstrD; // illegal if bad 32 or 16-bit instr
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end else begin
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assign InstrD = InstrRawD;
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@ -63,6 +63,11 @@ module riscvassertions import cvw::*; #(parameter cvw_t P);
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assert ((P.ZICBOP_SUPPORTED == 0) || (P.DCACHE_SUPPORTED == 1)) else $error("ZICBOP requires DCACHE_SUPPORTED");
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assert ((P.SVPBMT_SUPPORTED == 0) || (P.VIRTMEM_SUPPORTED == 1 && P.XLEN==64)) else $error("SVPBMT requires VIRTMEM_SUPPORTED and RV64");
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assert ((P.SVNAPOT_SUPPORTED == 0) || (P.VIRTMEM_SUPPORTED == 1 && P.XLEN==64)) else $error("SVNAPOT requires VIRTMEM_SUPPORTED and RV64");
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assert ((P.ZCB_SUPPORTED == 0) || (P.M_SUPPORTED == 1 && (P.ZBA_SUPPORTED == 1 || P.XLEN == 32) && P.ZBB_SUPPORTED == 1)) else $error("ZCB requires M and ZBB (and also ZBA for RV64)");
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assert ((P.C_SUPPORTED == 0) || (P.ZCA_SUPPORTED == 0 && P.ZCF_SUPPORTED == 0 && P.ZCD_SUPPORTED == 0)) else $error("C and ZCA/ZCD/ZCF cannot simultaneously be supported");
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assert ((P.ZCA_SUPPORTED == 1) || (P.ZCD_SUPPORTED == 0 && P.ZCF_SUPPORTED == 0)) else $error("ZCF or ZCD requires ZCA");
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assert ((P.ZCF_SUPPORTED == 0) || (P.F_SUPPORTED == 1)) else $error("ZCF requires F");
|
||||
assert ((P.ZCD_SUPPORTED == 0) || (P.D_SUPPORTED == 1)) else $error("ZCD requires D");
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
Loading…
Reference in New Issue
Block a user