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https://github.com/openhwgroup/cvw
synced 2025-01-23 13:04:28 +00:00
Merge pull request #619 from ross144/main
Merged all regression tests except imperas linux boot into testbench.sv.
This commit is contained in:
David Harris
GitHub
commit
d71efedab5
@ -154,22 +154,11 @@ localparam PLIC_SPI_ID = 32'd6;
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localparam PLIC_SDC_ID = 32'd9;
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localparam BPRED_SUPPORTED = 1;
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// this is an annoying hack for the branch predictor parameterization override.
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`ifdef BPRED_OVERRIDE
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localparam BPRED_TYPE = `BPRED_TYPE;
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localparam BPRED_SIZE = `BPRED_SIZE;
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`else
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localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
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localparam BPRED_SIZE = 32'd10;
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`endif
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localparam BPRED_NUM_LHR = 32'd6;
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`ifdef BTB_OVERRIDE
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localparam BTB_SIZE = `BTB_SIZE;
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localparam RAS_SIZE = `RAS_SIZE;
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`else
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localparam BTB_SIZE = 32'd10;
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localparam RAS_SIZE = 32'd16;
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`endif
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localparam INSTR_CLASS_PRED = 1;
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localparam SVADU_SUPPORTED = 1;
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@ -72,7 +72,7 @@ def getBuildrootTC(boot):
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BRcmd="vsim > {} -c <<!\ndo wally-batch.do buildroot buildroot $RISCV "+str(INSTR_LIMIT)+" 1 0 -coverage\n!"
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else:
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print( "buildroot no coverage")
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BRcmd="vsim > {} -c <<!\ndo wally-batch.do buildroot buildroot $RISCV "+str(INSTR_LIMIT)+" 1 0\n!"
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BRcmd="vsim > {} -c <<!\ndo wally-batch.do buildroot configOptions buildroot -GINSTR_LIMIT=" +str(INSTR_LIMIT) + " \n!"
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BRgrepstr=str(INSTR_LIMIT)+" instructions"
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return TestCase(name,variant="rv64gc",cmd=BRcmd,grepstr=BRgrepstr)
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@ -51,43 +51,15 @@ if {$argc >= 3} {
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# default to config/rv64ic, but allow this to be overridden at the command line. For example:
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# do wally-pipelined-batch.do ../config/rv32imc rv32imc
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if {$2 eq "buildroot"} {
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vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/deriv/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
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# start and run simulation
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if { $coverage } {
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echo "wally-batch buildroot coverage"
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vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -o testbenchopt +cover=sbecf
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vsim -lib wkdir/work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3691,13286 -fatal 7 -cover
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} else {
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vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -o testbenchopt
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vsim -lib wkdir/work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3691,13286 -fatal 7
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}
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run -all
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run -all
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exec ./slack-notifier/slack-notifier.py
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} elseif {$2 eq "buildroot-no-trace"} {
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vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/deriv/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
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# start and run simulation
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vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G NO_SPOOFING=1 -o testbenchopt
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vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829,13286 -fatal 7
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#-- Run the Simulation
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echo "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!"
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echo "Don't forget to change DEBUG_LEVEL = 0."
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echo "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!"
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run -all
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run -all
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exec ./slack-notifier/slack-notifier.py
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} elseif {$2 eq "configOptions"} {
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if {$2 eq "configOptions"} {
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# set arguments " "
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# for {set i 5} {$i <= $argc} {incr i} {
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# append arguments "\$$i "
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# }
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# puts $arguments
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# set options eval $arguments
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# **** fix this so we can pass any number of +defines.
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# only allows 3 right now
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# **** fix this so we can pass any number of +defines or top level params.
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# only allows 1 right now
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vlog -lint -work wkdir/work_${1}_${3}_${4} +incdir+../config/$1 +incdir+../config/deriv/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286
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# start and run simulation
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@ -40,7 +40,9 @@ module testbench;
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parameter BPRED_LOGGER=0;
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parameter I_CACHE_ADDR_LOGGER=0;
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parameter D_CACHE_ADDR_LOGGER=0;
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parameter RISCV_DIR = "/opt/riscv";
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parameter INSTR_LIMIT = 0;
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`include "parameter-defs.vh"
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logic clk;
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@ -134,6 +136,7 @@ module testbench;
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"arch64zfh_divsqrt": if (P.ZFH_SUPPORTED) tests = arch64zfh_divsqrt;
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"arch64zfaf": if (P.ZFA_SUPPORTED) tests = arch64zfaf;
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"arch64zfad": if (P.ZFA_SUPPORTED & P.D_SUPPORTED) tests = arch64zfad;
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"buildroot": tests = buildroot;
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endcase
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end else begin // RV32
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case (TEST)
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@ -210,7 +213,7 @@ module testbench;
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logic ResetCntRst;
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logic CopyRAM;
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string signame, memfilename, pathname;
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string signame, memfilename, bootmemfilename, pathname;
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integer begin_signature_addr, end_signature_addr, signature_size;
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assign ResetThreshold = 3'd5;
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@ -279,10 +282,17 @@ module testbench;
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always @(posedge clk) begin
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if(SelectTest) begin
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if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"};
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else if(TEST == "buildroot") begin
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memfilename = {RISCV_DIR, "/linux-testvectors/ram.bin"};
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bootmemfilename = {RISCV_DIR, "/linux-testvectors/bootmem.bin"};
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end
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else memfilename = {pathname, tests[test], ".elf.memfile"};
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if (riscofTest) begin
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ProgramAddrMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.addr"};
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ProgramLabelMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.lab"};
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end else if (TEST == "buildroot") begin
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ProgramAddrMapFile = {RISCV_DIR, "/buildroot/output/images/disassembly/vmlinux.objdump.addr"};
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ProgramLabelMapFile = {RISCV_DIR, "/buildroot/output/images/disassembly/vmlinux.objdump.lab"};
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end else begin
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ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"};
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ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};
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@ -352,6 +362,8 @@ module testbench;
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integer StartIndex;
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integer EndIndex;
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integer BaseIndex;
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integer memFile;
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integer readResult;
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if (P.SDC_SUPPORTED) begin
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always @(posedge clk) begin
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if (LoadMem) begin
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@ -373,7 +385,16 @@ module testbench;
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end else if (P.BUS_SUPPORTED) begin : bus_supported
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always @(posedge clk) begin
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if (LoadMem) begin
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$readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
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if (TEST == "buildroot") begin
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memFile = $fopen(bootmemfilename, "rb");
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readResult = $fread(dut.uncore.uncore.bootrom.bootrom.memory.ROM, memFile);
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$fclose(memFile);
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memFile = $fopen(memfilename, "rb");
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readResult = $fread(dut.uncore.uncore.ram.ram.memory.RAM, memFile);
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$fclose(memFile);
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end else
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$readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
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if (TEST == "embench") $display("Read memfile %s", memfilename);
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end
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if (CopyRAM) begin
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LogXLEN = (1 + P.XLEN/32); // 2 for rv32 and 3 for rv64
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@ -519,6 +540,15 @@ module testbench;
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DCacheFlushFSM #(P) DCacheFlushFSM(.clk(clk), .reset(reset), .start(DCacheFlushStart), .done(DCacheFlushDone));
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if(P.ZICSR_SUPPORTED) begin
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logic [P.XLEN-1:0] Minstret;
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assign Minstret = testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2];
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always @(negedge clk) begin
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if((Minstret != 0) && (Minstret % 'd100000 == 0)) $display("Reached %d instructions, %d", Minstret, INSTR_LIMIT);
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if((Minstret == INSTR_LIMIT) & (INSTR_LIMIT!=0)) begin $stop; $stop; end
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end
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end
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task automatic CheckSignature;
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// This task must be declared inside this module as it needs access to parameter P. There is
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// no way to pass P to the task unless we convert it to a module.
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@ -31,6 +31,7 @@
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`define EMBENCH "4"
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`define CUSTOM "5"
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`define COVERAGE "6"
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`define BUILDROOT "7"
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string tvpaths[] = '{
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"$RISCV/imperas-riscv-tests/work/",
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@ -71,6 +72,11 @@ string tvpaths[] = '{
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"pmpadrdecs"
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};
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string buildroot[] = '{
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`BUILDROOT,
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"buildroot"
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};
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string coremark[] = '{
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`COREMARK,
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"coremark.bare.riscv"
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