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Cleaned up indentation in testbench-fp
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David Harris
parent
da4eca4854
commit
0d56a281b9
@ -882,7 +882,7 @@ module testbenchfp;
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// - the sign of the NaN does not matter for the opperations being tested
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// - when 2 or more NaNs are inputed the NaN that is propigated doesn't matter
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if (UnitVal !== `CVTFPUNIT & UnitVal !== `CVTINTUNIT)
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case (FmtVal)
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case (FmtVal)
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2'b11: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res === {1'b0, {P.Q_NE+1{1'b1}}, {P.Q_NF-1{1'b0}}})) |
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(AnsFlg[4]&(Res[P.Q_LEN-2:0] === {{P.Q_NE+1{1'b1}}, {P.Q_NF-1{1'b0}}})) |
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(XNaN&(Res[P.Q_LEN-2:0] === {X[P.Q_LEN-2:P.Q_NF],1'b1,X[P.Q_NF-2:0]})) |
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@ -903,9 +903,9 @@ module testbenchfp;
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(XNaN&(Res[P.H_LEN-2:0] === {X[P.H_LEN-2:P.H_NF],1'b1,X[P.H_NF-2:0]})) |
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(YNaN&(Res[P.H_LEN-2:0] === {Y[P.H_LEN-2:P.H_NF],1'b1,Y[P.H_NF-2:0]})) |
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(ZNaN&(Res[P.H_LEN-2:0] === {Z[P.H_LEN-2:P.H_NF],1'b1,Z[P.H_NF-2:0]})));
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endcase
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else if (UnitVal === `CVTFPUNIT) // if converting from floating point to floating point OpCtrl contains the final FP format
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case (OpCtrlVal[1:0])
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endcase
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else if (UnitVal === `CVTFPUNIT) // if converting from floating point to floating point OpCtrl contains the final FP format
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case (OpCtrlVal[1:0])
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2'b11: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res === {1'b0, {P.Q_NE+1{1'b1}}, {P.Q_NF-1{1'b0}}})) |
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(AnsFlg[4]&(Res[P.Q_LEN-2:0] === {{P.Q_NE+1{1'b1}}, {P.Q_NF-1{1'b0}}})) |
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(AnsNaN&(Res[P.Q_LEN-2:0] === Ans[P.Q_LEN-2:0])) |
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@ -926,72 +926,70 @@ module testbenchfp;
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(AnsNaN&(Res[P.H_LEN-2:0] === Ans[P.H_LEN-2:0])) |
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(XNaN&(Res[P.H_LEN-2:0] === {X[P.H_LEN-2:P.H_NF],1'b1,X[P.H_NF-2:0]})) |
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(YNaN&(Res[P.H_LEN-2:0] === {Y[P.H_LEN-2:P.H_NF],1'b1,Y[P.H_NF-2:0]})));
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endcase
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else NaNGood = 1'b0; // integers can't be NaNs
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endcase
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else NaNGood = 1'b0; // integers can't be NaNs
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///////////////////////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////////////////////
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// ||||||| ||| ||| ||||||| ||||||| ||| |||
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// ||| ||| ||| ||| ||| ||| |||
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// ||| |||||||||| ||||||| ||| ||||||
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// ||| ||| ||| ||| ||| ||| |||
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// ||||||| ||| ||| ||||||| ||||||| ||| |||
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// ||||||| ||| ||| ||||||| ||||||| ||| |||
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// ||| ||| ||| ||| ||| ||| |||
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// ||| |||||||||| ||||||| ||| ||||||
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// ||| ||| ||| ||| ||| ||| |||
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// ||||||| ||| ||| ||||||| ||||||| ||| |||
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///////////////////////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////////////////////
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// check if result is correct
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// wait till the division result is done or one extra cylcle for early termination (to simulate the EM pipline stage)
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assign ResMatch = ((Res === Ans) | NaNGood | (NaNGood === 1'bx));
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assign FlagMatch = ((ResFlg === AnsFlg) | (AnsFlg === 5'bx));
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assign divsqrtop = (OpCtrlVal == `SQRT_OPCTRL) | (OpCtrlVal == `DIV_OPCTRL);
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assign FMAop = (OpCtrlVal == `FMAUNIT);
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assign DivDone = OldFDivBusyE & ~FDivBusyE;
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// check if result is correct
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// wait till the division result is done or one extra cylcle for early termination (to simulate the EM pipline stage)
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assign ResMatch = ((Res === Ans) | NaNGood | (NaNGood === 1'bx));
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assign FlagMatch = ((ResFlg === AnsFlg) | (AnsFlg === 5'bx));
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assign divsqrtop = (OpCtrlVal == `SQRT_OPCTRL) | (OpCtrlVal == `DIV_OPCTRL);
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assign FMAop = (OpCtrlVal == `FMAUNIT);
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assign DivDone = OldFDivBusyE & ~FDivBusyE;
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// Maybe change OpCtrl but for now just look at TEST for fma test
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assign CheckNow = ((DivDone | ~divsqrtop) | (TEST == "add" | TEST == "fma" | TEST == "sub")) & (UnitVal !== `CVTINTUNIT) & (UnitVal !== `CMPUNIT);
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if (~(ResMatch & FlagMatch) & CheckNow) begin
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// Maybe change OpCtrl but for now just look at TEST for fma test
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assign CheckNow = ((DivDone | ~divsqrtop) | (TEST == "add" | TEST == "fma" | TEST == "sub")) & (UnitVal !== `CVTINTUNIT) & (UnitVal !== `CMPUNIT);
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if (~(ResMatch & FlagMatch) & CheckNow) begin
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errors += 1;
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$display("\nError in %s", Tests[TestNum]);
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$display("TestNum %d OpCtrl %d", TestNum, OpCtrl[TestNum]);
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$display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Expected: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg);
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$stop;
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end else if (((UnitVal === `CVTINTUNIT) | (UnitVal === `CMPUNIT)) &
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~(ResMatch & FlagMatch) & (Ans[0] !== 1'bx)) begin // Check for conversion and comparisons
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errors += 1;
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$display("\nError in %s", Tests[TestNum]);
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$display("TestNum %d OpCtrl %d", TestNum, OpCtrl[TestNum]);
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$display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Expected: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg);
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$display("TestNum %d OpCtrl %d", TestNum, OpCtrl[TestNum]);
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$display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Ans: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg);
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$stop;
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end else if (((UnitVal === `CVTINTUNIT) | (UnitVal === `CMPUNIT)) &
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~(ResMatch & FlagMatch) & (Ans[0] !== 1'bx)) begin // Check for conversion and comparisons
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errors += 1;
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$display("\nError in %s", Tests[TestNum]);
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$display("TestNum %d OpCtrl %d", TestNum, OpCtrl[TestNum]);
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$display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Ans: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg);
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$stop;
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end
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end
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if (TestVectors[VectorNum][0] === 1'bx & Tests[TestNum] !== "") begin // if reached the eof
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// increment the test
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TestNum += 1;
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// clear the vectors
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for(int i=0; i<6133248; i++) TestVectors[i] = {P.FLEN*4+8{1'bx}};
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// read next files
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$readmemh({`PATH, Tests[TestNum]}, TestVectors);
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// set the vector index back to 0
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VectorNum = 0;
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// incemet the operation if all the rounding modes have been tested
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if (FrmNum === 4) OpCtrlNum += 1;
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// increment the rounding mode or loop back to rne
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if (FrmNum < 4)
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FrmNum += 1;
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else begin
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FrmNum = 0;
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// Add some time as a buffer between tests at the end of each test
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repeat (10)
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@(posedge clk);
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end
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// if no more Tests - finish
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if (Tests[TestNum] === "") begin
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$display("\nAll Tests completed with %d errors\n", errors);
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$stop;
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end
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$display("Running %s vectors", Tests[TestNum]);
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// increment the test
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TestNum += 1;
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// clear the vectors
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for(int i=0; i<6133248; i++) TestVectors[i] = {P.FLEN*4+8{1'bx}};
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// read next files
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$readmemh({`PATH, Tests[TestNum]}, TestVectors);
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// set the vector index back to 0
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VectorNum = 0;
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// incemet the operation if all the rounding modes have been tested
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if (FrmNum === 4) OpCtrlNum += 1;
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// increment the rounding mode or loop back to rne
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if (FrmNum < 4) FrmNum += 1;
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else begin
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FrmNum = 0;
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// Add some time as a buffer between tests at the end of each test
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repeat (10)
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@(posedge clk);
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end
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// if no more Tests - finish
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if (Tests[TestNum] === "") begin
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$display("\nAll Tests completed with %d errors\n", errors);
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$stop;
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end
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$display("Running %s vectors", Tests[TestNum]);
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end
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end
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endmodule
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