Merge branch 'main' of https://github.com/openhwgroup/cvw

examples/verilog/fulladder/fulladder-batch-coverage.do

@@ -0,0 +1,8 @@
+# fulladder-batch-coverage.do 
+# David_Harris@hmc.edu 22 May 2023
+vlog fulladder.sv 
+vopt +acc work.testbench -o workopt +cover=sbecf
+vsim workopt -coverage
+run -all
+coverage save -instance /testbench/dut fulladder.ucdb
+quit

sim/regression-wally

@@ -136,11 +136,9 @@ tests64gc = ["arch64f", "arch64d", "arch64f_fma", "arch64d_fma", "arch64i", "arc
              "arch64priv", "arch64c",  "arch64m", "arch64zi", "wally64a", "wally64periph", "wally64priv"] 
 if (coverage):  # delete all but 64gc tests when running coverage
     configs = []
-#    tests64gc = ["coverage64gc", "arch64f", "arch64d", "arch64i", "arch64priv", "arch64c",  "arch64m", 
     tests64gc = ["coverage64gc", "arch64i", "arch64priv", "arch64c",  "arch64m", 
                  "arch64zi", "wally64a", "wally64periph", "wally64priv", 
-                 "arch64zba",  "arch64zbb",  "arch64zbc",  "arch64zbs", 
-                 "imperas64f", "imperas64d", "imperas64c", "imperas64i"] 
+                 "arch64zba",  "arch64zbb",  "arch64zbc",  "arch64zbs"]
     if (fp):
        tests64gc.append("arch64f")
        tests64gc.append("arch64d")

sim/verilate

@@ -0,0 +1,22 @@
+#!/bin/bash
+# simulate with Verilator
+
+export PATH=$PATH:/usr/local/bin/
+verilator=`which verilator`
+
+basepath=$(dirname $0)/..
+#for config in rv32e rv64gc rv32gc rv32imc rv32i rv64i rv64fpquad; do
+for config in  rv64gc; do
+    echo "$config linting..."
+    if !($verilator --cc "$@" --top-module testbench "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/testbench/testbench.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then
+        echo "Exiting after $config lint due to errors or warnings"
+        exit 1
+    fi
+done
+echo "All lints run with no errors or warnings"
+
+# --lint-only just runs lint rather than trying to compile and simulate
+# -I points to the include directory where files such as `include wally-config.vh  are found
+
+# For more exhaustive (and sometimes spurious) warnings, add --Wall to the Verilator command
+# Unfortunately, this produces a bunch of UNUSED and UNDRIVEN signal warnings in blocks that are configured to not exist.

testbench/testbench.sv

@@ -256,7 +256,7 @@ module testbench;
         $readmemh(romfilename, dut.uncore.uncore.bootrom.bootrom.memory.ROM);
         $readmemh(sdcfilename, sdcard.sdcard.FLASHmem);
         // force sdc timers
-        force dut.uncore.uncore.sdc.SDC.LimitTimers = 1;
+        dut.uncore.uncore.sdc.SDC.LimitTimers = 1;
       end else begin
         if (`IROM_SUPPORTED)     $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
         else if (`BUS_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
@@ -324,10 +324,10 @@ module testbench;
             $display("Embench Benchmark: %s is done.", tests[test]);
             if (riscofTest) outputfile = {pathname, tests[test], "/ref/ref.sim.output"};
             else outputfile = {pathname, tests[test], ".sim.output"};
-            outputFilePointer = $fopen(outputfile);
+            outputFilePointer = $fopen(outputfile, "w");
             i = 0;
             while ($unsigned(i) < $unsigned(5'd5)) begin
-              $fdisplayh(outputFilePointer, DCacheFlushFSM.ShadowRAM[testadr+i]);
+              $fdisplay("%x %s", outputFilePointer, DCacheFlushFSM.ShadowRAM[testadr+i]);
               i = i + 1;
             end
             $fclose(outputFilePointer);
@@ -545,11 +545,7 @@ module testbench;
       always @(*) begin
         if(reset) begin
           for(adrindex = 0; adrindex < 2**`BPRED_NUM_LHR; adrindex++) begin
-            force dut.core.ifu.bpred.bpred.Predictor.DirPredictor.BHT.mem[adrindex] = 0;
-          end
-            #1;
-          for(adrindex = 0; adrindex < 2**`BPRED_NUM_LHR; adrindex++) begin
-            release dut.core.ifu.bpred.bpred.Predictor.DirPredictor.BHT.mem[adrindex];
+            dut.core.ifu.bpred.bpred.Predictor.DirPredictor.BHT.mem[adrindex] = 0;
           end
         end
       end
@@ -561,14 +557,7 @@ module testbench;
           force dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0;
         end
         for(adrindex = 0; adrindex < 2**`BPRED_SIZE; adrindex++) begin
-          force dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0;
-        end
-          #1;
-        for(adrindex = 0; adrindex < 2**`BTB_SIZE; adrindex++) begin
-          release dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex];
-        end 
-        for(adrindex = 0; adrindex < 2**`BPRED_SIZE; adrindex++) begin
-          release dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex];
+          dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0;
         end
       end
     end
@@ -593,7 +582,7 @@ module testbench;
     assign InvalEdge = dut.core.ifu.InvalidateICacheM & ~InvalDelayed;
 
     initial begin
-      LogFile = $psprintf("ICache.log");
+      LogFile = "ICache.log";
       file = $fopen(LogFile, "w");
       $fwrite(file, "BEGIN %s\n", memfilename);
     end
@@ -636,7 +625,7 @@ module testbench;
                      (AccessTypeString != "NULL");
 
     initial begin
-      LogFile = $psprintf("DCache.log");
+      LogFile = "DCache.log";
       file = $fopen(LogFile, "w");
       $fwrite(file, "BEGIN %s\n", memfilename);
     end
@@ -662,7 +651,8 @@ module testbench;
       flop #(1) ResetDReg(clk, reset, resetD);
       assign resetEdge = ~reset & resetD;
       initial begin
-        LogFile = $psprintf("branch_%s%0d.log", `BPRED_TYPE, `BPRED_SIZE);
+        LogFile = "branch.log"; // will break some of Ross's research analysis scripts
+        //LogFile = $psprintf("branch_%s%0d.log", `BPRED_TYPE, `BPRED_SIZE);
         file = $fopen(LogFile, "w");
       end
       always @(posedge clk) begin
@@ -761,8 +751,7 @@ module DCacheFlushFSM
     integer i, j, k, l;
 
     always @(posedge clk) begin
-      if (start) begin #1
-        #1
+      if (start) begin 
         for(i = 0; i < numlines; i++) begin
           for(j = 0; j < numways; j++) begin
             for(l = 0; l < cachesramwords; l++) begin

tests/riscof/sail_cSim/riscof_sail_cSim.py

@@ -130,4 +130,5 @@ class sail_cSim(pluginTemplate):
             make.add_target(execute)
 #        make.execute_all(self.work_dir)
 # DH 7/26/22 increase timeout so sim will finish on slow machines
-        make.execute_all(self.work_dir, timeout = 1800)
+# DH 5/17/23 increase timeout to 3600 seconds
+        make.execute_all(self.work_dir, timeout = 3600)

tests/riscof/spike/riscof_spike.py

@@ -191,7 +191,8 @@ class spike(pluginTemplate):
       # parallel using the make command set above.
       #make.execute_all(self.work_dir)
       # DH 7/26/22 increase timeout to 1800 seconds so sim will finish on slow machines
-      make.execute_all(self.work_dir, timeout = 1800) 
+      # DH 5/17/23 increase timeout to 3600 seconds
+      make.execute_all(self.work_dir, timeout = 3600) 
 
 
       # if target runs are not required then we simply exit as this point after running all