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Merge pull request #481 from ross144/main

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Fixed the BTB logger so sim_bp correctly reports BTB performance
This commit is contained in:
David Harris 2023-11-15 17:45:38 -08:00 committed by GitHub
commit 94201e993f
9 changed files with 80 additions and 43 deletions
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2
bin/CModelBTBAccuracy.sh
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@ -52,6 +52,6 @@ do
# with such long precision bc outputs onto multiple lines
# must remove \n and \ from string
Product=`echo "$Product" | tr -d '\n' | tr -d '\\\'`
GeoMean=`perl -E "say $Product**(1/$Count)"`
GeoMean=`perl -E "say $Product**(1/$Count) * 100"`
echo "$Pred$Size $GeoMean"
done

5
bin/SeparateBranch.sh
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@ -43,7 +43,8 @@ TrainLineNumberArray=($TrainLineNumbers)
BeginLineNumberArray=($BeginLineNumbers)
EndLineNumberArray=($EndLineNumbers)
mkdir -p branch
OutputPath=${File%%.*}
mkdir -p $OutputPath
Length=${#EndLineNumberArray[@]}
for i in $(seq 0 1 $((Length-1)))
do
@ -51,5 +52,5 @@ do
CurrTrain=$((${TrainLineNumberArray[$i]}+1))
CurrEnd=$((${EndLineNumberArray[$i]}-1))
echo $CurrName, $CurrTrain, $CurrEnd
sed -n "${CurrTrain},${CurrEnd}p" $File > branch/${CurrName}_branch.log
sed -n "${CurrTrain},${CurrEnd}p" $File > $OutputPath/${CurrName}_${File}
done

7
bin/parseHPMC.py
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@ -32,10 +32,12 @@ import math
import numpy as np
import argparse
RefData = [('twobitCModel6', 'twobitCModel', 64, 9.65280765420711), ('twobitCModel8', 'twobitCModel', 256, 8.75120245829945), ('twobitCModel10', 'twobitCModel', 1024, 8.1318382397263),
RefDataBP = [('twobitCModel6', 'twobitCModel', 64, 9.65280765420711), ('twobitCModel8', 'twobitCModel', 256, 8.75120245829945), ('twobitCModel10', 'twobitCModel', 1024, 8.1318382397263),
('twobitCModel12', 'twobitCModel', 4096, 7.53026646633342), ('twobitCModel14', 'twobitCModel', 16384, 6.07679338544009), ('twobitCModel16', 'twobitCModel', 65536, 6.07679338544009),
('gshareCModel6', 'gshareCModel', 64, 10.6602835418646), ('gshareCModel8', 'gshareCModel', 256, 8.38384710559667), ('gshareCModel10', 'gshareCModel', 1024, 6.36847432155534),
('gshareCModel12', 'gshareCModel', 4096, 3.91108491151983), ('gshareCModel14', 'gshareCModel', 16384, 2.83926519215395), ('gshareCModel16', 'gshareCModel', 65536, .60213659066941)]
RefDataBTB = [('BTBCModel6', 'BTBCModel', 64, 1.11806778745097), ('BTBCModel8', 'BTBCModel', 256, 0.183833943219956), ('BTBCModel10', 'BTBCModel', 1024, 0.0109271020749376),
('BTBCModel12', 'BTBCModel', 4096, 0.00437600802791213), ('BTBCModel14', 'BTBCModel', 16384, 0.00188756234204305), ('BTBCModel16', 'BTBCModel', 65536, 0.00188756234204305)]
def ParseBranchListFile(path):
'''Take the path to the list of Questa Sim log files containing the performance counters outputs. File
@ -436,7 +438,8 @@ performanceCounterList = BuildDataBase(predictorLogs) # builds a databas
benchmarkFirstList = ReorderDataBase(performanceCounterList) # reorder first by benchmark then trace
benchmarkDict = ExtractSelectedData(benchmarkFirstList) # filters to just the desired performance counter metric
if(args.reference): benchmarkDict['Mean'].extend(RefData)
if(args.reference and args.direction): benchmarkDict['Mean'].extend(RefDataBP)
if(args.reference and args.target): benchmarkDict['Mean'].extend(RefDataBTB)
#print(benchmarkDict['Mean'])
#print(benchmarkDict['aha-mont64Speed'])
#print(benchmarkDict)

1
linux/devicetree/wally-artya7.dts
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@ -31,6 +31,7 @@
status = "okay";
compatible = "riscv";
riscv,isa = "rv64imafdcsu";
riscv,isa-extensions = "imafdc", "sstc", "svinval", "svnapot", "svpbmt", "zba", "zbb", "zbc", "zbs", "zicbom", "zicbop", "zicbopz", "zicntr", "zicsr", "zifencei", "zihpm";
mmu-type = "riscv,sv48";
interrupt-controller {

1
linux/devicetree/wally-virt.dts
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@ -31,6 +31,7 @@
status = "okay";
compatible = "riscv";
riscv,isa = "rv64imafdcsu";
riscv,isa-extensions = "svadu";
mmu-type = "riscv,sv48";
interrupt-controller {

15
sim/bpred-sim.py
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@ -114,7 +114,20 @@ def main():
grepstr="")
configs.append(tc)
if(args.target or args.iclass):
if(args.target):
# BTB and class size sweep
bpdSize = [6, 8, 10, 12, 14, 16]
for CurrBPSize in bpdSize:
name = 'BTB'+str(CurrBPSize)
configOptions = "+define+INSTR_CLASS_PRED=0 +define+BPRED_OVERRIDE +define+BPRED_TYPE=\`BP_GSHARE" + "+define+BPRED_SIZE=16" + "+define+RAS_SIZE=16+define+BTB_SIZE=" + str(CurrBPSize) + "+define+BTB_OVERRIDE"
tc = TestCase(
name=name,
variant="rv32gc",
cmd="vsim > {} -c <<!\ndo wally-batch.do rv32gc configOptions " + name + " embench " + configOptions,
grepstr="")
configs.append(tc)
if(args.iclass):
# BTB and class size sweep
bpdSize = [6, 8, 10, 12, 14, 16]
for CurrBPSize in bpdSize:

2
sim/wally-linux-imperas.do
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@ -55,11 +55,13 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
+incdir+$env(IMPERAS_HOME)/ImpProprietary/include/host \
$env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvviApiPkg.sv \
$env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvviTrace.sv \
$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/idvApiPkg.sv \
$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/idvPkg.sv \
$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/idvApiPkg.sv \
$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2api.sv \
$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2log.sv \
$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2cov.sv \
$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2bin.sv \
../src/cvw.sv \
../testbench/testbench-linux-imperas.sv \
../testbench/common/*.sv ../src/*/*.sv \

27
testbench/common/loggers.sv
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@ -45,7 +45,7 @@ module loggers import cvw::*; #(parameter cvw_t P,
// performance counter logging
logic BeginSample;
logic StartSample, EndSample;
if(PrintHPMCounters & P.ZICNTR_SUPPORTED) begin : HPMCSample
if((PrintHPMCounters | BPRED_LOGGER) & P.ZICNTR_SUPPORTED) begin : HPMCSample
integer HPMCindex;
logic StartSampleFirst;
logic StartSampleDelayed, BeginDelayed;
@ -213,26 +213,41 @@ module loggers import cvw::*; #(parameter cvw_t P,
if (P.BPRED_SUPPORTED) begin : BranchLogger
if (BPRED_LOGGER) begin
string direction;
int file;
int file, CFIfile;
logic PCSrcM;
string LogFile;
string LogFile, CFILogFile;
logic resetD, resetEdge;
flopenrc #(1) PCSrcMReg(clk, reset, dut.core.FlushM, ~dut.core.StallM, dut.core.ifu.PCSrcE, PCSrcM);
flop #(1) ResetDReg(clk, reset, resetD);
assign resetEdge = ~reset & resetD;
initial begin
LogFile = "branch.log"; // will break some of Ross's research analysis scripts
CFILogFile = "cfi.log"; // will break some of Ross's research analysis scripts
//LogFile = $psprintf("branch_%s%0d.log", P.BPRED_TYPE, P.BPRED_SIZE);
file = $fopen(LogFile, "w");
CFIfile = $fopen(CFILogFile, "w");
end
always @(posedge clk) begin
if(resetEdge) $fwrite(file, "TRAIN\n");
if(StartSample) $fwrite(file, "BEGIN %s\n", memfilename);
if(resetEdge) begin
$fwrite(file, "TRAIN\n");
$fwrite(CFIfile, "TRAIN\n");
end
if(StartSample) begin
$fwrite(file, "BEGIN %s\n", memfilename);
$fwrite(CFIfile, "BEGIN %s\n", memfilename);
end
if(dut.core.ifu.InstrClassM[0] & ~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin
direction = PCSrcM ? "t" : "n";
$fwrite(file, "%h %s\n", dut.core.PCM, direction);
end
if(EndSample) $fwrite(file, "END %s\n", memfilename);
if((|dut.core.ifu.InstrClassM) & ~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin
direction = PCSrcM ? "t" : "n";
$fwrite(CFIfile, "%h %s\n", dut.core.PCM, direction);
end
if(EndSample) begin
$fwrite(file, "END %s\n", memfilename);
$fwrite(CFIfile, "END %s\n", memfilename);
end
end
end
end

63
testbench/testbench-linux-imperas.sv
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@ -226,21 +226,6 @@ module testbench;
///////////////////////////////////////////////////////////////////////////////
/////////////////////////////// Cache Issue ///////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
// Duplicate copy of pipeline registers that are optimized out of some configurations
logic [31:0] NextInstrE, InstrM;
mux2 #(32) FlushInstrMMux(dut.core.ifu.InstrE, dut.core.ifu.nop, dut.core.ifu.FlushM, NextInstrE);
flopenr #(32) InstrMReg(clk, reset, ~dut.core.ifu.StallM, NextInstrE, InstrM);
logic probe;
if (NO_SPOOFING)
assign probe = testbench.dut.core.PCM == 64'hffffffff80200c8c
& InstrM != 32'h14021273
& testbench.dut.core.InstrValidM;
@ -261,19 +246,20 @@ module testbench;
logic HREADYEXT, HRESPEXT;
logic HCLK, HRESETn;
logic HREADY;
logic HSELEXT;
logic HSELEXT;
logic HSELEXTSDC;
logic [P.PA_BITS-1:0] HADDR;
logic [P.AHBW-1:0] HWDATA;
logic [P.XLEN/8-1:0] HWSTRB;
logic HWRITE;
logic [2:0] HSIZE;
logic [2:0] HBURST;
logic [3:0] HPROT;
logic [1:0] HTRANS;
logic HMASTLOCK;
logic [31:0] GPIOIN;
logic [31:0] GPIOOUT, GPIOEN;
logic UARTSin, UARTSout;
logic [P.AHBW-1:0] HWDATA;
logic [P.XLEN/8-1:0] HWSTRB;
logic HWRITE;
logic [2:0] HSIZE;
logic [2:0] HBURST;
logic [3:0] HPROT;
logic [1:0] HTRANS;
logic HMASTLOCK;
logic [31:0] GPIOIN;
logic [31:0] GPIOOUT, GPIOEN;
logic UARTSin, UARTSout;
// FPGA-specific Stuff
logic SDCCLK;
@ -292,6 +278,21 @@ module testbench;
assign SDCIntr = 0;
///////////////////////////////////////////////////////////////////////////////
/////////////////////////////// Cache Issue ///////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
// Duplicate copy of pipeline registers that are optimized out of some configurations
logic [31:0] NextInstrE, InstrM;
mux2 #(32) FlushInstrMMux(dut.core.ifu.InstrE, dut.core.ifu.nop, dut.core.ifu.FlushM, NextInstrE);
flopenr #(32) InstrMReg(clk, reset, ~dut.core.ifu.StallM, NextInstrE, InstrM);
logic probe;
if (NO_SPOOFING)
assign probe = testbench.dut.core.PCM == 64'hffffffff80200c8c
& InstrM != 32'h14021273
& testbench.dut.core.InstrValidM;
`ifdef USE_IMPERAS_DV
@ -442,10 +443,10 @@ module testbench;
// Wally
wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT, .HSELEXTSDC,
.HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
.HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN,
.UARTSin, .UARTSout, .SDCIntr, .SPICS, .SPIOut, .SPIIn);
wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT, .HSELEXTSDC,
.HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
.HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN,
.UARTSin, .UARTSout, .SDCIntr, .SPIIn, .SPIOut, .SPICS);
// W-stage hardware not needed by Wally itself
parameter nop = 'h13;