Slight modification to testbench.sv

2025-02-02 17:55:19 +00:00 · 2023-10-17 14:13:18 -05:00 · 2023-10-17 14:13:18 -05:00 · 2b1c604016
commit 2b1c604016
parent 03ea0a02e0
1 changed files with 1 additions and 0 deletions
--- a/testbench/testbench.sv
+++ b/testbench/testbench.sv
@ -387,6 +387,7 @@ module testbench;

    assign SDCCmd = SDCCmdOE ? SDCCmdOut : 1'bz;
    assign SDCCmdIn = SDCCmd;
+    assign SDCDat = sd_dat_reg_t ? sd_dat_reg_o : sd_dat_i;
    assign SDCDatIn = SDCDat;
 -----/\----- EXCLUDED -----/\----- */
    assign SDCIntr = '0;