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1931 Commits

Author SHA1 Message Date
bbracker
58d478eb23 restore functionality of being able to turn on waves at a certain instruction count; restore linux-waves.do because wave.do seems to be in disrepair 2021-09-04 19:45:04 -04:00
bbracker
0004f647ec switching over to hopefully more consistent QEMU simulated clock 2021-09-04 19:43:39 -04:00
bbracker
6155716de4 replace triple gdb breakpoint continue with a double breakpoint ignore in hopes of improving parsing 2021-09-04 19:41:55 -04:00
James E. Stine
5bc3569b0e Not sure I understand the Misaligned hptw - seems like a bug and should be L1_ADR instead of L0_ADR 2021-09-03 10:26:38 -05:00
bbracker
4a938e493e output trace to linux-testvectors folder 2021-09-01 17:37:46 -04:00
Ross Thompson
5c2deab4e4 Partial multiway set associative icache. 2021-08-30 10:49:24 -05:00
Katherine Parry
7607adc951 FMA cleanup 2021-08-28 10:53:35 -04:00
Ross Thompson
4b0344898b Fixed bugs I introduced to the icache. 2021-08-27 15:00:40 -05:00
Ross Thompson
2dff72d9e9 Renamed PCMux (icache) to SelAdr to match dcache. 
Removed unused cache files.
 2021-08-27 11:14:10 -05:00
Ross Thompson
de9e234ffa Modified icache to no longer need StallF in the PCMux logic. Instead this is handled in the icachefsm. 
One downside is it increases the icache complexity.  However it also fixes an untested bug.  If a region
was uncacheable it would have been possible for the request to be made multiple times.  Now that is
not possible.  Additionally spills were oscillating between the spill hit states without this change.
The impact was 'benign' as the final spilled instruction always had the correct upper 16 bits.
 2021-08-27 11:03:36 -05:00
Ross Thompson
62d91e9ea1 Renamed ICacheCntrl to icachefsm. 2021-08-26 15:57:17 -05:00
Ross Thompson
cbb47956cb Swapped out the icachemem for cacheway. cacheway is modified to optionally support dirty bits. 2021-08-26 15:43:02 -05:00
Ross Thompson
b230d4daec Finished moving data path logic from the ICacheCntrl.sv to icache.sv. 2021-08-26 13:06:24 -05:00
Ross Thompson
b3849d8abb Moved data path logic from icacheCntrl to icache. 2021-08-26 10:58:19 -05:00
Ross Thompson
c83f0a2e99 Removed unused logic in icache. 2021-08-26 10:49:54 -05:00
Ross Thompson
642efbb563 Converted the icache type from logic to state type. 2021-08-26 10:41:42 -05:00
Ross Thompson
b5d6c4fb46 Additional cleanup of ahblite. 2021-08-25 22:53:20 -05:00
Ross Thompson
bf312bb37c Removed amo logic from ahblite. Removed many unused signals from ahblite. 2021-08-25 22:45:13 -05:00
Ross Thompson
939ff663a5 Forgot to include a few files in the last few commits. 
Also reorganized the dcache by read cpu path, write cpu path, and bus interface path.
Changed i/o names on subwordread to match signals in dcache.
 2021-08-25 22:30:05 -05:00
Ross Thompson
d2b3b7345e Moved dcache fsm to separate module. 2021-08-25 21:37:10 -05:00
Ross Thompson
7be0a73db1 Moved LRU and storage for the LRU into a single module. Also found a subtle bug with the update address used to write the cache's memory. 
This was correct for the LRU but incorrect for the data, tag, valid, and dirty storage.
 2021-08-25 21:09:42 -05:00
Ross Thompson
b5eba44417 Replaced dcache generate ORing with or_rows. 2021-08-25 13:46:36 -05:00
Ross Thompson
83cc0266b2 Rename of DCacheMem to cacheway. 
simplified dcache names.
 2021-08-25 13:33:15 -05:00
Ross Thompson
c48556836b Removed generate around the dcache memories. 2021-08-25 13:27:26 -05:00
Ross Thompson
7139279e50 Moved more logic inside the dcache memory. 2021-08-25 13:17:07 -05:00
Ross Thompson
a99b5f648b partial dcache reorg. 2021-08-25 12:42:05 -05:00
Ross Thompson
699053bab0 Updated linux test bench documenation and scripts. 2021-08-25 10:54:47 -05:00
David Harris
cb13e36d20 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-08-25 06:47:20 -04:00
David Harris
cf1e458ccf simplified or_rows generation and renamed oneHotDecoder to onehotdecoder 2021-08-25 06:46:41 -04:00
Ross Thompson
b7972eafeb Added function tracking to linux test bench. 2021-08-24 11:08:46 -05:00
Ross Thompson
bb3e94d68a Modified the preformance counter's InstRet to include ECALL and EBREAK by changing the hazard logic so these instructions don't self flush the W stage. 2021-08-23 15:46:17 -05:00
Ross Thompson
97653e1aea Wally previously was overcounting retired instructions when they were flushed. 
InstrValidM was used to control when the counter was updated.  However this is
not suppress the counter when the instruction is flushed in the M stage.
 2021-08-23 12:24:03 -05:00
Ross Thompson
f006655bdc Renamed output of qemu trace. 2021-08-22 22:56:34 -05:00
Ross Thompson
b6e2710f5d Confirmed David's changes to the interrupt code. 
When a timer interrupt occurs it should be routed to the machine interrupt
pending MTIP even if MIDELEG[5] = 1 when the current privilege mode is
Machine.  This is true for all the interrupts. The interrupt should not be
masked even though it is delegated to a lower privilege.  Since the CPU
is currently in machine mode the interrupt must be taken if MIE.

Additionally added a new qemu script which pipes together all the parsing and
post processing scripts to produce the singular all.txt trace without the
massivie intermediate files.
 2021-08-22 21:36:31 -05:00
David Harris
696be3ff68 possible interrupt code 2021-08-22 17:02:40 -04:00
Ross Thompson
c0667f30bb Fixed bug with coremark do file. When I moved the testbench to have a common set of files i forgot to remove the old path reference to function_radix.sv in wally-coremark_bare.do. 2021-08-19 10:33:11 -05:00
Ross Thompson
95f5ebaf30 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-08-17 16:06:54 -05:00
Ross Thompson
d3417e309b Minor changes to dcache. 2021-08-17 15:22:10 -05:00
Katherine Parry
facd4062d0 all conversions go through the execute stage result mux 2021-08-16 13:06:09 -04:00
Ross Thompson
66ad510abf Modified the hptw's simulation error message so that synthesis does not attempt to include this statement. 2021-08-16 10:02:29 -05:00
Ross Thompson
4c8ea89f15 Fixed syntax errors in some floating point modules. This came up in 
Xilinx synthesis.
 2021-08-15 16:48:49 -05:00
Ross Thompson
4eca94268c Added logic to linux test bench to not stop simulation on csr write faults. 2021-08-15 11:13:32 -05:00
Ross Thompson
15085448d7 Updated linux-wave.do to have cursors at the timer interrupt problem. 2021-08-13 17:29:37 -05:00
Ross Thompson
4f1f9d6e37 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-08-13 17:23:04 -05:00
Ross Thompson
4f3f26c5cb Switched ExceptionM to dcache to be just exceptions. 
Added test bench logic to hold forces until the W stage is unstalled.
 2021-08-13 15:53:50 -05:00
Ross Thompson
492b6f0ea4 Fixed bugs with CSR checking. The parsing algorithm was messing up the token order after the CSR token. 2021-08-13 14:53:43 -05:00
Ross Thompson
a1c26a16d6 Cleaned up the linux testbench by removing old code and signals. 
Added back in the csr checking logic.
Added code to force timer, external, and software interrupts by using the expected
values from qemu's (m/s)cause registers.
Still need to prevent wally's timer interrupt.
 2021-08-13 14:39:05 -05:00
Katherine Parry
567260751a move some FPU select muxs to execute stage 2021-08-13 14:41:22 -04:00
Ross Thompson
272425c41f Added documentation about how the dcache and ptw interact. 2021-08-12 18:05:36 -05:00
Ross Thompson
618cc18903 Optimized subwordread to reduce critical path from 8 muxes to 5 muxes + 1 AND gate. 2021-08-12 13:36:33 -05:00
Ross Thompson
3b327c949f Minor cleanup of the linux test bench. 2021-08-12 11:14:55 -05:00
Ross Thompson
4dfe326761 Removed unused states from dcache fsm. 2021-08-11 17:06:09 -05:00
Ross Thompson
192392b524 Modified invalid plic reads to return 0 rather than deadbeaf. 2021-08-11 16:56:22 -05:00
Ross Thompson
d0afa397ba Simplified Dcache by sharing the read data mux with the victim selection mux. 2021-08-11 16:55:55 -05:00
Ross Thompson
74e5b60819 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-08-10 13:36:29 -05:00
Ross Thompson
05a32508eb Dcache and LSU clean up. 2021-08-10 13:36:21 -05:00
Katherine Parry
21555c392f LZA added to FMA and attemting a merged FMA and adder in synthesis 2021-08-10 13:57:16 -04:00
Ross Thompson
467e24c05c Fixed another bug with the atomic instrucitons implemention in the dcache. 2021-08-08 22:50:31 -05:00
Ross Thompson
20a04d8cee Fixed another bug with AMO. If the CPU stalled as an AMO was finishing, the write to the 
cache's SRAM would occur.  Then in the next cycle the SRAM would be reread while stalled
providing the new update dated rather than the correct older value.
 2021-08-08 11:42:10 -05:00
Ross Thompson
25533bdc49 Fixed the AMO dcache bug. The subword write needs to occur before the AMO logic. 
Fixed logic for trace update in the M and W stages.  The M stage should not update if there
is an instruction fault.
 2021-08-08 00:28:18 -05:00
Ross Thompson
fda9985382 Finally past the CLINT issues. 2021-08-06 16:41:34 -05:00
Ross Thompson
839822d3b1 Now past the CLINT issues. 2021-08-06 16:16:39 -05:00
Ross Thompson
e1319a2fbe Partial conversion of the linux trace checking to read in the file in the Memory Stage so it is possible to overwrite registers, memory, and interrupts. 2021-08-06 16:06:50 -05:00
Ross Thompson
d430659983 fixed the read timer issue but we still have problems with interrupts and i/o devices. 2021-08-06 10:16:06 -05:00
Ross Thompson
722d298c35 Fixed issue with desync of PCW and ExpectedPCW in linux test bench. The ERROR macro had a 10 ns delay which caused the trace to skip 1 instruction. 2021-08-05 16:49:03 -05:00
Ross Thompson
b7fc737d93 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-30 17:57:13 -05:00
Ross Thompson
245e7014b3 Added some comments to linux testbench. 2021-07-30 17:57:03 -05:00
Ross Thompson
cd8a66353c Patched up changes for wally-pipelined.do and wally-buildroot.do to support moved common testbench files. 2021-07-30 14:24:50 -05:00
Ross Thompson
ef66cdeecf Moved the test bench modules to a common directory. 2021-07-30 14:16:14 -05:00
Ross Thompson
89a7b38f79 Removed 1 cycle delay on store miss. 
Changed some logic to partially support atomics.
 2021-07-30 14:00:51 -05:00
Ross Thompson
b9f8c25280 Created new linux test bench and parsing scripts. 2021-07-29 20:26:50 -05:00
Katherine Parry
d8ca70fc45 all fpu units use the unpacking unit 2021-07-28 23:49:21 -04:00
Ross Thompson
c60a1fed69 Fixed bug which caused stores to take an extra clock cycle. 2021-07-26 12:22:53 -05:00
Ross Thompson
5b376b9846 Fixed bug with the compressed immediate generation. Several formats should zero extend. 2021-07-26 11:55:31 -05:00
Ross Thompson
ce29d0f00f Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
 2021-07-26 11:55:00 -05:00
Ross Thompson
0291d987da Added additional interlock for itlb miss -> instrPageFault with concurrent memory operation. 2021-07-25 23:14:28 -05:00
Katherine Parry
8198e8162a fixed some fpu lint errors 2021-07-24 16:41:12 -04:00
Katherine Parry
85d240c2a5 fpu cleanup 2021-07-24 15:00:56 -04:00
Katherine Parry
67ab0b165c fpu cleanup 2021-07-24 14:59:57 -04:00
Kip Macsai-Goren
8823339aef added tests for 64/32 bit pma/pmp checker. They compile, but skip OVPsim simulation. They DO NOT pass regression yet 2021-07-23 16:02:42 -04:00
Kip Macsai-Goren
0653630d29 added sfence to legal instructions, zeroed out rom file to populate for tests 2021-07-23 15:55:08 -04:00
Kip Macsai-Goren
f02d52ce50 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-23 15:16:01 -04:00
bbracker
d7edfb7a70 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-23 14:00:52 -04:00
bbracker
71ef87bc55 testbench workaround for QEMU's SSTATUS XLEN bits 2021-07-23 14:00:44 -04:00
kipmacsaigoren
3bb6c8b32f Cleaned up priority thermometer verilog. passses regression, ideally shortens critical path through pmp's 2021-07-23 11:57:58 -05:00
David Harris
5306d42bfe Removed LEVELx states from HPTW 2021-07-23 08:11:15 -04:00
Ross Thompson
00f798b37e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-22 19:42:32 -05:00
Ross Thompson
32ec457e09 Removed the hardware page table walker fault state from the icache so that the icache will only unstall CPU for 1 cycle. 
In the dcache we added a register to save the load read data in the event an itlb miss occurs concurrently with
the load in the memory stage.  Under this situation we need to record the load ReadDataM into a temporary register,
SavedReadDataM.  At this time the CPU is stall; however the walker is going to change the address in the dcache
which destroys this data.  When leaving the PTW_READY state via a walker instruction fault or ITLB write we select
this SavedReadDataM so that the CPU can capture it.
 2021-07-22 19:42:19 -05:00
Kip Macsai-Goren
ee1eef3620 include SFENCE.VMA in legal instructions 2021-07-22 20:24:24 -04:00
David Harris
427063ee05 Minor unpacking cleanup 2021-07-22 17:52:37 -04:00
Ross Thompson
007812dbdc Moved the ReadDataW register into the datapath. 
The StallW from the hazard unit controls this.
Previously it was in the dcache and controlled by both the HPTW and hazard unit.
This caused an issue when the CPU expected the data to stay constant while
stalled, but the HPTW was causing the data to be modified.
 2021-07-22 14:52:03 -05:00
Ross Thompson
00858cd401 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-22 14:05:08 -05:00
Ross Thompson
936e034be9 Fixed bug with the itlb fault not dcache ptw ready state to ready state. 2021-07-22 14:04:56 -05:00
David Harris
0822d46e97 Move Z sign swapping out of unpacker 2021-07-22 14:32:38 -04:00
David Harris
85aaa4c6d7 Move Z=0 mux out of unpacker. 2021-07-22 14:28:55 -04:00
David Harris
c04f40d6e5 Move Z=0 mux out of unpacker. 2021-07-22 14:22:28 -04:00
David Harris
625d925369 Partial work on Unpacking exponents to larger word size. FCVT and FMA are presently broken. 2021-07-22 14:18:27 -04:00
David Harris
f4b45adf44 Simplify unpacker 2021-07-22 13:42:16 -04:00
David Harris
02f0c67e6f Simplify unpacker 2021-07-22 13:40:42 -04:00
David Harris
2f23ca2b77 Removed Assumed1 from FPU interface 2021-07-22 13:04:47 -04:00
David Harris
926ffc8a15 Simplified interface to fclassify and fsgn (fixed) 2021-07-22 12:33:38 -04:00
David Harris
ae29eaa98d Simplified interface to fclassify and fsgn 2021-07-22 12:30:46 -04:00
Ross Thompson
42fe5ceee3 Cleaned up icache and dcache. 2021-07-22 11:06:44 -05:00
Ross Thompson
89e22bc5e8 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-22 10:38:24 -05:00
Ross Thompson
e907d57340 Tested all numbers of ways for dcache 1, 2, 4, and 8. 2021-07-22 10:38:07 -05:00
bbracker
9dcd5d3622 fix UART RX FIFO bug where tail pointer can overtake head pointer 2021-07-22 02:09:41 -04:00
bbracker
cdcf419147 make address translator signals visible in waveview 2021-07-21 20:07:49 -04:00
bbracker
70ef670da1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-21 20:07:03 -04:00
bbracker
3c6a1f8824 replace physical address checking with virtual address checking because address translator is broken 2021-07-21 19:47:13 -04:00
bbracker
b48d179c37 hardcoded hack to fix missing STVEC vector 2021-07-21 19:34:57 -04:00
Ross Thompson
1e88784bd4 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-21 16:44:32 -05:00
Kip Macsai-Goren
bb8ec549a7 fixed issue with tlbflush remaining high during a stalled sfence instruction 2021-07-21 17:43:36 -04:00
Ross Thompson
aa624625bc Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-21 16:39:07 -05:00
Ross Thompson
1f0ff804cf Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-21 14:56:30 -05:00
Ross Thompson
511c36fb1b Improved address bus names and usages in the walker, dcache, and tlbs. 
Merge branch 'walkerEnhance' into main
 2021-07-21 14:55:09 -05:00
Ross Thompson
abe57e3fd0 Added comment about better muxing. 2021-07-21 14:40:14 -05:00
Ross Thompson
3d79dc51bb 4 way set associative is now working. 2021-07-21 14:01:14 -05:00
Kip Macsai-Goren
e59490d032 Fixed TLB parameterization and valid bit flop to correctly do instr page faults 2021-07-21 14:44:43 -04:00
Katherine Parry
59f79722ab FDIV and FSQRT work 2021-07-21 14:08:14 -04:00
bbracker
e8b966c5d1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-21 13:04:11 -04:00
bbracker
f7a61a5c73 progress on recovering from QEMU's errors 2021-07-21 13:00:32 -04:00
Ross Thompson
39fc9278ba Fixed remaining bugs in 2 way set associative dcache. 2021-07-21 10:35:23 -05:00
Ross Thompson
ba3aed8760 Finally fixed bug with the set associative design. The issue was not in the LRU but instead in the way selection mux. 
Also forgot to include cacheLRU.sv file.
 2021-07-20 23:17:42 -05:00
Katherine Parry
61f81bb76e FMA parameterized 2021-07-20 22:04:21 -04:00
Ross Thompson
8d0a552b5b Partially working 2 way set associative d cache. 2021-07-20 17:51:42 -05:00
bbracker
d6c93a50aa fix PC checking during InstrPageFault; fix order of S-mode CSR checking; rename peripheral scopes to not be genblk 2021-07-20 17:55:44 -04:00
bbracker
b5ceb6f7c3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-20 15:04:13 -04:00
bbracker
945c8d496f commented out old hack that used hardcoded addresses 2021-07-20 15:03:55 -04:00
David Harris
62b3673027 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-20 14:46:58 -04:00
David Harris
20744883df flag for optional boottim 2021-07-20 14:46:37 -04:00
Ross Thompson
a042c356e1 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-20 13:27:58 -05:00
Ross Thompson
bb5b5e71b1 Replaced FinalReadDataM with ReadDataM in dcache. 2021-07-20 13:27:29 -05:00
bbracker
7694342d4e ignore mhpmcounters because QEMU doesn't implement them 2021-07-20 13:37:52 -04:00
bbracker
761300afcd Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-20 12:08:46 -04:00
David Harris
c117356432 Parameterized I$/D$ configurations and added sanity check assertions in testbench 2021-07-20 08:57:13 -04:00
bbracker
3de8461f3c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-20 05:40:49 -04:00
bbracker
c9775de3b2 testbench hack to ignore MTVAL for illegal instr faults; testbench upgrade to not check PCW for illegal instr faults; testbench hack to not check speculative instrs following an MRET (it seems MRET has 1 stage more latency than a branch instr) 2021-07-20 05:40:39 -04:00
James E. Stine
b36d6fe1be slight mod to fpdiv - still bug in batch vs. non-batch 2021-07-20 01:47:46 -04:00
bbracker
5347a58192 major fixes to CSR checking 2021-07-20 00:22:07 -04:00
Ross Thompson
ae2371f2ce Added performance counters for dcache access and dcache miss. 2021-07-19 22:12:20 -05:00
Ross Thompson
07c47f0034 Restored TIM range. 2021-07-19 21:17:31 -05:00
bbracker
a01fea69dd Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-19 19:30:40 -04:00
bbracker
af5d319f08 change debugBuildroot because GDB formatted list is now 50 lines long per instruction (we lost 6 CSRs on the whole) 2021-07-19 19:30:29 -04:00
David Harris
678f705415 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-19 18:19:59 -04:00
David Harris
b2f7952b3d Added cache configuration to config files 2021-07-19 18:19:46 -04:00
bbracker
aeaf4a31f0 MemRWM shouldn't factor into PCD checking 2021-07-19 18:03:30 -04:00
bbracker
30c381c707 create qemu_output.txt 2021-07-19 18:02:41 -04:00
bbracker
45b78dd8b3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-19 17:11:49 -04:00
bbracker
5911029d2b make testbench ignore MIP because of timing imprecision and because QEMU maybe isn't getting MTIP right anyways 2021-07-19 17:11:42 -04:00
Kip Macsai-Goren
3a73ae0a8b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-19 16:46:46 -04:00
bbracker
bb2e3b1e02 remove busybear from regression because it is not keeping up with buildroot's changes to testbench-linux 2021-07-19 16:22:05 -04:00
bbracker
78e513160e put MTIMECMP's reset value back to 0 because the reset value of -1 broke the MCAUSE tests 2021-07-19 16:19:24 -04:00
bbracker
009e9d97bf adapt testbench to removal of ReadDataWEn signal 2021-07-19 15:42:14 -04:00
bbracker
02de6014b2 adapt testbench to removal of signal 2021-07-19 15:41:50 -04:00
bbracker
76be84fa92 whoops MTIMECMP is always 64 bits 2021-07-19 15:40:53 -04:00
bbracker
fb6e618b1c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-19 15:13:14 -04:00
bbracker
77b690faf0 make testbench check the same CSRs that QEMU logs; change CLINT to reset MTIMECMP to -1 so that we don't instantly get a timer interrupt upon reset 2021-07-19 15:13:03 -04:00
Kip Macsai-Goren
c1c564d54c added changes to priority encoders from synthesis branch (correctly this time I hope) 2021-07-19 15:06:14 -04:00
Ross Thompson
5edd513f8c Furture simplification of the dcache ReadDataW update. 2021-07-19 12:46:31 -05:00
Ross Thompson
5754b5f25f Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-19 12:32:35 -05:00
Ross Thompson
2ee97efb9c Fixed a complex bug in the dcache, where back to back loads would lose data on the load before a stall occurred. The solution was to modify the logic for SelAdrM in the dcache so that a stall would cause the SRAM to reread the address in the Memory stage rather than Execution stage. This also required updating the ReadDataWEn control so it is always enabled on ~StallW. 2021-07-19 12:32:16 -05:00
bbracker
8cbd83e804 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-19 13:21:04 -04:00
bbracker
2702064dda change buildroot expectations to match reality 2021-07-19 13:20:53 -04:00
Ross Thompson
6ccbdc372d Broken. 
Possible change to walker, dcache, tlb addressing.
Improves the naming of address signals.
But has a problem when the walker finishes the dcache does not get the correct
address on the cycle the DTLB is updated.  This leads to incorrect index
selection in the dcache.
 2021-07-19 10:33:27 -05:00
bbracker
986b7a8252 change sram1rw to have a small delay so that we don't have signals changing on clock edges 2021-07-19 11:30:07 -04:00
David Harris
1b55f584c7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-19 10:34:18 -04:00
James Stine
62b4ef6953 delete sbtm_a4 and sbtm_a5 as they are not needed 2021-07-19 08:06:00 -05:00
James Stine
892bc68918 remove sbtm3.sv - not needed 2021-07-19 08:00:53 -05:00
James Stine
55f2720f89 update part I on sbtm change 2021-07-19 07:59:27 -05:00
David Harris
0c41b8102d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-19 00:25:06 -04:00
Katherine Parry
8d101548f1 FDIV and FSQRT passes when simulating in modelsim 2021-07-18 23:00:04 -04:00
bbracker
64a81941ff change memread testvectors to not left-shift bytes and half-words 2021-07-18 21:49:53 -04:00
David Harris
4729a72167 Updated FMA1 with parameterized size 2021-07-18 20:40:49 -04:00
bbracker
f4f3ef0307 linux testbench progress 2021-07-18 18:47:40 -04:00
David Harris
398e9583e9 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-18 17:36:29 -04:00
David Harris
f22b6e7397 Added FLEN, NE, NF to config and started using these in FMA1 2021-07-18 17:28:25 -04:00
Katherine Parry
3527620c0b fdivsqrt inegrated, but not completley working 2021-07-18 14:03:37 -04:00
David Harris
e31d2ef9f5 Renamed pagetablewalker to hptw 2021-07-18 04:11:33 -04:00
David Harris
e962324d00 LSUArb: Removed Demuxes on ReadDataW, DataMiisalignedM, HPTWStall 2021-07-18 03:51:30 -04:00
David Harris
40c5d3ced7 HPTW: Simpliifieid PRegEn 2021-07-18 03:35:38 -04:00
David Harris
a5a7be3e03 Removed EndWalk signal and simplified TLBMissReg 2021-07-18 03:26:43 -04:00
Ross Thompson
a0017e39e2 Fixed bug with rv32a/WALLY-LRSC test in imperas. Minor issue. 2021-07-17 21:02:24 -05:00
Ross Thompson
d0ed6e250a Fixed LRSC in 64bit version. 32bit version is broken. 2021-07-17 20:58:49 -05:00
David Harris
3be88117c5 added lrsc.sv 2021-07-17 21:15:08 -04:00
David Harris
c29a2ff8df Started atomics 2021-07-17 21:11:41 -04:00
David Harris
3783b5dc00 moved subwordread to lsu 2021-07-17 20:37:20 -04:00
David Harris
84f579038c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-17 20:01:23 -04:00
David Harris
d441d4270c LSU cleanup 2021-07-17 20:01:03 -04:00
David Harris
f21582906f Pushing HPTWPAdrM flop into LSUArb 2021-07-17 19:39:18 -04:00
David Harris
989bb7c01b Simplified VPN case statement 2021-07-17 19:34:01 -04:00
Ross Thompson
379cf6c188 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-17 18:27:44 -05:00
David Harris
25450bd7c1 Finished HPTW TranslationPAdr simlification 2021-07-17 19:27:24 -04:00
Ross Thompson
053e9593af Before returning to the ready state the dcache must set SelAdr = 0 on the cycle before. 2021-07-17 18:26:29 -05:00
David Harris
217bf37668 Further TranslationVAdr simplification 2021-07-17 19:24:37 -04:00
David Harris
d8397b5e8b Continued Translation Address Cleanup of TranslationPAdrMux 2021-07-17 19:16:56 -04:00
David Harris
6f73844427 Continued Translation Address Cleanup 2021-07-17 19:09:13 -04:00
David Harris
2e2e948023 Refining address interface between HPTW and LSU 2021-07-17 19:02:18 -04:00
David Harris
12cfe91362 Fixed bad register in I-FSD-01 Imperas test. 2021-07-17 17:08:07 -04:00
David Harris
e3bf8db80b trap.sv comment cleanup 2021-07-17 16:01:07 -04:00
David Harris
b2c2194478 trap.sv cleanup 2021-07-17 15:57:10 -04:00
David Harris
777e983c19 Finished removing PageTableEntry redundant signals from hptw 2021-07-17 15:50:52 -04:00
David Harris
348e69c096 hptw: Removed NonBusTrapM from LSU 2021-07-17 15:24:26 -04:00
David Harris
49ec45d04d hptw: Removed NonBusTrapM from LSU 2021-07-17 15:22:24 -04:00
David Harris
162afcc994 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-17 15:11:43 -04:00
David Harris
e55546da34 hptw: Propagating PageTableEntryF removal through IFU 2021-07-17 15:04:39 -04:00
David Harris
bf56000f4e hptw: Propagating PageTableEntryF removal through LSU 2021-07-17 15:01:01 -04:00
bbracker
56f246463f separated buildroot debugging from buildroot logging 2021-07-17 14:52:34 -04:00
David Harris
d6b8a5e595 hptw: Unified PageTableEntryM and PageTableEntryF outputs of pagetablewalker into PTE 2021-07-17 14:48:44 -04:00
bbracker
6feb95c779 swapped out linux testbench signal names 2021-07-17 14:48:12 -04:00
bbracker
d85da77069 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-17 14:46:38 -04:00
bbracker
ac908bc2e4 swapped out linux testbench signal names 2021-07-17 14:46:18 -04:00
David Harris
ef03ec275c hptw: Added ValidLeaf and ValidNonLeaf for readability, renamed _WDV to _READ states 2021-07-17 14:36:27 -04:00
David Harris
d19679f213 hptw: Eliminated A and D bit faults while walking page table, per spec 2021-07-17 14:29:20 -04:00
David Harris
ad44835e6e hptw: Simplified TranslationVAdr calculation based just on DTLBWalk 2021-07-17 14:16:33 -04:00
David Harris
af02437c3a hptw: renamed DTLBMissQ to DTLBWalk 2021-07-17 14:13:00 -04:00
David Harris
8e966b37f2 hptw: renamed ADRE to ADR 2021-07-17 14:02:59 -04:00
David Harris
95d49e4e9b hptw: replaced PreviousWalkerState with a PageType FSM 2021-07-17 13:54:58 -04:00
David Harris
964f0d9f53 hptw: removed ITLBMissFQ 2021-07-17 13:44:08 -04:00
David Harris
9741b01465 hptw: minor cleanup 2021-07-17 13:40:12 -04:00
David Harris
ee784c19a5 hptw: Simplifed out AnyTLBMiss 2021-07-17 12:07:51 -04:00
David Harris
40989c4e3d hptw: Renamed Memstore to MemWrite 2021-07-17 12:01:43 -04:00
David Harris
ddd9110f7b hptw: Merged RV32/64 FSMs 2021-07-17 11:55:24 -04:00
David Harris
36a8d23222 hptw: FSM simplification 2021-07-17 11:41:43 -04:00
David Harris
6d28f3fe08 hptw: default state should be unreachable 2021-07-17 11:33:16 -04:00
David Harris
ef83a44c4d hptw: factored Misaligned 2021-07-17 11:31:16 -04:00
David Harris
e3b26b7b23 hptw: factored HPTWRead 2021-07-17 11:25:59 -04:00
David Harris
1bbc932bfd hptw: factored HPTWRead 2021-07-17 11:25:52 -04:00
David Harris
37cc2ca30f hptw: factored pregen 2021-07-17 11:11:10 -04:00
David Harris
1595e4f992 HPTW: more cleanup 2021-07-17 04:55:01 -04:00
David Harris
b74f3b14ec HPTW: factored out DTLBWrite/ITLBWrite 2021-07-17 04:44:23 -04:00
David Harris
9775294a6f HPTW: factored out PageTableENtry 2021-07-17 04:40:01 -04:00
David Harris
f168bd6749 more cleaning up FSM 2021-07-17 04:35:51 -04:00
David Harris
e2600bc55d cleaning up FSM 2021-07-17 04:26:41 -04:00
David Harris
52a7dd9ac0 Simplify FSM 2021-07-17 04:12:31 -04:00
David Harris
31a3b39e5c Pulled TranslationPAdr mux out of HPTW FSM 2021-07-17 04:06:26 -04:00
David Harris
7eb03c2ff6 Simplified bad PTE detection 2021-07-17 03:30:17 -04:00
David Harris
b8ee8a8ce0 Pulled out shared PTEReg 2021-07-17 03:21:09 -04:00
David Harris
d3974fafdd Flip-flop clean-up 2021-07-17 03:15:47 -04:00
David Harris
de72dff382 Flip-flop clean-up 2021-07-17 03:12:24 -04:00
David Harris
a5ac606dda Flip-flop clean-up 2021-07-17 03:10:17 -04:00
David Harris
2b0f8e9cf6 Started pagetablewalker cleanup: combined state flops shared for both RV versions 2021-07-17 02:53:52 -04:00
David Harris
fe8910437a Replaced separate PageTypeF and PageTypeM with common PageType 2021-07-17 02:31:23 -04:00
David Harris
622a14cbdd Removed more unused signals from ahblite 2021-07-17 02:21:54 -04:00
David Harris
52fcc47cdf Removed rest of HRDATAW from ahblite 2021-07-17 02:15:24 -04:00
David Harris
1d171d7ea6 Commented out HRDATAW logic in ebu 2021-07-17 02:10:57 -04:00
David Harris
d6f859da18 renamed or_rows.sv 2021-07-16 20:17:03 -04:00
David Harris
f69393f197 Reduced size of physical memory by 16 for performance 2021-07-16 20:10:12 -04:00
Kip Macsai-Goren
3d14d573a0 included virtual memory tests in testbench 2021-07-16 17:57:24 -04:00
Ross Thompson
e9649eb1f5 Made furture progress in the mmu tests. 2021-07-16 15:56:06 -05:00
Ross Thompson
965f34d78f Added guide for Ben to do linux conversion. 2021-07-16 15:04:30 -05:00
Ross Thompson
abce241f68 Also changed the shadow ram's dcache copy widths. 
Merge branch 'dcache' into main
 2021-07-16 14:21:09 -05:00
Ross Thompson
6ab7cd0f4d Updated the config so the tim has a bigger range. 2021-07-16 12:35:00 -05:00
Ross Thompson
bebc7cc5e3 Updated wave file. 2021-07-16 12:34:37 -05:00
Ross Thompson
d3715acf2d Fixed walker fault interaction with dcache. 2021-07-16 12:22:13 -05:00
bbracker
e51ab63a86 reduce number of UART ports to 1 2021-07-16 12:42:29 -04:00
bbracker
d38109bc1c changed stop of linux boot from arch_cpu_idle to do_idle 2021-07-16 12:27:15 -04:00
Ross Thompson
5ca7dc619c Updated the ptw, lsuarb and dcache to hopefully solve the interlock issues. 2021-07-16 11:12:57 -05:00
bbracker
f7092c60d1 incremental linux config de-bloating 2021-07-16 12:08:58 -04:00
bbracker
629d48f20f incremental linux config de-bloating 2021-07-16 11:33:11 -04:00
bbracker
0f1060ceb7 incremental linux config de-bloating 2021-07-16 11:15:25 -04:00
bbracker
fcb63a409a incremental linux config de-bloating 2021-07-16 01:58:21 -04:00
bbracker
0a1aa821b8 incremental linux config de-bloating 2021-07-16 01:54:36 -04:00
bbracker
149be959e0 incremental linux config de-bloating 2021-07-16 01:43:16 -04:00
bbracker
e5e3a60574 incremental linux config de-bloating 2021-07-16 01:33:51 -04:00
bbracker
7266b29656 incremental linux config de-bloating 2021-07-16 01:25:41 -04:00
bbracker
09de4ded87 incremental linux config de-bloating 2021-07-16 01:00:12 -04:00
bbracker
f7b43211ac incremental linux config de-bloating 2021-07-16 00:46:22 -04:00
bbracker
c5e9734851 incremental linux config de-bloating 2021-07-16 00:41:18 -04:00
bbracker
d6a4b8ccfa incremental linux config de-bloating 2021-07-16 00:34:41 -04:00
bbracker
285e5941e2 incremental linux config de-bloating 2021-07-16 00:16:12 -04:00
bbracker
a6071f3fb0 incremental linux config de-bloating 2021-07-16 00:10:31 -04:00
bbracker
226474051d incremental linux config de-bloating 2021-07-15 23:53:15 -04:00
bbracker
0a15468fd5 incremental linux config de-bloating 2021-07-15 23:30:24 -04:00
bbracker
588a7d0341 incremental linux config de-bloating 2021-07-15 23:12:21 -04:00
bbracker
703b72fb89 incremental linux config de-bloating 2021-07-15 23:00:20 -04:00
bbracker
847edccbd7 incremental linux config de-bloating 2021-07-15 21:33:52 -04:00
bbracker
2091a7104e incremental linux config de-bloating 2021-07-15 20:54:36 -04:00
bbracker
a4f9d7a6e5 working linux config 2021-07-15 18:49:54 -04:00
Kip Macsai-Goren
ba5bb12e26 Still broken, midway through fixing understanding of how ptw and datacache interact in time especially wrt adrE, adrM, faults, and tlb interaction. 2021-07-15 18:30:29 -04:00
bbracker
58cbce940a stripped down busybox a bit 2021-07-15 16:07:56 -04:00
Ross Thompson
96aa106852 Found bug in the PMA such that invalid addresses were sent to the tim. Once addressing this issue the sv48 test fails early with a pma access fault. 2021-07-15 11:56:35 -05:00
Ross Thompson
4549a9f1c9 Merge branch 'main' into dcache 2021-07-15 11:55:20 -05:00
Ross Thompson
5fb5ac3d5a Updated wave file. 2021-07-15 11:04:49 -05:00
Ross Thompson
c39a228266 Fixed how the dcache and page table walker stall cpu so that once a tlb miss occurs the CPU is always stalled until the walk is complete, the tlb updated, and the dcache fetched and hits. 2021-07-15 11:00:42 -05:00
Ross Thompson
c954fb510b Renamed DCacheStall to LSUStall in hart and hazard. 
Added missing logic in lsu.
 2021-07-15 10:16:16 -05:00
Ross Thompson
f234875779 dcache STATE_CPU_BUSY needs to assert CommittedM. This is required to ensure a completed memory operation is not bound to an interrupt. ie. MEPC should not be PCM when committed. 2021-07-14 23:08:07 -05:00
Ross Thompson
6163629204 Finally have the ptw correctly walking through the dcache to update the itlb. 
Still not working fully.
 2021-07-14 22:26:07 -05:00
Katherine Parry
701ea38964 Fixed lint warning 2021-07-14 21:24:48 -04:00
Ross Thompson
d41c9d5ad9 Added d cache StallW checks for any time the cache wants to go to STATE_READY. 2021-07-14 17:25:50 -05:00
Ross Thompson
d3a1a2c90a Fixed d cache not honoring StallW for uncache writes and reads. 2021-07-14 17:23:28 -05:00
Katherine Parry
f8b76082e4 fpu unpacking unit created 2021-07-14 17:56:49 -04:00
Ross Thompson
771c7ff130 Routed CommittedM and PendingInterruptM through the lsu arb. 2021-07-14 16:18:09 -05:00
Ross Thompson
1d7aa27316 Fixed a bug where the dcache did not update the read data if the CPU was stalled, but the memory not stalled. 2021-07-14 15:47:38 -05:00
Ross Thompson
3092e5acdf Forgot to include one hot decoder. 2021-07-14 15:46:52 -05:00
Ross Thompson
e17de4eb11 Separated interruptM into PendingInterruptM and InterruptM. The d cache now takes in both exceptions and PendingInterrupts. 
This solves the committedM issue.
 2021-07-14 15:00:33 -05:00
bbracker
04ce2f7256 testvector unlinker for dev purposes 2021-07-14 11:05:34 -04:00
James Stine
a2c0753edb put back for now to test fdiv 2021-07-14 06:48:29 -05:00
bbracker
9b6d45ead9 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-14 00:21:39 -04:00
bbracker
61e6ebd4d3 make testvector scripts agree with new file structure; use symbols to determine end of linux boot 2021-07-14 00:21:29 -04:00
Ross Thompson
ef598d0e79 Implemented uncached reads. 2021-07-13 23:03:09 -05:00
Ross Thompson
b6e5670bc3 Added CommitedM to data cache output. 2021-07-13 22:43:42 -05:00
bbracker
eb8c1bf5e7 needed to create a directory for gdb script 2021-07-13 19:39:57 -04:00
Ross Thompson
278bbfbe3c Partially working changes to support uncached memory access. Not sure what CommitedM is. 2021-07-13 17:24:59 -05:00
James E. Stine
45a6e96673 mod 2 of fpdivsqrt update 2021-07-13 16:59:17 -04:00
James E. Stine
d695be3ad0 Update fpdivsqrt item until move into uarch 2021-07-13 16:53:20 -04:00
bbracker
2036be2ea4 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-13 16:16:04 -04:00
bbracker
dff3970d1c changed QEMU to use different ports 2021-07-13 16:15:51 -04:00
Ross Thompson
b780e471b4 Fixed interaction between icache stall and dcache. On hit dcache needs to enter a cpu busy state when the cpu is stalled. 2021-07-13 14:51:42 -05:00
Ross Thompson
51249a0e04 Fixed the fetch buffer accidental overwrite on eviction. 2021-07-13 14:21:29 -05:00
Ross Thompson
2034a6584f Dcache AHB address generation was wrong. Needed to zero the offset. 2021-07-13 14:19:04 -05:00
Ross Thompson
ee09fa5f58 Moved StoreStall into the hazard unit instead of in the d cache. 2021-07-13 13:20:50 -05:00
David Harris
516b710db6 Fixed busybear by restoring InstrValidW needed by testbench 2021-07-13 14:17:36 -04:00
Ross Thompson
2004b2e044 Fixed back to back store issue. 
Note there is a bug in the lsuarb which needs to arbitrate a few execution stage signals.
 2021-07-13 12:46:20 -05:00
David Harris
9af5cef65a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-13 13:26:51 -04:00
David Harris
283c2cda0e added or.sv 2021-07-13 13:26:40 -04:00
Katherine Parry
b9edbb15eb Fixed writting MStatus FS bits 2021-07-13 13:22:04 -04:00
Katherine Parry
acdd2e4504 Fixed writting MStatus FS bits 2021-07-13 13:20:30 -04:00
David Harris
3427d2b7d6 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-13 13:19:24 -04:00
David Harris
68d1f87101 Fixed InstrValid from W to M stage for CSR performance counters 2021-07-13 13:19:13 -04:00
bbracker
90eb84cc61 updated buildroot make procedure to incorporate configs more robustly 2021-07-13 12:40:14 -04:00
Ross Thompson
40922cf064 Fixed subword write. subword read should not feed into subword write. 2021-07-13 11:21:44 -05:00
Ross Thompson
a314b3cf68 restored rv64ic config back to full sized dtim. 2021-07-13 11:18:54 -05:00
Ross Thompson
d3ffbe0e5d Modularized the shadow memory to reduce performance hit. 2021-07-13 10:55:57 -05:00
Ross Thompson
17dc488010 Got the shadow ram cache flush working. 2021-07-13 10:03:47 -05:00
bbracker
471fe8ab31 whoops I accidentally made main.config into a symbolic link; now it is a source file 2021-07-13 11:00:01 -04:00
bbracker
be81912c52 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-13 10:04:13 -04:00
bbracker
497d8e3f16 working config for a buildroot that boots 2021-07-13 10:04:09 -04:00
David Harris
4be1e8617f Replaced .or with or_rows structural code in MMU read circuitry for synthesis. 2021-07-13 09:32:02 -04:00
Ross Thompson
9fe6190763 Team work on solving the dcache data inconsistency problem. 2021-07-12 23:46:32 -05:00
Ross Thompson
6b42b93886 Now updates the dtim with the dirty data in the dcache. 
Simulation is showing issues.  It lookslike the cache is not
evicting the correct data.
 2021-07-12 15:13:27 -05:00
Ross Thompson
8ca8b9075d Progress towards the test bench flush. 2021-07-12 14:22:13 -05:00
Katherine Parry
a4bd128978 fcvt.sv cleanup 2021-07-11 21:30:01 -04:00
Katherine Parry
0cc07fda1b Almost all convert instructions pass Imperas tests 2021-07-11 18:06:33 -04:00
bbracker
05f9fa65bf rootfs.cpio no longer overlaps 2021-07-11 05:11:12 -04:00
Ross Thompson
282bde7205 Fixed the spurious AHB requests to address 0. Somehow by not having a default 
(else) in the fsm branch selection for STATE_READY in the d cache it was
possible to take an invalid branch through the fsm.
 2021-07-10 22:34:47 -05:00
Ross Thompson
d9fa3af94d Loads are working. 
There is a bug when the icache stalls 1 cycle before the d cache.
 2021-07-10 22:15:44 -05:00
Ross Thompson
a82c4c99c2 Actually writes the correct data now on stores. 2021-07-10 17:48:47 -05:00
Ross Thompson
ee72178eec Write miss with eviction works. 2021-07-10 15:17:40 -05:00
Ross Thompson
0a6c86af94 Write Hits and Write Misses without eviction are working correctly! The next 
step is to add eviction of dirty lines.
 2021-07-10 10:56:25 -05:00
bbracker
e77a9169b6 greatly stripped down unused stuff in linux config 2021-07-10 11:53:35 -04:00
David Harris
488cfa16ff Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-09 19:18:35 -04:00
David Harris
e6fb590187 added missing tlbmixer.sv 2021-07-09 19:18:23 -04:00
bbracker
4556098f0a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-09 18:56:28 -04:00
bbracker
e4f62e32ba fix_mem.py bugfix 2021-07-09 18:56:17 -04:00
Ross Thompson
94b29ec418 Loads in modelsim, but the first store double does not function correctly. The write address is wrong so the cache is updated using the wrong address. 
I think this is do to the cycle latency of stores.  We probably need extra muxes to select between MemPAdrM and MemPAdrW depending on if the write is a
full cache block or a word write from the CPU.
 2021-07-09 17:14:54 -05:00
bbracker
b2cb86d55c organize/update buildroot scripts for new image 2021-07-09 17:03:47 -04:00
Ross Thompson
7e98610651 Design loads in modelsim, but trap is an X. 2021-07-09 15:37:16 -05:00
Ross Thompson
6abd23a61d Lint passes, but I only hope to have loads working. Stores, lr/sc, atomic, are not fully implemented. 
Also faults and the dcache ptw interlock are not implemented.
 2021-07-09 15:16:38 -05:00
David Harris
ef2bcf6ea7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-09 07:53:30 -04:00
David Harris
b09fd0d0a8 Simplified tlbmixer mux to and-or 2021-07-08 23:34:24 -04:00
David Harris
4d53a935b3 Fixed missing stall in InstrRet counter 2021-07-08 20:08:04 -04:00
bbracker
5736fdecbb organize linux-testgen folder, add readme to describe Buildroot process, add Buildroot config source files 2021-07-08 19:18:11 -04:00
Ross Thompson
2efb7a4f81 Renamed signal in LSU toLSU and fromLSU to toDCache and fromDCache. 2021-07-08 18:03:52 -05:00
Ross Thompson
6041aef263 completed read miss branch through dcache fsm. 
The challenge now is to connect to ahb and lsu.
 2021-07-08 17:53:08 -05:00
David Harris
230654ea76 Eliminate reserved bits from TLB RAM 2021-07-08 17:35:00 -04:00
David Harris
f806707cb0 Array of muxes in tlbmixer; abbreviated PPN and VPN to match diagram 2021-07-08 16:58:11 -04:00
David Harris
b1592a0542 TLB cleanup to match diagrams 2021-07-08 16:52:06 -04:00
Ross Thompson
4c5aee3042 This d cache fsm is getting complex. 2021-07-08 15:26:16 -05:00
Ross Thompson
adcc7afffa Partial implementation of the data cache. Missing the fsm. 2021-07-07 17:52:16 -05:00
David Harris
dc44ca4b0b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-07 06:32:29 -04:00
David Harris
6dc49dd073 Renamed tlb ReadLines to Matches 2021-07-07 06:32:26 -04:00
Abe
09a092abd5 Updated MISA defining as well as porting sizes for peripherals (34 to 56) 2021-07-07 02:37:09 -04:00
Abe
244e197348 Changed SvMode to SVMode on line 76 2021-07-06 23:28:58 -04:00
David Harris
1301f4df7f Added ASID matching for CAM 2021-07-06 18:56:25 -04:00
Kip Macsai-Goren
1652e09b38 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-06 18:54:41 -04:00
David Harris
2b26bbbbd7 more TLB name touchups 2021-07-06 18:39:30 -04:00
Kip Macsai-Goren
8dfa28125f fixed upper bits page fault signal 2021-07-06 18:32:47 -04:00
David Harris
73024fee2d connected signals in tlb by name instead of .* 2021-07-06 17:22:10 -04:00
David Harris
18f4fa600a changed tlbphysicalpagemask to structural 2021-07-06 17:16:58 -04:00
David Harris
404ba5988a changed tlbphysicalpagemask to structural 2021-07-06 17:08:04 -04:00
David Harris
78850bfcd8 MMU produces page fault when upper bits aren't equal. Renamed input to MMU to be 'Address' and moved translation mux into MMU out of TLB 2021-07-06 15:29:42 -04:00
Ross Thompson
dc4c26d2a2 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-06 13:45:20 -05:00
Ross Thompson
d85bf23af3 Merged several of the load/store/instruction access faults inside the mmu. 
Still need to figure out what is wrong with the generation of load page fault when dtlb hit.
 2021-07-06 13:43:53 -05:00
bbracker
0e708a72f3 more completely uncomment MMU tests to make sim wally work 2021-07-06 14:33:52 -04:00
Abe
79e62b7c53 Disabled MCOUNTINHIBIT to enable csr counters (changed to 32'h0 on line 140) 2021-07-06 12:37:58 -04:00
Ross Thompson
61f870809d Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-06 10:41:45 -05:00
Ross Thompson
71a23626d5 Fixed bug in the LSU pagetable walker interlock. 2021-07-06 10:41:36 -05:00
David Harris
6d25ea1508 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-06 10:44:17 -04:00
David Harris
4c2cbe3200 Cleaned up tlb output muxing 2021-07-06 10:44:05 -04:00
David Harris
087bed3b67 Replaced muxing of upper address bits with disregarding their match. Moved WriteEnables gate into tlblru to eliminate WriteLines 2021-07-06 10:38:30 -04:00
Kip Macsai-Goren
35f89f9e99 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-06 10:16:34 -04:00
David Harris
69c0358ffd Created tlbcontrol module to hide details 2021-07-06 03:25:11 -04:00
David Harris
6785ed9994 Implemented TSR, TW, TVM, MXR status bits 2021-07-06 01:32:05 -04:00
David Harris
3cb9e5acd3 Fixed adrdecs to use Access signals for TIMs 2021-07-05 23:42:58 -04:00
David Harris
a390736f26 Don't generate HPTW when MEM_VIRTMEM=0 2021-07-05 23:35:44 -04:00
David Harris
e3f6758265 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-05 23:23:17 -04:00
David Harris
8ca7abaa02 Added support for TVM flag in CSRS and to disabl TLB when MEM_VIRTMEM = 0 2021-07-05 20:35:31 -04:00
Ross Thompson
4d9b87a823 Fixed combo loop in the page table walker. 2021-07-05 16:37:26 -05:00
Ross Thompson
59913e13aa Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-05 16:07:27 -05:00
Kip Macsai-Goren
770420b448 added new mmu tests to makefrag and commented out in the testbench 2021-07-05 10:54:30 -04:00
David Harris
e65fb5bb35 Added F_SUPPORTED flag to disable floating point unit when not in MISA 2021-07-05 10:30:46 -04:00
David Harris
b8b7fab02b Fixed disabling MulDiv when not supported. Started adding generate for FPU unsupported 2021-07-04 19:33:46 -04:00
David Harris
bbbc1d2f89 Simplified PLIC with generate 2021-07-04 19:17:15 -04:00
David Harris
ce3edd0288 Renamed Funct3ToLSU/fromLSU -> SizeToLSU/FromLSU and simplified size muxing in lsuArb 2021-07-04 19:02:56 -04:00
David Harris
39fa84efdd Renamed Funct3ToLSU/fromLSU -> SizeToLSU/FromLSU and simplified size muxing in lsuArb 2021-07-04 18:56:30 -04:00
David Harris
d2e3e14cbc Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-04 18:55:24 -04:00
David Harris
57e1111df3 Gave names to for loops in generate blocks for ease of reference 2021-07-04 18:52:16 -04:00
bbracker
825900565c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-04 18:17:16 -04:00
David Harris
cc04009f82 Touched up TLB D and A bit checks 2021-07-04 18:17:09 -04:00
bbracker
11606e96f1 ICacheCntrl now reacts differently to InstrPageFaultF vs ITLBWriteF 2021-07-04 18:17:06 -04:00
Ross Thompson
058c37b5b1 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-04 17:07:57 -05:00
David Harris
595df47a3e Fixed TLB_ENTRIES merge conflict and handling of global PTEs 2021-07-04 18:05:22 -04:00
Ross Thompson
e198f348da Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-04 16:54:31 -05:00
Ross Thompson
2c56e30c73 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-04 16:53:16 -05:00
David Harris
71268cc0e8 Added ASID & Global PTE handling to TLB CAM 2021-07-04 17:53:08 -04:00
David Harris
6b9cfe90d8 Added ASID & Global PTE handling to TLB CAM 2021-07-04 17:52:00 -04:00
Ross Thompson
f2c4df0a5b Removed the TranslationVAdrQ as it is not necessary. 2021-07-04 16:49:34 -05:00
bbracker
a20afc6e1a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-04 17:20:55 -04:00
bbracker
96939328ea for GPIO give priority to clearing interrupts 2021-07-04 17:20:16 -04:00
Ross Thompson
8e48865140 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-04 16:19:39 -05:00
David Harris
d138d6545d Restructured TLB Read as AND-OR operation with one-hot match/read line 2021-07-04 17:01:22 -04:00
David Harris
b59213c83f Reorganized TLB to use one-hot read/write select signals to eliminate decoders and encoders 2021-07-04 16:33:13 -04:00
David Harris
deae60eb1d TLB cleanup 2021-07-04 14:59:04 -04:00
Ross Thompson
8ae0a5bd7d relocated lsuarb and pagetable walker inside the lsu. Does not pass busybear or buildroot, but passes rv32ic and rv64ic. 2021-07-04 13:49:38 -05:00
David Harris
243c03f870 TLB cleanup 2021-07-04 14:37:53 -04:00
David Harris
fed096407b TLB minor organization 2021-07-04 14:30:56 -04:00
David Harris
a5c0dc8c81 Fixed MPRV and MXR checks in TLB 2021-07-04 13:20:29 -04:00
David Harris
5b891e05ac TLB mux and swizzling cleanup 2021-07-04 12:53:52 -04:00
David Harris
622060b99f Replaced generates with arrays in TLB 2021-07-04 12:32:27 -04:00
David Harris
b5df9b282d Added support for PMP lock bits in csrm and repartitioned design to pass around 8-bit PMPCFG entries 2021-07-04 11:39:59 -04:00
David Harris
9276446797 Switched to array notation for pmpchecker 2021-07-04 10:51:56 -04:00
David Harris
c016ab8e58 Commented out some unused modules 2021-07-04 01:40:27 -04:00
David Harris
1bd353c1d7 Merge conflict on linux-waves.do 2021-07-04 01:22:10 -04:00
David Harris
c897bef8cd Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang. 2021-07-04 01:19:38 -04:00
bbracker
17ef10568f optionally output GDB-formatted instruction list to main buildroot folder 2021-07-03 17:25:19 -04:00
Ross Thompson
9b959715a0 removed mmustall and finished port annotations on ptw and lsuArb. 2021-07-03 16:06:09 -05:00
Ross Thompson
fd088f8ecd Added explicit names to lsu, lsuarb and pagetable walker to make the code refactoring process eaiser. 2021-07-03 15:51:25 -05:00
Ben Bracker
66692af57c src/cache/ICacheCntrl.sv 2021-07-03 11:24:41 -05:00
Ben Bracker
d6c7dc02ed fix ICache indenting 2021-07-03 11:11:07 -05:00
David Harris
ee605d7550 Changed IMMU ExecuteAccessF to 1 rather than InstrReadF to fix buildroot; simplified PMP checker 2021-07-03 03:29:33 -04:00
David Harris
d3dedc1637 Cleaned up PMA/PMP checker unused code 2021-07-03 02:25:31 -04:00
Ben Bracker
9709bd78e1 stop busybear from hanging 2021-07-02 17:22:09 -05:00
David Harris
4ec570d2d7 Fixed PMPCFG read faults 2021-07-02 17:08:13 -04:00
Ross Thompson
16e672ada0 Fixed up the physical address generation for 64 bit page table walker. 2021-07-02 15:49:32 -05:00
Ross Thompson
a8fbbb0631 Fixed up the bit widths on the page table walker for rv32. 2021-07-02 15:45:05 -05:00
Ross Thompson
46831035fb Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-02 13:56:49 -05:00
Katherine Parry
4a6abe0f50 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-02 12:56:53 -04:00
Katherine Parry
72406b8a88 FPU update - missing files 2021-07-02 12:53:05 -04:00
Ross Thompson
549b7b2a62 Merge branch 'main' into bigbadbranch 2021-07-02 11:52:26 -05:00
David Harris
1ce98cc100 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-02 12:52:20 -04:00
Katherine Parry
3f61e313d2 FPU update 2021-07-02 12:40:58 -04:00
David Harris
cd6cabac2f Optimized PMP checker logic and added support for configurable number of PMP registers 2021-07-02 11:05:25 -04:00
David Harris
648c09e5ef Optimized PMP checker logic and added support for configurable number of PMP registers 2021-07-02 11:04:13 -04:00
Ross Thompson
2616f41f91 reverted change to the imperas tests order. Accidently commited change which placed the virtual memory tests first. 2021-07-01 18:04:43 -05:00
Ross Thompson
386193de00 added page table walker fault exit for icache. 2021-07-01 17:59:55 -05:00
Ross Thompson
3dae02818c OMG. It's working! 2021-07-01 17:37:53 -05:00
Ross Thompson
9139cd2954 Fixed tab space issue. 2021-07-01 17:17:53 -05:00
Ross Thompson
c3eaa3169e Fixed the wrong virtual address write into the dtlb. 2021-07-01 16:55:16 -05:00
Teo Ene
1d5d7a7840 Flow updated for 90nm 2021-07-01 13:32:42 -05:00
Ross Thompson
9d9415ea67 Got some stores working in virtual memory. 2021-07-01 12:49:09 -05:00
Ross Thompson
be6468c6d9 Icache ITLB interlock fix. 2021-06-30 19:24:59 -05:00
Ross Thompson
4530e43df6 The icache ptw interlock is actually correct now. There needed to be a 1 cycle delay. 2021-06-30 17:02:36 -05:00
Ross Thompson
07a0b66fdf Major rewrite of ptw to remove combo loop. 2021-06-30 16:25:03 -05:00
Ross Thompson
b31e0afc2a The icache now correctly interlocks with the PTW on TLB miss. 2021-06-30 11:24:26 -05:00
Ross Thompson
2598f08782 Page table walker now walks the table. 
Added interlock so the icache stalls.
Page table walker not walking correctly, goes to fault state.
 2021-06-29 22:33:57 -05:00
Katherine Parry
6216bd7172 FPU control signals changed and FMA works 2021-06-28 18:53:58 -04:00
Ross Thompson
ae6140bd94 Don't use this branch walker still broken. 2021-06-28 17:26:11 -05:00
bbracker
a7f810e2c4 trying out Noah and Kaveh's proposed hack for which CSRs to update for QEMU MMU bug 2021-06-26 08:30:58 -04:00
bbracker
aa8da43743 temporarily disable PMP checking for EBU accesses. 2021-06-26 07:19:51 -04:00
bbracker
59b2a49854 split intermediate GDB output file into smaller files for better debug experience 2021-06-26 07:18:26 -04:00
Ross Thompson
8dfbf60b67 AMO and LR/SC instructions now working correctly. 
Page table walking is not working.
 2021-06-25 15:42:07 -05:00
Ross Thompson
a4266c0136 Some progress. Had to change how the page table walker got it's ready. 2021-06-25 15:07:41 -05:00
Ross Thompson
9fd1761fd6 Working through a combo loop. 2021-06-25 14:49:27 -05:00
Ross Thompson
17636b3293 Regression test runs further. The LSU state machine which fakes the Dcache had a few bugs. MemAccessM needed to be squashed on bus faults. 2021-06-25 11:05:17 -05:00
bbracker
9927f771cc linux testbench now ignores HWRITE glitches caused by flush glitches 2021-06-25 09:28:52 -04:00
bbracker
2694a7a43f made testbench-linux's PCDwrong be FlushD 2021-06-25 08:15:19 -04:00
bbracker
4e09793a9a ah merge; I checked and this does pass all of regression except lints 2021-06-25 07:37:06 -04:00
bbracker
aac9b46a1f changed SC M-to-E fowarding to W-to-E forwarding to improve critical path 2021-06-25 07:18:38 -04:00
Kip Macsai-Goren
1485d29dde Light cleanup of signals, style. Changed several signals to account for new Phys Addr sizes as opposed to HADDR. 2021-06-24 20:01:11 -04:00
Kip Macsai-Goren
389b9a510e Removed AHB address, etc signals from physical memory checkers, replaced with physical address from cpu or ptw. Passes lint but not simulations. 2021-06-24 19:59:29 -04:00
Katherine Parry
bc8d660bc5 FPU forwarding reworked pt.1 2021-06-24 18:39:18 -04:00
bbracker
ced5039776 Revert "fixed forwarding" 
This reverts commit 0f4a4a6ade.
 2021-06-24 17:39:37 -04:00
Ross Thompson
d8183e59e4 Works until pma checker breaks the simulation by reading HADDR rather than data physical address. 2021-06-24 14:42:59 -05:00
Ross Thompson
732551d6be Fixed combo loop in between the page table walker and i/dtlb. 2021-06-24 13:47:10 -05:00
Ross Thompson
0377d3b2c9 Progress. 2021-06-24 13:05:22 -05:00
bbracker
0f4a4a6ade fixed forwarding 2021-06-24 11:20:21 -04:00
bbracker
3ae4cd951a make linux testgen be nohup-friendly and make parser account for lr/sc memory accesses 2021-06-24 08:35:00 -04:00
bbracker
3d6b422e34 regression can overcome the fact that buildroots UART prints stuff 2021-06-24 02:00:01 -04:00
bbracker
409a73604c whoops meant to remove notifications from busybear, not buildroot 2021-06-24 01:54:46 -04:00
bbracker
55cf205222 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-24 01:42:41 -04:00
bbracker
b84419ff4e overhauled linux testbench and spoofed MTTIME interrupt 2021-06-24 01:42:35 -04:00
Kip Macsai-Goren
547bf1d0af added a few very simple arbitrations in the lsuArb that pass regression. cleaned up a few unused signals. Added several comments and concerns to lsuarb so I can remember where my thoughts were at the end of the day. 2021-06-23 19:59:06 -04:00
Ross Thompson
abe5bc90bf Partial addition of page table walker arbiter. 2021-06-23 17:03:54 -05:00
Ross Thompson
6134c22aca Split the ReadDataW bus into two parts in preparation for the data cache. On the AHB side it is now HRDATAW and on the CPU to data cache side it is ReadDataW. lsu.sv now handles the connection between the two. 
Also reorganized the inputs and outputs of lsu and pagetablewalker into connects between CPU, pagetablewalker, and AHB.
Finally add DisableTranslation to TLB as teh pagetablewalker will need to force no translation when active regardless of the state of SATP.
With Kip.
 2021-06-23 16:43:22 -05:00
Katherine Parry
44af47608c fpu clean-up 2021-06-23 16:42:40 -04:00
Ross Thompson
d5063bee7d Updated icache to abhlite to use pa_bits length and moved F/D stage instr register to ifu from icache. 2021-06-23 15:13:56 -05:00
Ross Thompson
5de7a46237 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-06-23 09:34:42 -05:00
David Harris
718630c378 Reduced complexity of pmpadrdec 2021-06-23 03:03:52 -04:00
David Harris
4189b2d4a7 Reduced complexity of pmpadrdec 2021-06-23 02:31:50 -04:00
David Harris
1972d83002 Refactored pmachecker to have adrdecs used in uncore 2021-06-23 01:41:00 -04:00
David Harris
6dc54acde8 renamed dmem to lsu and removed adrdec module from pmpadrdec 2021-06-22 23:03:43 -04:00
bbracker
ae0fa90450 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-22 18:28:30 -04:00
bbracker
b43a8885cd give EBU a dedicated PMA unit as just an address decoder 2021-06-22 18:28:08 -04:00
Ross Thompson
e7d8d0b337 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-06-22 15:47:16 -05:00
Katherine Parry
9eb6eb40bf rv64f FLW passes imperas tests 2021-06-22 16:36:16 -04:00
Kip Macsai-Goren
d6c5c61b59 Fixed mask assignment error, made usage, variables more clear 2021-06-22 13:31:06 -04:00
Kip Macsai-Goren
b78c09baed Continued fixing fsm to work right with svmode 2021-06-22 13:29:49 -04:00
Kip Macsai-Goren
852bb9296f updated so svmode actually causes the right state tranitions. fsm now stuck in idle loop 2021-06-22 11:21:11 -04:00
bbracker
56b0d4d016 added slack notifier for long sims 2021-06-22 08:31:41 -04:00
Ross Thompson
03084a4128 Icache now uses physical lenght bits rather than XLEN. 2021-06-21 16:41:09 -05:00
Ross Thompson
8ec5b0c4f1 Improved some names in icache. 2021-06-21 16:40:37 -05:00
David Harris
82515862e3 Commented out 100k tests to improve speed 2021-06-21 01:43:18 -04:00
David Harris
29ad38fb9e Added Physical Address and Size to PMA Checker/MMU 2021-06-21 01:27:02 -04:00
David Harris
aef408af58 Reversed [0:...] with [...:0] in bus widths across the project 2021-06-21 01:17:08 -04:00
David Harris
0a59b006ab Cleaned up fcsr code and added _SUPPORTED to optionally disable peripherals 2021-06-20 22:59:04 -04:00
bbracker
83a1f29c37 remove OVP_CSR_CONFIG because it is an alias of BUSYBEAR 2021-06-20 22:38:25 -04:00
bbracker
5afad80432 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-20 22:29:40 -04:00
bbracker
665a67f442 linux actually uses FPU now! 2021-06-20 22:29:21 -04:00
Katherine Parry
26bad083ad all rv64f instructions except convert, divide, square root, and FLD pass 2021-06-20 20:24:09 -04:00
bbracker
1f2a967e0f read from MSTATUS workaround because QEMU has incorrect MSTATUS 2021-06-20 10:11:39 -04:00
bbracker
2611d214a6 testbench update b/c QEMU extends 32b CSRs to 64b 2021-06-20 09:24:19 -04:00
bbracker
7aa2f0d953 make xCOUNTEREN what buildroot expects it to be 2021-06-20 09:22:31 -04:00
bbracker
6e9c6e3e6a whoops wavedo typo 2021-06-20 05:36:54 -04:00
bbracker
9469367da3 make buildroot ignore SSTATUS because QEMU did not originally log it 2021-06-20 05:31:24 -04:00
bbracker
78f4703dc9 MSTATUS workaround 2021-06-20 04:48:09 -04:00
bbracker
927d99cf3b workaround for ignoring MTIME 2021-06-20 02:26:39 -04:00
bbracker
52fb630379 remove lingering busybear stuff from buildroot do files 2021-06-20 00:50:53 -04:00
bbracker
124ef980e3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-20 00:40:44 -04:00
bbracker
3e32ba3684 make buildroot waves only turn on after a user-specified point 2021-06-20 00:39:30 -04:00
Ross Thompson
bb756849a7 Revert "Icache now uses physical lenght bits rather than XLEN." 
This reverts commit d4de8a54a2.
 2021-06-19 08:58:34 -05:00
Ross Thompson
e4c932265d Revert "Improved some names in icache." 
This reverts commit 22ea801edb.
 2021-06-19 08:58:32 -05:00
bbracker
ebe893b70c change buildroot config to use relative path for testvectors 2021-06-18 22:28:07 -04:00
bracker
3d99c9c2c4 gitignore merge 2021-06-18 21:12:05 -05:00
bracker
ed75172f21 handle tera usernames more gracefully 2021-06-18 21:11:14 -05:00
bbracker
10ca2ac5bc on-Tera solution for sym linking to linux testvectors 2021-06-18 22:01:18 -04:00
bracker
a9f9ef1180 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-18 20:41:01 -05:00
bracker
8a8b0dcfd7 script support for copying large files from tera 2021-06-18 20:40:19 -05:00
bbracker
f394b91515 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-18 17:37:49 -04:00
bbracker
f84a689c19 fixed PCtext error by using blocking assignments 2021-06-18 17:37:40 -04:00
Ross Thompson
0250d52ae3 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-06-18 12:24:42 -05:00
Ross Thompson
22ea801edb Improved some names in icache. 2021-06-18 12:22:41 -05:00
Ross Thompson
d4de8a54a2 Icache now uses physical lenght bits rather than XLEN. 2021-06-18 12:02:59 -05:00
David Harris
43bc17350b Restored wally-busybear testbench now that graphical sim is working 2021-06-18 12:36:25 -04:00
bbracker
958f60c704 restore graphical buildroot sim 2021-06-18 11:58:16 -04:00
Abe
892c14430b Updated directory coremark_bare's wally-config file to define PMP_ENTRIES 2021-06-18 11:46:25 -04:00
bbracker
1e93bbd119 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-18 09:49:37 -04:00
bbracker
72f1e3eab6 buildroot added to regression because it passes regression 2021-06-18 09:49:30 -04:00
David Harris
21a55458ca Made MemPAdrM and related signals PA_BITS wide 2021-06-18 09:36:22 -04:00
David Harris
a3f3533cce Changed physical addresses to PA_BITS in size in MMU and TLB 2021-06-18 09:11:31 -04:00
bbracker
0980ce92bc Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-18 08:15:40 -04:00
bbracker
8ae333a6b2 remove unused testbench-busybear.sv 2021-06-18 08:15:19 -04:00
David Harris
cc78504ae4 Cleaned up PMAAccessFult logic but it still doesn't accomdate TIM and BootTim depending on AccessRWX 2021-06-18 08:13:15 -04:00
David Harris
72d8d34e3c allow all size memory access in CLINT; added underscore to peripheral address symbols 2021-06-18 08:05:50 -04:00
David Harris
e03912f64c Cleaned up name of MTIME register in CSRC 2021-06-18 07:53:49 -04:00
David Harris
8357b14957 Further cleaning of PMA checker 2021-06-17 22:27:39 -04:00
David Harris
91a13999a9 Added SUPPORTED to each peripheral in each config file 2021-06-17 21:36:32 -04:00
David Harris
5e7ed4bd88 added inputs to pmaadrdec 2021-06-17 18:54:39 -04:00
David Harris
09c5e27853 Started simplifying PMA checker 2021-06-17 16:28:06 -04:00
bbracker
076469230f added MTIME and MTIMECMP as read-only CSRs; this likely is not the final version 2021-06-17 12:09:10 -04:00
bbracker
db0abfd36d enable TIME CSR for 32 bit mode as well 2021-06-17 11:34:16 -04:00