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Fixed the wrong virtual address write into the dtlb.

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This commit is contained in:
Ross Thompson 2021-07-01 16:55:16 -05:00
parent 9d9415ea67
commit c3eaa3169e
3 changed files with 61 additions and 102 deletions
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73
wally-pipelined/regression/wave.do
View File

@ -118,18 +118,18 @@ add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/a
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/b
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/result
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/flags
add wave -noupdate -group alu -divider internals
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/overflow
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/carry
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/zero
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/neg
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/lt
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/ltu
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/a
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/b
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/result
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/flags
add wave -noupdate -expand -group alu -divider internals
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/overflow
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/carry
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/zero
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/neg
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/lt
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/ltu
add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1D
add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs2D
add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1E
@ -241,6 +241,7 @@ add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED
add wave -noupdate -group AHB /testbench/dut/hart/ebu/StallW
add wave -noupdate -expand -group lsu -color Gold /testbench/dut/hart/lsu/CurrState
add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/DisableTranslation
add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemRWM
add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/DataStall
add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemAdrM
@ -316,16 +317,17 @@ add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/h
add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/pagetablewalker/WalkerStorePageFaultM
add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/pagetablewalker/MMUStall
add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/pagetablewalker/EndWalk
add wave -noupdate -expand -group {LSU ARB} -color Gold /testbench/dut/hart/arbiter/CurrState
add wave -noupdate -expand -group {LSU ARB} /testbench/dut/hart/arbiter/SelPTW
add wave -noupdate -expand -group {LSU ARB} -expand -group hptw /testbench/dut/hart/arbiter/HPTWTranslate
add wave -noupdate -expand -group {LSU ARB} -expand -group hptw /testbench/dut/hart/arbiter/HPTWRead
add wave -noupdate -expand -group {LSU ARB} -expand -group hptw /testbench/dut/hart/arbiter/HPTWPAdr
add wave -noupdate -expand -group {LSU ARB} -expand -group hptw /testbench/dut/hart/arbiter/HPTWReadPTE
add wave -noupdate -expand -group {LSU ARB} -expand -group hptw /testbench/dut/hart/arbiter/HPTWReady
add wave -noupdate -expand -group {LSU ARB} -expand -group toLSU /testbench/dut/hart/arbiter/MemAdrMtoLSU
add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/MMUPAdr
add wave -noupdate -group {LSU ARB} -color Gold /testbench/dut/hart/arbiter/CurrState
add wave -noupdate -group {LSU ARB} /testbench/dut/hart/arbiter/SelPTW
add wave -noupdate -group {LSU ARB} -expand -group hptw /testbench/dut/hart/arbiter/HPTWTranslate
add wave -noupdate -group {LSU ARB} -expand -group hptw /testbench/dut/hart/arbiter/HPTWRead
add wave -noupdate -group {LSU ARB} -expand -group hptw /testbench/dut/hart/arbiter/HPTWPAdr
add wave -noupdate -group {LSU ARB} -expand -group hptw /testbench/dut/hart/arbiter/HPTWReadPTE
add wave -noupdate -group {LSU ARB} -expand -group hptw /testbench/dut/hart/arbiter/HPTWReady
add wave -noupdate -group {LSU ARB} -expand -group toLSU /testbench/dut/hart/arbiter/MemAdrMtoLSU
add wave -noupdate /testbench/dut/hart/lsu/DataStall
add wave -noupdate -expand -group csr /testbench/dut/hart/priv/csr/MIP_REGW
add wave -noupdate -group csr /testbench/dut/hart/priv/csr/MIP_REGW
add wave -noupdate /testbench/dut/uncore/genblk2/plic/ExtIntM
add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HCLK
add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HRESETn
@ -351,10 +353,31 @@ add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genb
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/RXRDYb
add wave -noupdate -expand -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss
add wave -noupdate -expand -group dtlb /testbench/dut/hart/lsu/dmmu/tlb/TLBWrite
add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/ITLBMissF
add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF
add wave -noupdate /testbench/dut/hart/pagetablewalker/StartWalk
add wave -noupdate /testbench/dut/hart/lsu/dmmu/tlb/DisableTranslation
add wave -noupdate -group tlbread /testbench/dut/hart/lsu/dmmu/tlb/VirtualAddress
add wave -noupdate -group tlbread /testbench/dut/hart/lsu/dmmu/tlb/tlbcam/CAMHit
add wave -noupdate -group tlbread /testbench/dut/hart/lsu/dmmu/tlb/tlbcam/VPNIndex
add wave -noupdate -group tlbread /testbench/dut/hart/lsu/dmmu/tlb/tlbcam/HitPageType
add wave -noupdate -group tlbread /testbench/dut/hart/lsu/dmmu/tlb/tlbcam/VirtualPageNumber
add wave -noupdate -group tlbwrite /testbench/dut/hart/lsu/dmmu/tlb/tlbcam/TLBWrite
add wave -noupdate -group tlbwrite /testbench/dut/hart/lsu/dmmu/tlb/PTEWriteVal
add wave -noupdate -group tlbwrite /testbench/dut/hart/lsu/dmmu/tlb/tlbcam/WriteLines
add wave -noupdate /testbench/dut/hart/lsu/dmmu/tlb/SATP_REGW
add wave -noupdate /testbench/dut/hart/lsu/dmmu/tlb/STATUS_MXR
add wave -noupdate /testbench/dut/hart/lsu/dmmu/tlb/STATUS_SUM
add wave -noupdate /testbench/dut/hart/lsu/dmmu/tlb/PrivilegeModeW
add wave -noupdate /testbench/dut/hart/lsu/dmmu/tlb/TLBAccessType
add wave -noupdate /testbench/dut/hart/lsu/dmmu/tlb/DisableTranslation
add wave -noupdate /testbench/dut/hart/lsu/dmmu/tlb/VirtualAddress
add wave -noupdate /testbench/dut/hart/lsu/dmmu/tlb/PTEWriteVal
add wave -noupdate /testbench/dut/hart/lsu/dmmu/tlb/PageTypeWriteVal
add wave -noupdate /testbench/dut/hart/lsu/dmmu/tlb/TLBWrite
add wave -noupdate /testbench/dut/hart/lsu/dmmu/tlb/TLBFlush
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 5} {11172515 ns} 0} {{Cursor 8} {3377 ns} 0}
quietly wave cursor active 2
WaveRestoreCursors {{Cursor 8} {3766 ns} 0} {{Cursor 3} {3377 ns} 0} {{Cursor 4} {3215 ns} 0}
quietly wave cursor active 3
configure wave -namecolwidth 250
configure wave -valuecolwidth 189
configure wave -justifyvalue left
@ -369,4 +392,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {3091 ns} {3683 ns}
WaveRestoreZoom {3163 ns} {3403 ns}

6
wally-pipelined/src/lsu/lsu.sv
View File

@ -225,7 +225,7 @@ module lsu (
STATE_READY:
if (DTLBMissM) begin
NextState = STATE_PTW_READY;
DataStall = 1'b0;
DataStall = 1'b1;
end else if (AtomicMaskedM[1]) begin
NextState = STATE_FETCH_AMO_1; // *** should be some misalign check
DataStall = 1'b1;
@ -278,7 +278,7 @@ module lsu (
STATE_PTW_READY: begin
DataStall = 1'b0;
if (DTLBWriteM) begin
NextState = STATE_PTW_DONE;
NextState = STATE_READY;
end else if (MemReadM & ~DataMisalignedM) begin
NextState = STATE_PTW_FETCH;
end else begin
@ -290,7 +290,7 @@ module lsu (
if (MemAckW & ~DTLBWriteM) begin
NextState = STATE_PTW_READY;
end else if (MemAckW & DTLBWriteM) begin
NextState = STATE_PTW_DONE;
NextState = STATE_READY;
end else begin
NextState = STATE_PTW_FETCH;
end

84
wally-pipelined/src/mmu/pagetablewalker.sv
View File

@ -148,7 +148,8 @@ module pagetablewalker (
assign StartWalk = WalkerState == IDLE && (DTLBMissM | ITLBMissF);
assign EndWalk = (WalkerState == LEVEL0 && ValidPTE && LeafPTE && ~AccessAlert) ||
assign EndWalk = WalkerState == LEAF ||
//(WalkerState == LEVEL0 && ValidPTE && LeafPTE && ~AccessAlert) ||
(WalkerState == LEVEL1 && ValidPTE && LeafPTE && ~AccessAlert) ||
(WalkerState == LEVEL2 && ValidPTE && LeafPTE && ~AccessAlert) ||
(WalkerState == LEVEL3 && ValidPTE && LeafPTE && ~AccessAlert) ||
@ -351,13 +352,14 @@ module pagetablewalker (
// access bit. The following commented line of code is
// supposed to perform that check. However, it is untested.
if (ValidPTE && LeafPTE && ~BadTerapage) begin
NextWalkerState = IDLE;
NextWalkerState = LEAF;
PageTableEntry = CurrentPTE;
PageType = (WalkerState == LEVEL3) ? 2'b11 :
((WalkerState == LEVEL2) ? 2'b10 :
((WalkerState == LEVEL1) ? 2'b01 : 2'b00));
DTLBWriteM = DTLBMissMQ;
ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions
TranslationPAdr = TranslationVAdrQ;
end
// else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line.
else if (ValidPTE && ~LeafPTE) begin
@ -390,13 +392,14 @@ module pagetablewalker (
// access bit. The following commented line of code is
// supposed to perform that check. However, it is untested.
if (ValidPTE && LeafPTE && ~BadGigapage) begin
NextWalkerState = IDLE;
NextWalkerState = LEAF;
PageTableEntry = CurrentPTE;
PageType = (WalkerState == LEVEL3) ? 2'b11 :
((WalkerState == LEVEL2) ? 2'b10 :
((WalkerState == LEVEL1) ? 2'b01 : 2'b00));
DTLBWriteM = DTLBMissMQ;
ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions
TranslationPAdr = TranslationVAdrQ;
end
// else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line.
else if (ValidPTE && ~LeafPTE) begin
@ -429,13 +432,14 @@ module pagetablewalker (
// access bit. The following commented line of code is
// supposed to perform that check. However, it is untested.
if (ValidPTE && LeafPTE && ~BadMegapage) begin
NextWalkerState = IDLE;
NextWalkerState = LEAF;
PageTableEntry = CurrentPTE;
PageType = (WalkerState == LEVEL3) ? 2'b11 :
((WalkerState == LEVEL2) ? 2'b10 :
((WalkerState == LEVEL1) ? 2'b01 : 2'b00));
DTLBWriteM = DTLBMissMQ;
ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions
TranslationPAdr = TranslationVAdrQ;
end
// else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line.
@ -464,14 +468,14 @@ module pagetablewalker (
LEVEL0: begin
if (ValidPTE && LeafPTE && ~AccessAlert) begin
NextWalkerState = IDLE;
NextWalkerState = LEAF;
PageTableEntry = CurrentPTE;
PageType = (WalkerState == LEVEL3) ? 2'b11 :
((WalkerState == LEVEL2) ? 2'b10 :
((WalkerState == LEVEL1) ? 2'b01 : 2'b00));
DTLBWriteM = DTLBMissMQ;
ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions
TranslationPAdr = TranslationVAdrQ;
end else begin
NextWalkerState = FAULT;
WalkerInstrPageFaultF = ~DTLBMissMQ;
@ -516,74 +520,6 @@ module pagetablewalker (
assign VPN1 = TranslationVAdrQ[29:21];
assign VPN0 = TranslationVAdrQ[20:12];
always_comb begin
// default values
//TranslationPAdr = '0;
/* -----\/----- EXCLUDED -----\/-----
PageTableEntry = '0;
PageType = '0;
DTLBWriteM = '0;
ITLBWriteF = '0;
WalkerInstrPageFaultF = '0;
WalkerLoadPageFaultM = '0;
WalkerStorePageFaultM = '0;
-----/\----- EXCLUDED -----/\----- */
// The MMU defaults to stalling the processor
//MMUStall = '1;
case (NextWalkerState)
IDLE: begin
//MMUStall = '0;
end
LEVEL3: begin
//TranslationPAdr = {BasePageTablePPN, VPN3, 3'b000};
// *** this is a huge breaking point. if we're going through level3 every time, even when sv48 is off,
// what should translationPAdr be when level3 is just off?
end
LEVEL3_WDV: begin
//TranslationPAdr = {BasePageTablePPN, VPN3, 3'b000};
// *** this is a huge breaking point. if we're going through level3 every time, even when sv48 is off,
// what should translationPAdr be when level3 is just off?
end
LEVEL2: begin
//TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000};
end
LEVEL2_WDV: begin
//TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000};
end
LEVEL1: begin
//TranslationPAdr = {CurrentPPN, VPN1, 3'b000};
end
LEVEL1_WDV: begin
//TranslationPAdr = {CurrentPPN, VPN1, 3'b000};
end
LEVEL0: begin
//TranslationPAdr = {CurrentPPN, VPN0, 3'b000};
end
LEVEL0_WDV: begin
//TranslationPAdr = {CurrentPPN, VPN0, 3'b000};
end
LEAF: begin
// Keep physical address alive to prevent HADDR dropping to 0
//TranslationPAdr = {CurrentPPN, VPN0, 3'b000};
end
FAULT: begin
// Keep physical address alive to prevent HADDR dropping to 0
//TranslationPAdr = {CurrentPPN, VPN0, 3'b000};
/* -----\/----- EXCLUDED -----\/-----
WalkerInstrPageFaultF = ~DTLBMissMQ;
WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore;
WalkerStorePageFaultM = DTLBMissMQ && MemStore;
-----/\----- EXCLUDED -----/\----- */
//MMUStall = '0; // Drop the stall early to enter trap handling code
end
default: begin
// nothing
end
endcase
end
// Capture page table entry from ahblite
flopenr #(`XLEN) ptereg(clk, reset, PRegEn, MMUReadPTE, SavedPTE);