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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main

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bbracker 2021-07-09 18:56:28 -04:00
commit 4556098f0a
4 changed files with 5 additions and 5 deletions
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4
wally-pipelined/src/mmu/tlbcontrol.sv
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@ -64,7 +64,7 @@ module tlbcontrol #(parameter TLB_ENTRIES = 8,
// Grab the sv mode from SATP and determine whether translation should occur
assign EffectivePrivilegeMode = (ITLB == 1) ? PrivilegeModeW : (STATUS_MPRV ? STATUS_MPP : PrivilegeModeW); // DTLB uses MPP mode when MPRV is 1
assign Translate = (SATP_MODE != `NO_TRANSLATE) & (EffectivePrivilegeMode != `M_MODE) & ~ DisableTranslation;
assign Translate = (SATP_MODE != `NO_TRANSLATE) & (EffectivePrivilegeMode != `M_MODE) & ~DisableTranslation;
generate
if (`XLEN==64) begin
assign SV39Mode = (SATP_MODE == `SV39);
@ -122,5 +122,5 @@ module tlbcontrol #(parameter TLB_ENTRIES = 8,
endgenerate
assign TLBHit = CAMHit & TLBAccess;
assign TLBMiss = ~TLBHit & ~TLBFlush & Translate & TLBAccess;
assign TLBMiss = ~CAMHit & ~TLBFlush & Translate & TLBAccess;
endmodule

2
wally-pipelined/src/mmu/tlblru.sv
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@ -48,5 +48,5 @@ module tlblru #(parameter TLB_ENTRIES = 8) (
assign AllUsed = &RUBitsAccessed; // if all recently used, then clear to none
assign RUBitsNext = AllUsed ? 0 : RUBitsAccessed;
flopenrc #(TLB_ENTRIES) lrustate(clk, reset, TLBFlush, (CAMHit || TLBWrite), RUBitsNext, RUBits);
// *** seems like enable must be ORd with TLBFlush to ensure flop fires on a flush. DH 7/8/21
endmodule

2
wally-pipelined/src/privileged/csrc.sv
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@ -114,7 +114,7 @@ module csrc #(parameter
// Counter adders with inhibits for power savings
assign CYCLEPlusM = CYCLE_REGW + {63'b0, ~MCOUNTINHIBIT_REGW[0]};
//assign TIMEPlusM = TIME_REGW + 1; // can't be inhibited
assign INSTRETPlusM = INSTRET_REGW + {63'b0, InstrValidW & ~MCOUNTINHIBIT_REGW[2]};
assign INSTRETPlusM = INSTRET_REGW + {63'b0, InstrValidW & ~StallW & ~MCOUNTINHIBIT_REGW[2]};
//assign HPMCOUNTER3PlusM = HPMCOUNTER3_REGW + {63'b0, LoadStallD & ~MCOUNTINHIBIT_REGW[3]}; // count load stalls
//assign HPMCOUNTER4PlusM = HPMCOUNTER4_REGW + {63'b0, 1'b0 & ~MCOUNTINHIBIT_REGW[4]}; // change to count signals
assign NextCYCLEM = WriteCYCLEM ? CSRWriteValM : CYCLEPlusM[`XLEN-1:0];

2
wally-pipelined/src/privileged/csrs.sv
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@ -93,7 +93,7 @@ module csrs #(parameter
if (`MEM_VIRTMEM)
flopenr #(`XLEN) SATPreg(clk, reset, WriteSATPM, CSRWriteValM, SATP_REGW);
else
assign SATP_REGW = 0;
assign SATP_REGW = 0; // hardwire to zero if virtual memory not supported
if (`BUSYBEAR == 1)
flopenl #(32) SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, {CSRWriteValM[31:2],1'b0,CSRWriteValM[0]}, 32'b0, SCOUNTEREN_REGW);
else if (`BUILDROOT == 1)