mirror of
https://github.com/openhwgroup/cvw
synced 2025-01-24 13:34:28 +00:00
Confirmed David's changes to the interrupt code.
When a timer interrupt occurs it should be routed to the machine interrupt pending MTIP even if MIDELEG[5] = 1 when the current privilege mode is Machine. This is true for all the interrupts. The interrupt should not be masked even though it is delegated to a lower privilege. Since the CPU is currently in machine mode the interrupt must be taken if MIE. Additionally added a new qemu script which pipes together all the parsing and post processing scripts to produce the singular all.txt trace without the massivie intermediate files.
This commit is contained in:
Ross Thompson
parent
696be3ff68
commit
b6e2710f5d
18
wally-pipelined/linux-testgen/testvector-generation/CreateTrace.sh
Executable file
18
wally-pipelined/linux-testgen/testvector-generation/CreateTrace.sh
Executable file
@ -0,0 +1,18 @@
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#!/bin/bash
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# Oftentimes this script runs so long you'll go to sleep.
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# But you don't want the script to die when your computer goes to sleep.
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# So consider invoking this with nohup (i.e. "nohup ./logAllBuildroot.sh")
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# You can run "tail -f nohup.out" to see what would've
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# outputted to the terminal if you didn't use nohup
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#customQemu="/courses/e190ax/qemu_sim/rv64_initrd/qemu_experimental/qemu/build/qemu-system-riscv64"
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customQemu="qemu-system-riscv64"
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imageDir="../buildroot-image-output"
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intermedDir="../linux-testvectors/intermediate-outputs"
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outDir="../linux-testvectors"
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# - Logs info needed by buildroot testbench
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#($customQemu -M virt -nographic -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio -d nochain,cpu,in_asm -serial /dev/null -singlestep -gdb tcp::1236 -S 2>&1 >/dev/null | ./parseNew.py "$outDir") & riscv64-unknown-elf-gdb -x gdbinit_qemulog
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#./fix_csrs.py "$outDir"
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($customQemu -M virt -nographic -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio -d nochain,cpu,in_asm -serial /dev/null -singlestep -gdb tcp::1236 -S 2>&1 >/dev/null | ./parse_qemu.py | ./parseNew.py | ./remove_dup.awk > allNew2.txt) & riscv64-unknown-elf-gdb -x gdbinit_qemulog
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@ -9,9 +9,10 @@ import sys, fileinput, re
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InstrStartDelim = '=>'
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InstrEndDelim = '-----'
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InputFile = 'noparse.txt'
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#InputFile = 'noparse.txt'
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#InputFile = sys.stdin
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#InputFile = 'temp.txt'
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OutputFile = 'parsedAll.txt'
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#OutputFile = 'parsedAll.txt'
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HUMAN_READABLE = False
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@ -134,67 +135,67 @@ RegNumber = {'zero': 0, 'ra': 1, 'sp': 2, 'gp': 3, 'tp': 4, 't0': 5, 't1': 6, 't
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# initial state
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CurrentInstr = ['0', '0', None, 'other', {'zero': 0, 'ra': 0, 'sp': 0, 'gp': 0, 'tp': 0, 't0': 0, 't1': 0, 't2': 0, 's0': 0, 's1': 0, 'a0': 0, 'a1': 0, 'a2': 0, 'a3': 0, 'a4': 0, 'a5': 0, 'a6': 0, 'a7': 0, 's2': 0, 's3': 0, 's4': 0, 's5': 0, 's6': 0, 's7': 0, 's8': 0, 's9': 0, 's10': 0, 's11': 0, 't3': 0, 't4': 0, 't5': 0, 't6': 0, 'mhartid': 0, 'mstatus': 0, 'mip': 0, 'mie': 0, 'mideleg': 0, 'medeleg': 0, 'mtvec': 0, 'stvec': 0, 'mepc': 0, 'sepc': 0, 'mcause': 0, 'scause': 0, 'mtval': 0, 'stval': 0}, {}, None, None, None]
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with open (InputFile, 'r') as InputFileFP:
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#lines = InputFileFP.readlines()
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lineNum = 0
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StartLine = 0
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EndLine = 0
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#instructions = []
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MemAdr = 0
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lines = []
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for line in InputFileFP:
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lines.insert(lineNum, line)
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if InstrStartDelim in line:
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lineNum = 0
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StartLine = lineNum
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elif InstrEndDelim in line:
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EndLine = lineNum
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(InstrBits, text) = lines[StartLine].split(':')
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InstrBits = int(InstrBits.strip('=> '), 16)
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text = text.strip()
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PC = int(lines[StartLine+1].split(':')[0][2:], 16)
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Regs = toDict(lines[StartLine+2:EndLine])
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(Class, Addr, WriteReg, ReadReg) = whichClass(text, Regs)
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#print("CWR", Class, WriteReg, ReadReg)
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PreviousInstr = CurrentInstr
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#with open (InputFile, 'r') as InputFileFP:
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#lines = InputFileFP.readlines()
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lineNum = 0
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StartLine = 0
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EndLine = 0
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#instructions = []
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MemAdr = 0
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lines = []
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for line in fileinput.input('-'):
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lines.insert(lineNum, line)
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if InstrStartDelim in line:
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lineNum = 0
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StartLine = lineNum
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elif InstrEndDelim in line:
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EndLine = lineNum
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(InstrBits, text) = lines[StartLine].split(':')
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InstrBits = int(InstrBits.strip('=> '), 16)
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text = text.strip()
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PC = int(lines[StartLine+1].split(':')[0][2:], 16)
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Regs = toDict(lines[StartLine+2:EndLine])
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(Class, Addr, WriteReg, ReadReg) = whichClass(text, Regs)
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#print("CWR", Class, WriteReg, ReadReg)
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PreviousInstr = CurrentInstr
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Changed = whatChanged(PreviousInstr[4], Regs)
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Changed = whatChanged(PreviousInstr[4], Regs)
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if (ReadReg !=None): ReadData = ReadReg
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else: ReadData = None
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if (ReadReg !=None): ReadData = ReadReg
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else: ReadData = None
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if (WriteReg !=None): WriteData = WriteReg
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else: WriteData = None
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if (WriteReg !=None): WriteData = WriteReg
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else: WriteData = None
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CurrentInstr = [PC, InstrBits, text, Class, Regs, Changed, Addr, WriteData, ReadData]
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CurrentInstr = [PC, InstrBits, text, Class, Regs, Changed, Addr, WriteData, ReadData]
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#print(CurrentInstr[0:4], PreviousInstr[5], CurrentInstr[6:7], PreviousInstr[8])
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#print(CurrentInstr[0:4], PreviousInstr[5], CurrentInstr[6:7], PreviousInstr[8])
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# pc, instrbits, text and class come from the last line.
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MoveInstrToRegWriteLst = PreviousInstr[0:4]
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# updated registers come from the current line.
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MoveInstrToRegWriteLst.append(CurrentInstr[5]) # destination regs
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# memory address if present comes from the last line.
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MoveInstrToRegWriteLst.append(PreviousInstr[6]) # MemAdrM
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# write data from the previous line
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#MoveInstrToRegWriteLst.append(PreviousInstr[7]) # WriteDataM
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# pc, instrbits, text and class come from the last line.
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MoveInstrToRegWriteLst = PreviousInstr[0:4]
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# updated registers come from the current line.
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MoveInstrToRegWriteLst.append(CurrentInstr[5]) # destination regs
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# memory address if present comes from the last line.
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MoveInstrToRegWriteLst.append(PreviousInstr[6]) # MemAdrM
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# write data from the previous line
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#MoveInstrToRegWriteLst.append(PreviousInstr[7]) # WriteDataM
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if (PreviousInstr[7] != None):
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MoveInstrToRegWriteLst.append(Regs[PreviousInstr[7]]) # WriteDataM
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else:
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MoveInstrToRegWriteLst.append(None)
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if (PreviousInstr[7] != None):
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MoveInstrToRegWriteLst.append(Regs[PreviousInstr[7]]) # WriteDataM
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else:
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MoveInstrToRegWriteLst.append(None)
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# read data from the current line
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#MoveInstrToRegWriteLst.append(PreviousInstr[8]) # ReadDataM
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if (PreviousInstr[8] != None):
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MoveInstrToRegWriteLst.append(Regs[PreviousInstr[8]]) # ReadDataM
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else:
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MoveInstrToRegWriteLst.append(None)
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# read data from the current line
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#MoveInstrToRegWriteLst.append(PreviousInstr[8]) # ReadDataM
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if (PreviousInstr[8] != None):
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MoveInstrToRegWriteLst.append(Regs[PreviousInstr[8]]) # ReadDataM
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else:
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MoveInstrToRegWriteLst.append(None)
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lines.clear()
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#instructions.append(MoveInstrToRegWriteLst)
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PrintInstr(MoveInstrToRegWriteLst, sys.stdout)
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lineNum += 1
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lines.clear()
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#instructions.append(MoveInstrToRegWriteLst)
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PrintInstr(MoveInstrToRegWriteLst, sys.stdout)
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lineNum += 1
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#for instruction in instructions[1::]:
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20
wally-pipelined/linux-testgen/testvector-generation/remove_dup.awk
Executable file
20
wally-pipelined/linux-testgen/testvector-generation/remove_dup.awk
Executable file
@ -0,0 +1,20 @@
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#!/usr/bin/awk -f
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BEGIN{
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old = "first"
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}
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{
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if($1 != old){
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if(old != "first"){
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print oldAll
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}
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}
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old=$1
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oldAll=$0
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}
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END{
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print oldAll
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}
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@ -52,17 +52,12 @@ module csri #(parameter
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always_comb begin
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IntInM = 0;
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IntInM[11] = ExtIntM & ~MIDELEG_REGW[9]; // MEIP
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IntInM[11] = ExtIntM;; // MEIP
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IntInM[9] = ExtIntM & MIDELEG_REGW[9]; // SEIP
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IntInM[7] = TimerIntM & ~MIDELEG_REGW[5]; // MTIP
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IntInM[7] = TimerIntM; // MTIP
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IntInM[5] = TimerIntM & MIDELEG_REGW[5]; // STIP
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IntInM[3] = SwIntM & ~MIDELEG_REGW[1]; // MSIP
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IntInM[3] = SwIntM; // MSIP
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IntInM[1] = SwIntM & MIDELEG_REGW[1]; // SSIP
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/* maybe only machine mode interrupts should be directly triggered:
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IntInM[11] = ExtIntM; // MEIP
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IntInM[7] = TimerIntM; // MTIP
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IntInM[3] = SwIntM; // MSIP
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*/
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end
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// Interrupt Write Enables
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@ -128,7 +128,7 @@ module testbench();
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integer NumCSRMIndex;
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integer NumCSRWIndex;
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integer NumCSRPostWIndex;
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logic CurrentInterruptForce;
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// logic CurrentInterruptForce;
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// -----------
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// Error Macro
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@ -141,11 +141,13 @@ module testbench();
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data_file_all = $fopen({`LINUX_TEST_VECTORS,"all.txt"}, "r");
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end
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/* -----\/----- EXCLUDED -----\/-----
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initial begin
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CurrentInterruptForce = 1'b0;
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end
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-----/\----- EXCLUDED -----/\----- */
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assign checkInstrM = dut.hart.ieu.InstrValidM & ~dut.hart.priv.trap.InstrPageFaultM & ~dut.hart.StallM;
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assign checkInstrM = dut.hart.ieu.InstrValidM & ~dut.hart.priv.trap.InstrPageFaultM & ~dut.hart.priv.trap.InterruptM & ~dut.hart.StallM;
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// trapW will already be invalid in there was an InstrPageFault in the previous instruction.
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assign checkInstrW = dut.hart.ieu.InstrValidW & ~dut.hart.StallW;
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@ -228,6 +230,29 @@ module testbench();
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MarkerIndex += 2;
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// if we get an xcause with the interrupt bit set we must generate an interrupt as interrupts
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// are imprecise. Forcing the trap at this time will allow wally to track what qemu does.
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// the msb of xcause will be set.
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// bits 1:0 select mode; 0 = user, 1 = superviser, 3 = machine
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// bits 3:2 select the type of interrupt, 0 = software, 1 = timer, 2 = external
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if(ExpectedCSRArrayM[NumCSRM].substr(1, 5) == "cause" && (ExpectedCSRArrayValueM[NumCSRM][`XLEN-1] == 1'b1)) begin
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//what type?
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ExpectedIntType = ExpectedCSRArrayValueM[NumCSRM] & 64'h0000_000C;
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$display("%t: CSR = %s. Forcing interrupt of cause = %x", $time, ExpectedCSRArrayM[NumCSRM], ExpectedCSRArrayValueM[NumCSRM]);
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if(ExpectedIntType == 0) begin
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force dut.hart.priv.SwIntM = 1'b1;
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$display("Force SwIntM");
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end
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else if(ExpectedIntType == 4) begin
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force dut.hart.priv.TimerIntM = 1'b1;
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$display("Force TimeIntM");
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end
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else if(ExpectedIntType == 8) begin
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force dut.hart.priv.ExtIntM = 1'b1;
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$display("Force ExtIntM");
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end
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end
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NumCSRM++;
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end
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end
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@ -305,7 +330,18 @@ module testbench();
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//$display("%t: releasing force of ReadDataM.", $time);
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release dut.hart.ieu.dp.ReadDataM;
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end
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// remove forces on interrupts
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for(NumCSRMIndex = 0; NumCSRMIndex < NumCSRM; NumCSRMIndex++) begin
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if(ExpectedCSRArrayM[NumCSRMIndex].substr(1, 5) == "cause" && (ExpectedCSRArrayValueM[NumCSRMIndex][`XLEN-1] == 1'b1)) begin
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//what type?
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$display("%t: Releasing all forces on interrupts", $time);
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release dut.hart.priv.SwIntM;
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release dut.hart.priv.TimerIntM;
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release dut.hart.priv.ExtIntM;
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end
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end
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end
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end
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end
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@ -507,6 +543,7 @@ module testbench();
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end
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endcase // case (ExpectedCSRArrayW[NumCSRPostWIndex])
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/* -----\/----- EXCLUDED -----\/-----
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if(CurrentInterruptForce) begin
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CurrentInterruptForce = 1'b0;
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// remove forces on interrupts
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@ -516,32 +553,8 @@ module testbench();
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release dut.hart.priv.TimerIntM;
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release dut.hart.priv.ExtIntM;
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end
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-----/\----- EXCLUDED -----/\----- */
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// if we get an xcause with the interrupt bit set we must generate an interrupt as interrupts
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// are imprecise. Forcing the trap at this time will allow wally to track what qemu does.
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// the msb of xcause will be set.
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// bits 1:0 select mode; 0 = user, 1 = superviser, 3 = machine
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// bits 3:2 select the type of interrupt, 0 = software, 1 = timer, 2 = external
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if(ExpectedCSRArrayW[NumCSRPostWIndex].substr(1, 5) == "cause" && (ExpectedCSRArrayValueW[NumCSRPostWIndex][`XLEN-1] == 1'b1)) begin
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//what type?
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ExpectedIntType = ExpectedCSRArrayValueW[NumCSRPostWIndex] & 64'h0000_000C;
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$display("%t: CSR = %s. Forcing interrupt of cause = %x", $time, ExpectedCSRArrayW[NumCSRPostWIndex], ExpectedCSRArrayValueW[NumCSRPostWIndex]);
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CurrentInterruptForce = 1'b1;
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if(ExpectedIntType == 0) begin
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force dut.hart.priv.SwIntM = 1'b1;
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$display("Force SwIntM");
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end
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else if(ExpectedIntType == 4) begin
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force dut.hart.priv.TimerIntM = 1'b1;
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$display("Force TimeIntM");
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end
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else if(ExpectedIntType == 8) begin
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force dut.hart.priv.ExtIntM = 1'b1;
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$display("Force ExtIntM");
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end
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end
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end // for (NumCSRPostWIndex = 0; NumCSRPostWIndex < NumCSRW; NumCSRPostWIndex++)
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if (fault == 1) begin
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`ERROR
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