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AMO and LR/SC instructions now working correctly.

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Page table walking is not working.
This commit is contained in:
Ross Thompson 2021-06-25 15:42:07 -05:00
parent a4266c0136
commit 8dfbf60b67
2 changed files with 6 additions and 3 deletions
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4
wally-pipelined/regression/wave.do
View File

@ -283,7 +283,7 @@ add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/MTIMECMP
add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/TimerIntM
add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/SwIntM
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 4} {32648010 ns} 0} {{Cursor 5} {10763646 ns} 0}
WaveRestoreCursors {{Cursor 4} {32648010 ns} 0} {{Cursor 5} {11165332 ns} 0} {{Cursor 3} {7672141 ns} 0}
quietly wave cursor active 2
configure wave -namecolwidth 250
configure wave -valuecolwidth 189
@ -299,4 +299,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {10763302 ns} {10763880 ns}
WaveRestoreZoom {11156770 ns} {11173894 ns}

5
wally-pipelined/src/lsu/lsu.sv
View File

@ -214,9 +214,12 @@ module lsu (
always_comb begin
case (CurrState)
STATE_READY:
if (|AtomicMaskedM) begin
if (AtomicMaskedM[1]) begin
NextState = STATE_FETCH_AMO_1; // *** should be some misalign check
DataStall = 1'b1;
end else if((MemReadM & AtomicM[0]) | (MemWriteM & AtomicM[0])) begin
NextState = STATE_FETCH_AMO_2;
DataStall = 1'b1;
end else if (MemAccessM & ~DataMisalignedM) begin
NextState = STATE_FETCH;
DataStall = 1'b1;