Ross Thompson 5754b5f25f Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main		2021-07-19 12:32:35 -05:00
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bin
config
linux-testgen
misc
ppa
regression	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-07-19 12:32:35 -05:00
src	Fixed a complex bug in the dcache, where back to back loads would lose data on the load before a stall occurred. The solution was to modify the logic for SelAdrM in the dcache so that a stall would cause the SRAM to reread the address in the Memory stage rather than Execution stage. This also required updating the ReadDataWEn control so it is always enabled on ~StallW.	2021-07-19 12:32:16 -05:00
testbench	FDIV and FSQRT passes when simulating in modelsim	2021-07-18 23:00:04 -04:00
testgen
lint-wally