cvw/wally-pipelined
2021-07-04 19:02:56 -04:00
..
bin
config Added ASID & Global PTE handling to TLB CAM 2021-07-04 17:52:00 -04:00
linux-testgen optionally output GDB-formatted instruction list to main buildroot folder 2021-07-03 17:25:19 -04:00
misc
ppa
regression Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-04 16:19:39 -05:00
src Renamed Funct3ToLSU/fromLSU -> SizeToLSU/FromLSU and simplified size muxing in lsuArb 2021-07-04 19:02:56 -04:00
testbench Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang. 2021-07-04 01:19:38 -04:00
testgen mcause test fixes and s-mode interrupt bugfix 2021-06-16 17:37:08 -04:00
lint-wally Merge difficulties 2021-06-07 09:50:23 -04:00