Ross Thompson 2ee97efb9c Fixed a complex bug in the dcache, where back to back loads would lose data on the load before a stall occurred. The solution was to modify the logic for SelAdrM in the dcache so that a stall would cause the SRAM to reread the address in the Memory stage rather than Execution stage. This also required updating the ReadDataWEn control so it is always enabled on ~StallW.		2021-07-19 12:32:16 -05:00
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bin	Icache integrated!	2021-04-26 11:48:58 -05:00
config	Added FLEN, NE, NF to config and started using these in FMA1	2021-07-18 17:28:25 -04:00
linux-testgen	change memread testvectors to not left-shift bytes and half-words	2021-07-18 21:49:53 -04:00
misc	Clean up MMU code	2021-05-14 07:12:32 -04:00
ppa	Config file for ppa experiments	2021-03-25 10:23:21 -05:00
regression	Fixed a complex bug in the dcache, where back to back loads would lose data on the load before a stall occurred. The solution was to modify the logic for SelAdrM in the dcache so that a stall would cause the SRAM to reread the address in the Memory stage rather than Execution stage. This also required updating the ReadDataWEn control so it is always enabled on ~StallW.	2021-07-19 12:32:16 -05:00
src	Fixed a complex bug in the dcache, where back to back loads would lose data on the load before a stall occurred. The solution was to modify the logic for SelAdrM in the dcache so that a stall would cause the SRAM to reread the address in the Memory stage rather than Execution stage. This also required updating the ReadDataWEn control so it is always enabled on ~StallW.	2021-07-19 12:32:16 -05:00
testbench	FDIV and FSQRT passes when simulating in modelsim	2021-07-18 23:00:04 -04:00
testgen	mcause test fixes and s-mode interrupt bugfix	2021-06-16 17:37:08 -04:00
lint-wally	Merge difficulties	2021-06-07 09:50:23 -04:00