Ross Thompson 6134c22aca Split the ReadDataW bus into two parts in preparation for the data cache. On the AHB side it is now HRDATAW and on the CPU to data cache side it is ReadDataW. lsu.sv now handles the connection between the two. ... Also reorganized the inputs and outputs of lsu and pagetablewalker into connects between CPU, pagetablewalker, and AHB. Finally add DisableTranslation to TLB as teh pagetablewalker will need to force no translation when active regardless of the state of SATP. With Kip.		2021-06-23 16:43:22 -05:00
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bin	Icache integrated!	2021-04-26 11:48:58 -05:00
config	Cleaned up fcsr code and added _SUPPORTED to optionally disable peripherals	2021-06-20 22:59:04 -04:00
linux-testgen	change buildroot config to use relative path for testvectors	2021-06-18 22:28:07 -04:00
misc	Clean up MMU code	2021-05-14 07:12:32 -04:00
ppa	Config file for ppa experiments	2021-03-25 10:23:21 -05:00
regression	Reduced complexity of pmpadrdec	2021-06-23 03:03:52 -04:00
src	Split the ReadDataW bus into two parts in preparation for the data cache. On the AHB side it is now HRDATAW and on the CPU to data cache side it is ReadDataW. lsu.sv now handles the connection between the two.	2021-06-23 16:43:22 -05:00
testbench	rv64f FLW passes imperas tests	2021-06-22 16:36:16 -04:00
testgen	mcause test fixes and s-mode interrupt bugfix	2021-06-16 17:37:08 -04:00
lint-wally	Merge difficulties	2021-06-07 09:50:23 -04:00